diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-03-09 15:33:07 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-03-09 15:33:07 -0500 |
| commit | 470051345af2a78425730bd790000530b1b8a1f5 (patch) | |
| tree | d2bdfb09a2cfc4c96a5fcd9c4399610fbf4206a3 /tests/long/se/50.vortex/ref | |
| parent | 9a9a4a0780865dc722b7564ea1c1bf8bacb4e5ce (diff) | |
| download | gem5-470051345af2a78425730bd790000530b1b8a1f5.tar.xz | |
ARM: Update stats for CBNZ fix.
Diffstat (limited to 'tests/long/se/50.vortex/ref')
7 files changed, 601 insertions, 596 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 1d9e3541a..466d8993c 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +148,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -161,7 +161,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -428,7 +428,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -449,7 +449,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -465,11 +465,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -489,8 +489,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -500,7 +500,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -532,7 +533,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -542,5 +544,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 2abcbcd2a..bc6c11a64 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:19:56 -gem5 started Feb 12 2012 20:47:12 +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:25:21 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 30746529500 because target called exit() +Exiting @ tick 30755543500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index a9b05e877..324eff178 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.030747 # Number of seconds simulated -sim_ticks 30746529500 # Number of ticks simulated -final_tick 30746529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.030756 # Number of seconds simulated +sim_ticks 30755543500 # Number of ticks simulated +final_tick 30755543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146131 # Simulator instruction rate (inst/s) -host_op_rate 207370 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63356016 # Simulator tick rate (ticks/s) -host_mem_usage 232084 # Number of bytes of host memory used -host_seconds 485.30 # Real time elapsed on the host -sim_insts 70917047 # Number of instructions simulated -sim_ops 100636295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8680064 # Number of bytes read from this memory -system.physmem.bytes_inst_read 363776 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5661120 # Number of bytes written to this memory -system.physmem.num_reads 135626 # Number of read requests responded to by this memory -system.physmem.num_writes 88455 # Number of write requests responded to by this memory +host_inst_rate 147147 # Simulator instruction rate (inst/s) +host_op_rate 208812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63815156 # Simulator tick rate (ticks/s) +host_mem_usage 235936 # Number of bytes of host memory used +host_seconds 481.95 # Real time elapsed on the host +sim_insts 70917252 # Number of instructions simulated +sim_ops 100636500 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 8681216 # Number of bytes read from this memory +system.physmem.bytes_inst_read 364288 # Number of instructions bytes read from this memory +system.physmem.bytes_written 5661440 # Number of bytes written to this memory +system.physmem.num_reads 135644 # Number of read requests responded to by this memory +system.physmem.num_writes 88460 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 282310366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 11831449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 184122244 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 466432610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 282265082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 11844629 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 184078685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 466343767 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 61493060 # number of cpu cycles simulated +system.cpu.numCycles 61511088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17207683 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11124675 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 739996 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12413226 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8258713 # Number of BTB hits +system.cpu.BPredUnit.lookups 17165899 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 13150342 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 741670 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12130394 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8128680 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1860363 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 182681 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13006035 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87629176 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17207683 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10119076 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21952285 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2766047 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 23185818 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2820 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12232999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 233597 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 60095316 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.044969 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.137732 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1854457 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 183977 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13000354 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87655737 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17165899 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9983137 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21873848 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2772277 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 23278441 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2074 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12226708 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 230090 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 60107424 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.046912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.144766 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 38160956 63.50% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2271093 3.78% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1990023 3.31% 70.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2119724 3.53% 74.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1647401 2.74% 76.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1441763 2.40% 79.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1000150 1.66% 80.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1230223 2.05% 82.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10233983 17.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 38251797 63.64% 63.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2252747 3.75% 67.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1977441 3.29% 70.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2053713 3.42% 74.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1587290 2.64% 76.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1440263 2.40% 79.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 985496 1.64% 80.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1267048 2.11% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10291629 17.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 60095316 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.279831 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.425025 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14817180 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 21950690 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20398412 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1086428 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1842606 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3463605 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108661 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119794628 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 354485 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1842606 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16634867 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1966833 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15615217 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19642472 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4393321 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116600703 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4194 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3033361 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 70 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 116869923 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536821347 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536814358 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6989 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99147741 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17722182 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 787670 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786973 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12493394 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29971388 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22471181 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2503550 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3551864 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111668104 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 780017 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107789312 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 331076 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11606029 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28797672 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 76559 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 60095316 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.793639 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.921516 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 60107424 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.279070 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.425040 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14856562 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 22001240 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20371729 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1031804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1846089 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3466450 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109251 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119897530 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 366577 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1846089 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16668221 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1965297 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15638738 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19567499 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4421580 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116607925 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4528 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3022237 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 40 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 116831766 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536941360 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536932869 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8491 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99148069 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 17683697 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 794887 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 794929 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12663863 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29905745 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22497839 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2550433 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3605599 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111646205 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 783462 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107783359 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 315194 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11596172 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28526322 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 79963 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 60107424 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.793179 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.923398 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21617080 35.97% 35.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11242625 18.71% 54.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8368043 13.92% 68.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7334755 12.21% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4853612 8.08% 88.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3598814 5.99% 94.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1699571 2.83% 97.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 846136 1.41% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 534680 0.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21602316 35.94% 35.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11403464 18.97% 54.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8200759 13.64% 68.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7319332 12.18% 80.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4922118 8.19% 88.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3558954 5.92% 94.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1700735 2.83% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 865239 1.44% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 534507 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 60095316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 60107424 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 104237 3.89% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 1 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1507488 56.31% 60.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1065632 39.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 107169 4.01% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1504678 56.36% 60.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1057992 39.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56897133 52.79% 52.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 88643 0.08% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 206 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29161823 27.05% 79.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21641500 20.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56937666 52.83% 52.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 88934 0.08% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 306 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29100662 27.00% 79.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21655782 20.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107789312 # Type of FU issued -system.cpu.iq.rate 1.752870 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2677358 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024839 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 278681648 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124068735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105618069 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 726 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1184 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 180 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110466305 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 365 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1905391 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107783359 # Type of FU issued +system.cpu.iq.rate 1.752259 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2669841 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024770 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 278658374 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124040880 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105647232 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 803 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1299 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 239 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110452800 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 400 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1897681 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2662397 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4708 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16942 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1913561 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2596713 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5092 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1940178 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 60 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 48 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 61 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1842606 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 954066 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 28419 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112530590 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 448477 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29971388 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22471181 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 763809 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1185 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1150 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16942 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 525308 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 249263 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 774571 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106544172 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28789537 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1245140 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1846089 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 949061 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 28680 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112509386 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 471926 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29905745 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22497839 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 767420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1122 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1174 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17660 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 518600 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 257124 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 775724 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106553535 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28745908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1229824 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 82469 # number of nop insts executed -system.cpu.iew.exec_refs 50119660 # number of memory reference insts executed -system.cpu.iew.exec_branches 14611553 # Number of branches executed -system.cpu.iew.exec_stores 21330123 # Number of stores executed -system.cpu.iew.exec_rate 1.732621 # Inst execution rate -system.cpu.iew.wb_sent 105962456 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105618249 # cumulative count of insts written-back -system.cpu.iew.wb_producers 52610922 # num instructions producing a value -system.cpu.iew.wb_consumers 101691142 # num instructions consuming a value +system.cpu.iew.exec_nop 79719 # number of nop insts executed +system.cpu.iew.exec_refs 50100729 # number of memory reference insts executed +system.cpu.iew.exec_branches 14610772 # Number of branches executed +system.cpu.iew.exec_stores 21354821 # Number of stores executed +system.cpu.iew.exec_rate 1.732265 # Inst execution rate +system.cpu.iew.wb_sent 105985847 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105647471 # cumulative count of insts written-back +system.cpu.iew.wb_producers 52628676 # num instructions producing a value +system.cpu.iew.wb_consumers 101773898 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.717564 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.517360 # average fanout of values written-back +system.cpu.iew.wb_rate 1.717535 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.517114 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 70922599 # The number of committed instructions -system.cpu.commit.commitCommittedOps 100641847 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11889102 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 703458 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 696794 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 58252711 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.727677 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.445395 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 70922804 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100642052 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 11867683 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 703499 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 697454 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 58261336 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.727424 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.444675 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25477544 43.74% 43.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14542293 24.96% 68.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4151131 7.13% 75.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3607676 6.19% 82.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2313094 3.97% 85.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1905802 3.27% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 675667 1.16% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 497156 0.85% 91.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5082348 8.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25494739 43.76% 43.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14514509 24.91% 68.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4165612 7.15% 75.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3613399 6.20% 82.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2299623 3.95% 85.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1924742 3.30% 89.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 677832 1.16% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 500112 0.86% 91.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5070768 8.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 58252711 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70922599 # Number of instructions committed -system.cpu.commit.committedOps 100641847 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 58261336 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70922804 # Number of instructions committed +system.cpu.commit.committedOps 100642052 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47866611 # Number of memory references committed -system.cpu.commit.loads 27308991 # Number of loads committed +system.cpu.commit.refs 47866693 # Number of memory references committed +system.cpu.commit.loads 27309032 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13670510 # Number of branches committed +system.cpu.commit.branches 13670551 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91480315 # Number of committed integer instructions. +system.cpu.commit.int_insts 91480479 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5082348 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5070768 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 165676013 # The number of ROB reads -system.cpu.rob.rob_writes 226913156 # The number of ROB writes -system.cpu.timesIdled 61654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1397744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70917047 # Number of Instructions Simulated -system.cpu.committedOps 100636295 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70917047 # Number of Instructions Simulated -system.cpu.cpi 0.867113 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.867113 # CPI: Total CPI of All Threads -system.cpu.ipc 1.153253 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.153253 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 512941825 # number of integer regfile reads -system.cpu.int_regfile_writes 103506893 # number of integer regfile writes -system.cpu.fp_regfile_reads 822 # number of floating regfile reads -system.cpu.fp_regfile_writes 678 # number of floating regfile writes -system.cpu.misc_regfile_reads 145707136 # number of misc regfile reads -system.cpu.misc_regfile_writes 35604 # number of misc regfile writes -system.cpu.icache.replacements 30139 # number of replacements -system.cpu.icache.tagsinuse 1825.169858 # Cycle average of tags in use -system.cpu.icache.total_refs 12199552 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 32178 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379.127105 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 165675004 # The number of ROB reads +system.cpu.rob.rob_writes 226873042 # The number of ROB writes +system.cpu.timesIdled 61564 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1403664 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70917252 # Number of Instructions Simulated +system.cpu.committedOps 100636500 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70917252 # Number of Instructions Simulated +system.cpu.cpi 0.867364 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.867364 # CPI: Total CPI of All Threads +system.cpu.ipc 1.152918 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.152918 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 512909735 # number of integer regfile reads +system.cpu.int_regfile_writes 103521788 # number of integer regfile writes +system.cpu.fp_regfile_reads 1198 # number of floating regfile reads +system.cpu.fp_regfile_writes 998 # number of floating regfile writes +system.cpu.misc_regfile_reads 145684870 # number of misc regfile reads +system.cpu.misc_regfile_writes 35686 # number of misc regfile writes +system.cpu.icache.replacements 28916 # number of replacements +system.cpu.icache.tagsinuse 1823.894979 # Cycle average of tags in use +system.cpu.icache.total_refs 12194402 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30952 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 393.977837 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1825.169858 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.891196 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.891196 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12199556 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12199556 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12199556 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12199556 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12199556 # number of overall hits -system.cpu.icache.overall_hits::total 12199556 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33443 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33443 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33443 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33443 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33443 # number of overall misses -system.cpu.icache.overall_misses::total 33443 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 390329000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 390329000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 390329000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 390329000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 390329000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 390329000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12232999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12232999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12232999 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12232999 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12232999 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12232999 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002734 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002734 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002734 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11671.470861 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11671.470861 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11671.470861 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1823.894979 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.890574 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.890574 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12194406 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12194406 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12194406 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12194406 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12194406 # number of overall hits +system.cpu.icache.overall_hits::total 12194406 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 32302 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 32302 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 32302 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 32302 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 32302 # number of overall misses +system.cpu.icache.overall_misses::total 32302 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 385546000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 385546000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 385546000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 385546000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 385546000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 385546000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12226708 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12226708 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12226708 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12226708 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12226708 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12226708 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002642 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002642 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002642 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11935.669618 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11935.669618 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11935.669618 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,224 +382,224 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1227 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1227 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1227 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1227 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1227 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1227 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32216 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 32216 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 32216 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 32216 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 32216 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 32216 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262568000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 262568000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262568000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 262568000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262568000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 262568000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002634 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8150.235908 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8150.235908 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8150.235908 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1300 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1300 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1300 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1300 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1300 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1300 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31002 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31002 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31002 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31002 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31002 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31002 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 260426000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 260426000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 260426000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 260426000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 260426000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 260426000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8400.296755 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8400.296755 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8400.296755 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158787 # number of replacements -system.cpu.dcache.tagsinuse 4071.855025 # Cycle average of tags in use -system.cpu.dcache.total_refs 44862936 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162883 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 275.430438 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 309114000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4071.855025 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26515454 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26515454 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18310363 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18310363 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 19173 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 19173 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 17801 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 17801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44825817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44825817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44825817 # number of overall hits -system.cpu.dcache.overall_hits::total 44825817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 110570 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 110570 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1539538 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1539538 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1650108 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1650108 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1650108 # number of overall misses -system.cpu.dcache.overall_misses::total 1650108 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2444111000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2444111000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 52524497000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 52524497000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 460000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 460000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54968608000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54968608000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54968608000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54968608000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26626024 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26626024 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 158739 # number of replacements +system.cpu.dcache.tagsinuse 4072.206882 # Cycle average of tags in use +system.cpu.dcache.total_refs 44824724 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162835 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 275.276961 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 306509000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.206882 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994191 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994191 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26477714 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26477714 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18310173 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18310173 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 18862 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 18862 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 17842 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 17842 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44787887 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44787887 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44787887 # number of overall hits +system.cpu.dcache.overall_hits::total 44787887 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 109145 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 109145 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1539728 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1539728 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 32 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 32 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1648873 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1648873 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1648873 # number of overall misses +system.cpu.dcache.overall_misses::total 1648873 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2419748500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2419748500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 52564184000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 52564184000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 414000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 414000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54983932500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54983932500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54983932500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54983932500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26586859 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26586859 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19208 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 19208 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 17801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 17801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46475925 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46475925 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46475925 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46475925 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004153 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077559 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001822 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035505 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035505 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22104.648639 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34117.051349 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13142.857143 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33312.127449 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33312.127449 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18894 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18894 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 17842 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 17842 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46436760 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46436760 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46436760 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46436760 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004105 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077569 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001694 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035508 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035508 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22170.035274 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34138.616691 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12937.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33346.372037 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33346.372037 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 210500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 199000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19136.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19900 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123777 # number of writebacks -system.cpu.dcache.writebacks::total 123777 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54544 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54544 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432641 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1432641 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1487185 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1487185 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1487185 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1487185 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56026 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 56026 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106897 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 106897 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162923 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162923 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162923 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162923 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1045999000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1045999000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3665143000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3665143000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4711142000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4711142000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4711142000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4711142000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003506 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003506 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18669.885410 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34286.677830 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28916.371537 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28916.371537 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 123771 # number of writebacks +system.cpu.dcache.writebacks::total 123771 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 53183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432805 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1432805 # 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Cycle average of tags in use -system.cpu.l2cache.total_refs 77246 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 134234 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.575458 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 115379 # number of replacements +system.cpu.l2cache.tagsinuse 18377.888131 # Cycle average of tags in use +system.cpu.l2cache.total_refs 75936 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 134247 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.565644 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15926.417770 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 869.276792 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1584.362140 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.486036 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55926 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 86876 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 123771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 123771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 50 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 50 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 106909 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 106909 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 30950 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 162835 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 193785 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 30950 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 162835 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 193785 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.184653 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.490380 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959648 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.184653 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.798477 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.184653 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.798477 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34240.594926 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34230.082042 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 871.794872 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34291.851455 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34240.594926 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.822489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34240.594926 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.822489 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -608,59 +608,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88455 # number of writebacks -system.cpu.l2cache.writebacks::total 88455 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 88460 # number of writebacks +system.cpu.l2cache.writebacks::total 88460 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 23 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5684 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27361 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33045 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 29 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102581 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102581 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5684 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 129942 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 135626 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5684 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 129942 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 135626 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176568000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 850424500 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 4220605000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488677 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959661 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797763 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.176664 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31064.039409 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31081.630788 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31068.965517 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31132.592780 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31064.039409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31121.862062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31064.039409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31121.862062 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 90 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5692 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 33050 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102595 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102595 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5692 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 129953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 135645 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5692 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 129953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 135645 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176784500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 850283000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027067500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1211000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1211000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3193896000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3193896000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4044179000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4220963500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4044179000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4220963500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.489182 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959648 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.798066 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.798066 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31058.415320 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31079.866949 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31051.282051 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31131.107754 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31058.415320 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31120.320424 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31058.415320 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31120.320424 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index e57dda708..fc20c8ede 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -71,7 +71,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[5] +port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts @@ -87,7 +87,7 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.membus.port[4] +port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer @@ -119,7 +119,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory @@ -129,5 +130,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 89b488ea9..34e49ce66 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932162000 # Number of ticks simulated final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2464229 # Simulator instruction rate (inst/s) -host_op_rate 3496968 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1874136829 # Simulator tick rate (ticks/s) -host_mem_usage 220180 # Number of bytes of host memory used -host_seconds 28.78 # Real time elapsed on the host +host_inst_rate 2398112 # Simulator instruction rate (inst/s) +host_op_rate 3403143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1823852749 # Simulator tick rate (ticks/s) +host_mem_usage 223920 # Number of bytes of host memory used +host_seconds 29.57 # Real time elapsed on the host sim_insts 70913189 # Number of instructions simulated sim_ops 100632437 # Number of ops (including micro ops) simulated system.physmem.bytes_read 419153654 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 100632437 # Nu system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 10735849 # number of instructions that are conditional controls system.cpu.num_int_insts 91472788 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index a85bd162d..69f507d60 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -26,7 +26,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +80,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -93,11 +93,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -118,7 +118,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -134,11 +134,11 @@ type=ArmTableWalker max_backoff=100000 min_backoff=0 sys=system -port=system.cpu.toL2Bus.port[2] +port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -158,8 +158,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[4] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -169,7 +169,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -201,7 +202,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -211,5 +213,5 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 0f7cee094..37dcac738 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133117 # Nu sim_ticks 133117442000 # Number of ticks simulated final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1269489 # Simulator instruction rate (inst/s) -host_op_rate 1800168 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2401339947 # Simulator tick rate (ticks/s) -host_mem_usage 229088 # Number of bytes of host memory used -host_seconds 55.43 # Real time elapsed on the host +host_inst_rate 1310173 # Simulator instruction rate (inst/s) +host_op_rate 1857860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2478297620 # Simulator tick rate (ticks/s) +host_mem_usage 232836 # Number of bytes of host memory used +host_seconds 53.71 # Real time elapsed on the host sim_insts 70373636 # Number of instructions simulated sim_ops 99791663 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8570688 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 99791663 # Nu system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 10735849 # number of instructions that are conditional controls system.cpu.num_int_insts 91472788 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read |