diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/long/se/50.vortex/ref | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/long/se/50.vortex/ref')
6 files changed, 1955 insertions, 1955 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 361b9fcbc..1f592bc6b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.047911 # Number of seconds simulated -sim_ticks 47910588500 # Number of ticks simulated -final_tick 47910588500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.046793 # Number of seconds simulated +sim_ticks 46793182500 # Number of ticks simulated +final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102205 # Simulator instruction rate (inst/s) -host_op_rate 102205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55429613 # Simulator tick rate (ticks/s) -host_mem_usage 227308 # Number of bytes of host memory used -host_seconds 864.35 # Real time elapsed on the host +host_inst_rate 59681 # Simulator instruction rate (inst/s) +host_op_rate 59681 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31612654 # Simulator tick rate (ticks/s) +host_mem_usage 227600 # Number of bytes of host memory used +host_seconds 1480.20 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 515328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10272960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10788288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 515328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 515328 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10272832 # Number of bytes read from this memory +system.physmem.bytes_read::total 10787712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 514880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 514880 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160515 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168567 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 8045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160513 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168558 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10756036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 214419408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 225175443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10756036 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10756036 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 154921913 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 154921913 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 154921913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10756036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 214419408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380097356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 11003312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 219536938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 230540250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11003312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11003312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 158621397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 158621397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 158621397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11003312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 219536938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 389161648 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -42,18 +42,18 @@ system.cpu.dtb.read_hits 20277225 # DT system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 20367373 # DTB read accesses -system.cpu.dtb.write_hits 14736863 # DTB write hits +system.cpu.dtb.write_hits 14736820 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14744115 # DTB write accesses -system.cpu.dtb.data_hits 35014088 # DTB hits +system.cpu.dtb.write_accesses 14744072 # DTB write accesses +system.cpu.dtb.data_hits 35014045 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111488 # DTB accesses -system.cpu.itb.fetch_hits 12475946 # ITB hits -system.cpu.itb.fetch_misses 12952 # ITB misses +system.cpu.dtb.data_accesses 35111445 # DTB accesses +system.cpu.itb.fetch_hits 12477645 # ITB hits +system.cpu.itb.fetch_misses 12958 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12488898 # ITB accesses +system.cpu.itb.fetch_accesses 12490603 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 95821178 # number of cpu cycles simulated +system.cpu.numCycles 93586366 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18829757 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12442338 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5025331 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16200752 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5042995 # Number of BTB hits +system.cpu.branch_predictor.lookups 18829185 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12442057 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5026145 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16204746 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5047870 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1660949 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.128154 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8471214 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10358543 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74332888 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 1031 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 31.150565 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8475762 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10353423 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74332851 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126652138 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65238 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126652101 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65265 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292868 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14120784 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064786 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4680831 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 234000 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4914831 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8857404 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.686517 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44775821 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292895 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14120054 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064610 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4681911 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 233734 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4915645 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8856618 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.692355 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44775927 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78582835 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78075293 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 467389 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25530263 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70290915 # Number of cycles cpu stages are processed. -system.cpu.activity 73.356346 # Percentage of cycles cpu is active +system.cpu.timesIdled 311800 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23300937 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70285429 # Number of cycles cpu stages are processed. +system.cpu.activity 75.102210 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.084678 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.059380 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.084678 # CPI: Total CPI of All Threads -system.cpu.ipc 0.921933 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.059380 # CPI: Total CPI of All Threads +system.cpu.ipc 0.943948 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.921933 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 42394050 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53427128 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 55.757119 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 53163082 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42658096 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 44.518442 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 52694545 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43126633 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.007413 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 73699998 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22121180 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.085899 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 49718969 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46102209 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 48.112755 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85335 # number of replacements -system.cpu.icache.tagsinuse 1885.674638 # Cycle average of tags in use -system.cpu.icache.total_refs 12357256 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87381 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.418111 # Average number of references to valid blocks. +system.cpu.ipc_total 0.943948 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 40161098 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53425268 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 57.086593 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 50931554 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42654812 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.578019 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 50461046 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43125320 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 46.080772 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 71466223 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120143 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.636074 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47482076 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46104290 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 49.263896 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85221 # number of replacements +system.cpu.icache.tagsinuse 1887.407088 # Cycle average of tags in use +system.cpu.icache.total_refs 12359392 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87267 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.627328 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1885.674638 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.920740 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.920740 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12357256 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12357256 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12357256 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12357256 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12357256 # number of overall hits -system.cpu.icache.overall_hits::total 12357256 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118639 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118639 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118639 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118639 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118639 # number of overall misses -system.cpu.icache.overall_misses::total 118639 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081863500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2081863500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2081863500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2081863500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2081863500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2081863500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12475895 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12475895 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12475895 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12475895 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12475895 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12475895 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009509 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009509 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009509 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009509 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009509 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009509 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.884760 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17547.884760 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17547.884760 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17547.884760 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1887.407088 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.921585 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.921585 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12359392 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12359392 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12359392 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12359392 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12359392 # number of overall hits +system.cpu.icache.overall_hits::total 12359392 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118206 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118206 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118206 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118206 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118206 # number of overall misses +system.cpu.icache.overall_misses::total 118206 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1871587000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1871587000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1871587000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1871587000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1871587000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1871587000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12477598 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12477598 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12477598 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12477598 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12477598 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12477598 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15833.265655 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15833.265655 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15833.265655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15833.265655 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1176500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1025000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 105 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 94 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 11204.761905 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 10904.255319 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31258 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 31258 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 31258 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 31258 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 31258 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 31258 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87381 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87381 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87381 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87381 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87381 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87381 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364888000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1364888000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364888000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1364888000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364888000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1364888000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007004 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007004 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.963150 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.963150 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30939 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30939 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30939 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30939 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30939 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30939 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87267 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87267 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87267 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87267 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87267 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87267 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1309592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1309592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1309592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1309592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1309592500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1309592500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006994 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006994 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006994 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15006.732213 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15006.732213 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.238819 # Cycle average of tags in use -system.cpu.dcache.total_refs 34125947 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4072.865489 # Cycle average of tags in use +system.cpu.dcache.total_refs 34126021 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.999990 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 499859000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.238819 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994443 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994443 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180530 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945417 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945417 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34125947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34125947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34125947 # number of overall hits -system.cpu.dcache.overall_hits::total 34125947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96108 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96108 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667960 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667960 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 764068 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 764068 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 764068 # number of overall misses -system.cpu.dcache.overall_misses::total 764068 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4228645000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 42089863000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 42089863000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46318508000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46318508000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46318508000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46318508000 # number of overall miss cycles +system.cpu.dcache.avg_refs 167.000352 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 486992000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.865489 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994352 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994352 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180532 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180532 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945489 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945489 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34126021 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34126021 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34126021 # number of overall hits +system.cpu.dcache.overall_hits::total 34126021 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96106 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96106 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667888 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667888 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 763994 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 763994 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 763994 # number of overall misses +system.cpu.dcache.overall_misses::total 763994 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3881207000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3881207000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 34562623000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 34562623000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38443830000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38443830000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38443830000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38443830000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045709 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045709 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.886669 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.886669 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63012.550153 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63012.550153 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60620.923792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60620.923792 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045704 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045704 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021897 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021897 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40384.648201 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40384.648201 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51749.130094 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51749.130094 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50319.544394 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50319.544394 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6946123500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6260683500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124169 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124119 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 55940.882990 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50440.975999 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 165805 # number of writebacks -system.cpu.dcache.writebacks::total 165805 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35341 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35341 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524380 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524380 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559721 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559721 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559721 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559721 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 165811 # number of writebacks +system.cpu.dcache.writebacks::total 165811 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35339 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35339 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524308 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524308 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559647 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559647 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559647 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559647 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1936845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1936845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7870166500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7870166500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9807011500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9807011500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9807011500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9807011500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1916080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1916080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7177771000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7177771000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9093851000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9093851000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9093851000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9093851000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -318,98 +318,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31873.302944 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31873.302944 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54813.807633 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54813.807633 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31531.587868 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31531.587868 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49991.440312 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49991.440312 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44502.003944 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44502.003944 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44502.003944 # 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number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 25348.854435 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1730.144008 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1731.788804 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.773586 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052800 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.052850 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.879235 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 79222 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31112 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 110334 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 165811 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 165811 # 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mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911511 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785502 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.577822 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785502 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.577822 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40878.539493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40093.613194 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40262.067219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40106.060375 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40106.060375 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.578018 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.578018 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40934.369173 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40104.136971 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40282.197222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40232.698955 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40232.698955 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index e1fb122e9..dcb5671a4 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021620 # Number of seconds simulated -sim_ticks 21619627000 # Number of ticks simulated -final_tick 21619627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021083 # Number of seconds simulated +sim_ticks 21083079000 # Number of ticks simulated +final_tick 21083079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 209503 # Simulator instruction rate (inst/s) -host_op_rate 209503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56907639 # Simulator tick rate (ticks/s) -host_mem_usage 228332 # Number of bytes of host memory used -host_seconds 379.91 # Real time elapsed on the host +host_inst_rate 162660 # Simulator instruction rate (inst/s) +host_op_rate 162660 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43087037 # Simulator tick rate (ticks/s) +host_mem_usage 228624 # Number of bytes of host memory used +host_seconds 489.31 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 559680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10295552 # Number of bytes read from this memory -system.physmem.bytes_read::total 10855232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 559680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 559680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7426432 # Number of bytes written to this memory -system.physmem.bytes_written::total 7426432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160868 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169613 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116038 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116038 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25887588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476213211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 502100799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25887588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25887588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 343504169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 343504169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 343504169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25887588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476213211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845604968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 559552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10295232 # Number of bytes read from this memory +system.physmem.bytes_read::total 10854784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 559552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 559552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7426304 # Number of bytes written to this memory +system.physmem.bytes_written::total 7426304 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8743 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160863 # Number of read requests responded to by this memory +system.physmem.num_reads::total 169606 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116036 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116036 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 26540336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 488317290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 514857626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 26540336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 26540336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 352240012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 352240012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 352240012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 26540336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 488317290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 867097638 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22478221 # DTB read hits -system.cpu.dtb.read_misses 218727 # DTB read misses -system.cpu.dtb.read_acv 49 # DTB read access violations -system.cpu.dtb.read_accesses 22696948 # DTB read accesses -system.cpu.dtb.write_hits 15797623 # DTB write hits -system.cpu.dtb.write_misses 42281 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 15839904 # DTB write accesses -system.cpu.dtb.data_hits 38275844 # DTB hits -system.cpu.dtb.data_misses 261008 # DTB misses -system.cpu.dtb.data_acv 51 # DTB access violations -system.cpu.dtb.data_accesses 38536852 # DTB accesses -system.cpu.itb.fetch_hits 14126153 # ITB hits -system.cpu.itb.fetch_misses 38209 # ITB misses +system.cpu.dtb.read_hits 22489278 # DTB read hits +system.cpu.dtb.read_misses 215924 # DTB read misses +system.cpu.dtb.read_acv 41 # DTB read access violations +system.cpu.dtb.read_accesses 22705202 # DTB read accesses +system.cpu.dtb.write_hits 15793400 # DTB write hits +system.cpu.dtb.write_misses 42287 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 15835687 # DTB write accesses +system.cpu.dtb.data_hits 38282678 # DTB hits +system.cpu.dtb.data_misses 258211 # DTB misses +system.cpu.dtb.data_acv 41 # DTB access violations +system.cpu.dtb.data_accesses 38540889 # DTB accesses +system.cpu.itb.fetch_hits 14126698 # ITB hits +system.cpu.itb.fetch_misses 39196 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14164362 # ITB accesses +system.cpu.itb.fetch_accesses 14165894 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,245 +67,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 43239256 # number of cpu cycles simulated +system.cpu.numCycles 42166161 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16713940 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10785641 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 474517 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12148042 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7471828 # Number of BTB hits +system.cpu.BPredUnit.lookups 16730416 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10797894 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 473008 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12422807 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7474415 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1996046 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44341 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15442173 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106653150 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16713940 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9467874 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19795691 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2142333 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5738431 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8227 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 318072 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14126153 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 221095 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42854841 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.488707 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.154001 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1997304 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44664 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15021331 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106728114 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16730416 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9471719 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19806820 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2130939 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5131628 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8233 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 318680 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14126698 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 218104 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 41829396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.551510 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.168900 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23059150 53.81% 53.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1544639 3.60% 57.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1408806 3.29% 60.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1522467 3.55% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4195710 9.79% 74.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1864977 4.35% 78.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 685640 1.60% 79.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1085683 2.53% 82.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7487769 17.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22022576 52.65% 52.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1548600 3.70% 56.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1408416 3.37% 59.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1521519 3.64% 63.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4198220 10.04% 73.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1858565 4.44% 77.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 685862 1.64% 79.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1087856 2.60% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7497782 17.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42854841 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.386546 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.466582 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16604436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5227614 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18845700 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 731163 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1445928 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3801623 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109086 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104782719 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304838 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1445928 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17078558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2955442 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 82947 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19068517 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2223449 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103359605 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 254 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 47854 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2072460 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62291613 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124619411 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124164571 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 454840 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 41829396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.396774 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.531132 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16130863 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4679035 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18837705 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 745587 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1436206 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3804156 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108982 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104831583 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305633 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1436206 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16616599 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2463979 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 82005 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19040737 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2189870 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103389139 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 244 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14351 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2051944 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62312738 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124671441 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124212160 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 459281 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9744732 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5573 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5571 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4558890 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23363714 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16388828 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1131841 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 391237 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91420984 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5434 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89018152 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 120887 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11240273 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4901766 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 851 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42854841 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.077202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.113927 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9765857 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5555 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5551 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4525057 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23373120 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16387776 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1111175 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 372431 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91431067 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5402 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89032304 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 124930 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11266116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4904200 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 819 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 41829396 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.128463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.117137 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 14370838 33.53% 33.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7100087 16.57% 50.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5540527 12.93% 63.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4772141 11.14% 74.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4704722 10.98% 85.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2673915 6.24% 91.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1941470 4.53% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1325823 3.09% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 425318 0.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13456265 32.17% 32.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6919123 16.54% 48.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5589725 13.36% 62.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4803253 11.48% 73.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4671765 11.17% 84.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2679732 6.41% 91.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1951840 4.67% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1334332 3.19% 98.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 423361 1.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42854841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 41829396 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 128315 6.76% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 799448 42.10% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 971123 51.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 128041 6.73% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 804964 42.29% 49.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 970251 50.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49717774 55.85% 55.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43792 0.05% 55.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49721701 55.85% 55.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43788 0.05% 55.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 120893 0.14% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121944 0.14% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38928 0.04% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22969813 25.80% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16004865 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121439 0.14% 56.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 86 0.00% 56.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 122461 0.14% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38932 0.04% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22979273 25.81% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16004570 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89018152 # Type of FU issued -system.cpu.iq.rate 2.058735 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1898886 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222303440 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102266391 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86984314 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 607478 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 416601 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 296142 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90613228 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 303810 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1449481 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89032304 # Type of FU issued +system.cpu.iq.rate 2.111463 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1903256 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021377 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221310686 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102298169 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86978851 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420531 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 298097 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90629664 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305896 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1444097 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3087076 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5237 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1775451 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3096482 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5652 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17147 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1774399 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2459 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2494 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 46 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1445928 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1740049 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 88499 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100965460 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 244137 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23363714 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16388828 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5434 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 53254 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 431 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17226 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250564 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 172705 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 423269 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88055069 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22700407 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 963083 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1436206 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1444549 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 56493 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100968085 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 243573 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23373120 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16387776 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5402 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48618 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 436 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17147 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 252218 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 171298 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423516 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88057641 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22708636 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 974663 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9539042 # number of nop insts executed -system.cpu.iew.exec_refs 38540674 # number of memory reference insts executed -system.cpu.iew.exec_branches 15139519 # Number of branches executed -system.cpu.iew.exec_stores 15840267 # Number of stores executed -system.cpu.iew.exec_rate 2.036461 # Inst execution rate -system.cpu.iew.wb_sent 87694134 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87280456 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33430607 # num instructions producing a value -system.cpu.iew.wb_consumers 43860363 # num instructions consuming a value +system.cpu.iew.exec_nop 9531616 # number of nop insts executed +system.cpu.iew.exec_refs 38544729 # number of memory reference insts executed +system.cpu.iew.exec_branches 15136263 # Number of branches executed +system.cpu.iew.exec_stores 15836093 # Number of stores executed +system.cpu.iew.exec_rate 2.088349 # Inst execution rate +system.cpu.iew.wb_sent 87691296 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87276948 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33460873 # num instructions producing a value +system.cpu.iew.wb_consumers 43882648 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.018547 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762205 # average fanout of values written-back +system.cpu.iew.wb_rate 2.069834 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762508 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9526459 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9477917 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 368198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 41408913 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.133373 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.803824 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 366510 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 40393190 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.187019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.818394 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18342699 44.30% 44.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7125223 17.21% 61.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3513214 8.48% 69.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2087650 5.04% 75.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2070192 5.00% 80.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1179714 2.85% 82.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1132729 2.74% 85.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 709577 1.71% 87.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5247915 12.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17375613 43.02% 43.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7063647 17.49% 60.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3493568 8.65% 69.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2102678 5.21% 74.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2090838 5.18% 79.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1172557 2.90% 82.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1137405 2.82% 85.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 723784 1.79% 87.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5233100 12.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 41408913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 40393190 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5247915 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5233100 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132710787 # The number of ROB reads -system.cpu.rob.rob_writes 197183581 # The number of ROB writes -system.cpu.timesIdled 23387 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 384415 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 131661337 # The number of ROB reads +system.cpu.rob.rob_writes 197076783 # The number of ROB writes +system.cpu.timesIdled 11011 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 336765 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.543263 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.543263 # CPI: Total CPI of All Threads -system.cpu.ipc 1.840729 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.840729 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116590843 # number of integer regfile reads -system.cpu.int_regfile_writes 57851456 # number of integer regfile writes -system.cpu.fp_regfile_reads 250950 # number of floating regfile reads -system.cpu.fp_regfile_writes 240941 # number of floating regfile writes -system.cpu.misc_regfile_reads 38077 # number of misc regfile reads +system.cpu.cpi 0.529781 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.529781 # CPI: Total CPI of All Threads +system.cpu.ipc 1.887574 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.887574 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116593496 # number of integer regfile reads +system.cpu.int_regfile_writes 57858579 # number of integer regfile writes +system.cpu.fp_regfile_reads 252858 # number of floating regfile reads +system.cpu.fp_regfile_writes 241901 # number of floating regfile writes +system.cpu.misc_regfile_reads 38310 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 92836 # number of replacements -system.cpu.icache.tagsinuse 1929.378925 # Cycle average of tags in use -system.cpu.icache.total_refs 14026889 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 94884 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.831974 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18060721000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1929.378925 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942080 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942080 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14026889 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14026889 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14026889 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14026889 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14026889 # number of overall hits -system.cpu.icache.overall_hits::total 14026889 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 99264 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 99264 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 99264 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 99264 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 99264 # number of overall misses -system.cpu.icache.overall_misses::total 99264 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1029034500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1029034500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1029034500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1029034500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1029034500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1029034500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14126153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14126153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14126153 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14126153 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14126153 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14126153 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007027 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007027 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007027 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007027 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10366.643496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10366.643496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10366.643496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10366.643496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10366.643496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10366.643496 # average overall miss latency +system.cpu.icache.replacements 94995 # number of replacements +system.cpu.icache.tagsinuse 1931.010955 # Cycle average of tags in use +system.cpu.icache.total_refs 14025954 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 97043 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 144.533392 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 17649756000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1931.010955 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942876 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942876 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14025954 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14025954 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14025954 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14025954 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14025954 # number of overall hits +system.cpu.icache.overall_hits::total 14025954 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 100744 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 100744 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 100744 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 100744 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 100744 # number of overall misses +system.cpu.icache.overall_misses::total 100744 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 779635000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 779635000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 779635000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 779635000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 779635000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 779635000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14126698 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14126698 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14126698 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14126698 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14126698 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14126698 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007131 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007131 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007131 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007131 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007131 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007131 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7738.773525 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 7738.773525 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7738.773525 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 7738.773525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7738.773525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 7738.773525 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,286 +388,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4379 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4379 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4379 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4379 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4379 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4379 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94885 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 94885 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 94885 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 94885 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 94885 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 94885 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 637176500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 637176500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 637176500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 637176500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 637176500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 637176500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006717 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006717 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006717 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6715.250040 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6715.250040 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6715.250040 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6715.250040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6715.250040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6715.250040 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3700 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3700 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3700 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3700 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3700 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3700 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 97044 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 97044 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 97044 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 97044 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 97044 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 97044 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 497811000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 497811000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 497811000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 497811000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 497811000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 497811000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006870 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006870 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006870 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006870 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006870 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5129.745270 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5129.745270 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5129.745270 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5129.745270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5129.745270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5129.745270 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201660 # number of replacements -system.cpu.dcache.tagsinuse 4075.950117 # Cycle average of tags in use -system.cpu.dcache.total_refs 34352002 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205756 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.955044 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 168155000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4075.950117 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995105 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995105 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20774603 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20774603 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13577332 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13577332 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 67 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 67 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34351935 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34351935 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34351935 # number of overall hits -system.cpu.dcache.overall_hits::total 34351935 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 251586 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 251586 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1036045 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1036045 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1287631 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1287631 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1287631 # number of overall misses -system.cpu.dcache.overall_misses::total 1287631 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8533517000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8533517000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 45981514500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45981514500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54515031500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54515031500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54515031500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54515031500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21026189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21026189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201505 # number of replacements +system.cpu.dcache.tagsinuse 4076.313431 # Cycle average of tags in use +system.cpu.dcache.total_refs 34371357 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205601 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.175048 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 155296000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.313431 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995194 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995194 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20790228 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20790228 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13581056 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13581056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 73 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 73 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34371284 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34371284 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34371284 # number of overall hits +system.cpu.dcache.overall_hits::total 34371284 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 252353 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 252353 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1032321 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1032321 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1284674 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1284674 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1284674 # number of overall misses +system.cpu.dcache.overall_misses::total 1284674 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7773688500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7773688500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39504948500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39504948500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 47278637000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 47278637000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 47278637000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 47278637000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21042581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21042581 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35639566 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35639566 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35639566 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35639566 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011965 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011965 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070897 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.070897 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036129 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036129 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036129 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33918.886584 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33918.886584 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44381.773475 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44381.773475 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42337.464305 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42337.464305 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42337.464305 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42337.464305 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 96000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5647.058824 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 73 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 73 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35655958 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35655958 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35655958 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35655958 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011992 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011992 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070642 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.070642 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036030 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036030 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036030 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036030 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30804.819043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30804.819043 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38268.085702 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38268.085702 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36802.050170 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36802.050170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36802.050170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36802.050170 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 90500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6033.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 166377 # number of writebacks -system.cpu.dcache.writebacks::total 166377 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 189261 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 189261 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 892614 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 892614 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1081875 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1081875 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1081875 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1081875 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62325 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62325 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143431 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143431 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205756 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205756 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205756 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205756 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1244348500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1244348500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5521425000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5521425000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6765773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6765773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6765773500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6765773500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002964 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002964 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 166256 # number of writebacks +system.cpu.dcache.writebacks::total 166256 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 190181 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 190181 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 888892 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 888892 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1079073 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1079073 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1079073 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1079073 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62172 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62172 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143429 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143429 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205601 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205601 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205601 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205601 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1152797500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1152797500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5564302000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5564302000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6717099500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6717099500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6717099500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6717099500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002955 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002955 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005773 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005773 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005773 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005773 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19965.479342 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19965.479342 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38495.339222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38495.339222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32882.508894 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32882.508894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32882.508894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32882.508894 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005766 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005766 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005766 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005766 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18542.068777 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18542.068777 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38794.818342 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38794.818342 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32670.558509 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32670.558509 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32670.558509 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32670.558509 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 137206 # number of replacements -system.cpu.l2cache.tagsinuse 29113.613445 # Cycle average of tags in use -system.cpu.l2cache.total_refs 155241 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 168083 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.923597 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 137202 # number of replacements +system.cpu.l2cache.tagsinuse 29157.346540 # Cycle average of tags in use +system.cpu.l2cache.total_refs 157131 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 168078 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.934870 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25325.507446 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1911.510034 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1876.595965 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.772873 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.058335 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.057269 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.888477 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 86140 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32424 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 118564 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 166377 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 166377 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12464 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12464 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 86140 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 44888 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 131028 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 86140 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 44888 # number of overall hits -system.cpu.l2cache.overall_hits::total 131028 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8745 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 29899 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 38644 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130969 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.242692 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913094 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913094 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.090093 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782404 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.560412 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.090093 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782404 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.560412 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32460.825803 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32288.373415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32327.393892 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38170.193027 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38170.193027 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32460.825803 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37077.034495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36839.074089 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32460.825803 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37077.034495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36839.074089 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 5c01fa696..456c7f9d2 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.134581 # Number of seconds simulated -sim_ticks 134581343000 # Number of ticks simulated -final_tick 134581343000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133756 # Number of seconds simulated +sim_ticks 133756135000 # Number of ticks simulated +final_tick 133756135000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1566292 # Simulator instruction rate (inst/s) -host_op_rate 1566291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2386143258 # Simulator tick rate (ticks/s) -host_mem_usage 226128 # Number of bytes of host memory used -host_seconds 56.40 # Real time elapsed on the host +host_inst_rate 1270571 # Simulator instruction rate (inst/s) +host_op_rate 1270570 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1923763163 # Simulator tick rate (ticks/s) +host_mem_usage 227600 # Number of bytes of host memory used +host_seconds 69.53 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 160477 # Nu system.physmem.num_reads::total 168060 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115955 # Number of write requests responded to by this memory system.physmem.num_writes::total 115955 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3606087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 76314649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 79920736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3606087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3606087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 55142264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55142264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55142264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3606087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 76314649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 135063001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3628335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 76785472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 80413807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3628335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3628335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55482464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55482464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55482464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3628335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 76785472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 135896271 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 269162686 # number of cpu cycles simulated +system.cpu.numCycles 267512270 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 269162686 # Number of busy cycles +system.cpu.num_busy_cycles 267512270 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.699205 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.674409 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.699205 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913916 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913916 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1871.674409 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.913904 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.913904 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1390813000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1390813000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1390813000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1390813000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1390813000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1390813000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312229000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1312229000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1312229000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1312229000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1312229000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1312229000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18195.784709 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18195.784709 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18195.784709 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18195.784709 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18195.784709 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18195.784709 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17167.682767 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17167.682767 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17167.682767 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17167.682767 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1161505000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1161505000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1161505000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1161505000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1161505000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1161505000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1159357000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1159357000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1159357000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1159357000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1159357000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1159357000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15195.784709 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15195.784709 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15195.784709 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15195.784709 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15195.784709 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15195.784709 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15167.682767 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15167.682767 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.801621 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.879185 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 947396000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.801621 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995801 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995801 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4078.879185 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995820 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995820 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2092728000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2092728000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7513894000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7513894000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9606622000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9606622000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9606622000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9606622000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2026896000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2026896000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7369702000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7369702000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9396598000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9396598000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9396598000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9396598000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34439.127143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34439.127143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52333.184750 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52333.184750 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47012.009161 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47012.009161 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47012.009161 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47012.009161 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33355.758154 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33355.758154 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51328.908329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51328.908329 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45984.212896 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45984.212896 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1910430000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1910430000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7083160000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7083160000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8993590000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8993590000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8993590000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8993590000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1905364000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1905364000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7082546000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7082546000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8987910000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8987910000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8987910000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31439.127143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31439.127143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49333.184750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49333.184750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44012.009161 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44012.009161 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44012.009161 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44012.009161 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31355.758154 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31355.758154 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49328.908329 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49328.908329 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43984.212896 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43984.212896 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43984.212896 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43984.212896 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 135625 # number of replacements -system.cpu.l2cache.tagsinuse 29002.571879 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29005.267541 # Cycle average of tags in use system.cpu.l2cache.total_refs 136279 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 166491 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.818537 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25772.303239 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1646.708734 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1583.559905 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.786508 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.050254 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.048326 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.885088 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 25782.627688 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1648.153103 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1574.486750 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.786823 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.050298 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.048050 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.885171 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 68853 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31317 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 100170 # number of ReadReq hits @@ -304,17 +304,17 @@ system.cpu.l2cache.demand_misses::total 168060 # nu system.cpu.l2cache.overall_misses::cpu.inst 7583 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 160477 # number of overall misses system.cpu.l2cache.overall_misses::total 168060 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 394316000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1531348000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1925664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6813456000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6813456000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 394316000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8344804000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8739120000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 394316000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8344804000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8739120000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 394391000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1531428000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1925819000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6813468000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6813468000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 394391000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8344896000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8739287000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 394391000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8344896000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8739287000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) @@ -339,17 +339,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.598547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099207 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.785328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.598547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52009.890545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.716561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52004.185569 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.091583 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.091583 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52009.890545 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.573291 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.993693 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52009.890545 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.573291 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.993693 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,17 +371,17 @@ system.cpu.l2cache.demand_mshr_misses::total 168060 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 160477 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 168060 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1177960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1481280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5241120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5241120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6419080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6722400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6419080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6722400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303395000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1178040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1481435000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5241132000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5241132000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303395000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6419172000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6722567000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303395000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6419172000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6722567000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.484630 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269909 # mshr miss rate for ReadReq accesses @@ -393,17 +393,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.598547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785328 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.598547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.890545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.716561 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40004.185569 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.091583 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.091583 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.890545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.573291 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.993693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.890545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.573291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.993693 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index fdf8f5a60..3a7d388e3 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024261 # Number of seconds simulated -sim_ticks 24260940500 # Number of ticks simulated -final_tick 24260940500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023747 # Number of seconds simulated +sim_ticks 23747395500 # Number of ticks simulated +final_tick 23747395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115016 # Simulator instruction rate (inst/s) -host_op_rate 163211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39343372 # Simulator tick rate (ticks/s) -host_mem_usage 237732 # Number of bytes of host memory used -host_seconds 616.65 # Real time elapsed on the host -sim_insts 70924159 # Number of instructions simulated -sim_ops 100643406 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 327680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory -system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 327680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 327680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417600 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84650 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84650 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13506484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330903577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 344410061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13506484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13506484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 223305440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 223305440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 223305440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13506484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330903577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 567715501 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 107822 # Simulator instruction rate (inst/s) +host_op_rate 153002 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36101670 # Simulator tick rate (ticks/s) +host_mem_usage 242616 # Number of bytes of host memory used +host_seconds 657.79 # Real time elapsed on the host +sim_insts 70924309 # Number of instructions simulated +sim_ops 100643556 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 325888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8028992 # Number of bytes read from this memory +system.physmem.bytes_read::total 8354880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 325888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 325888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417728 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417728 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5092 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125453 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130545 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84652 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84652 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13723105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 338099898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 351823003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13723105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13723105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 228139882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 228139882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 228139882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13723105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 338099898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 579962885 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 48521882 # number of cpu cycles simulated +system.cpu.numCycles 47494792 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16966170 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12979168 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 675165 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11674119 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7996673 # Number of BTB hits +system.cpu.BPredUnit.lookups 16945853 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12976600 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 671047 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11791616 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7980415 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1849293 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114426 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12701255 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 86893403 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16966170 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9845966 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21627617 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2635386 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10974011 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 407 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 11950097 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 196542 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47237958 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.329156 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1850372 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114214 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12555295 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 86800259 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16945853 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9830787 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21603869 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2612787 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10088905 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 11920379 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 192164 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46165707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.632126 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.343505 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25631712 54.26% 54.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2165185 4.58% 58.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2027432 4.29% 63.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2093511 4.43% 67.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1492717 3.16% 70.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1413949 2.99% 73.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 984209 2.08% 75.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1226744 2.60% 78.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10202499 21.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24583523 53.25% 53.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2172032 4.70% 57.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2013449 4.36% 62.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2091121 4.53% 66.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1494392 3.24% 70.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1411801 3.06% 73.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 982905 2.13% 75.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1224192 2.65% 77.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10192292 22.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47237958 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.349660 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.790809 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14870883 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9280138 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19842641 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1415670 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1828626 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3426061 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108157 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118947297 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 370581 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1828626 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16604946 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2957626 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 761420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19440844 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5644496 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116783060 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12596 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4803591 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 254 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117118920 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 537771429 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537766148 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5281 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17959800 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25743 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25726 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13145883 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29944086 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22669898 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3682577 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4376453 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112886356 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41706 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108196580 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 320650 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12119727 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28466628 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4614 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47237958 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.290458 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.991605 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 46165707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.356794 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.827574 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14647959 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8470510 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19858799 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1377235 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1811204 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3409264 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108749 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118806925 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 370081 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1811204 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16375618 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2381141 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 742521 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19461585 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5393638 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116666793 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 61 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9401 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4563999 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 255 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117035573 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 537232740 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537225721 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7019 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159360 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 17876213 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25291 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25289 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12820996 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29922759 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22636012 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3511140 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4209388 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112770529 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41465 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108119060 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 319934 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12017924 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28288746 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4343 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46165707 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.341978 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.993843 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11517306 24.38% 24.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8382479 17.75% 42.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7488515 15.85% 57.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7167095 15.17% 73.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5452995 11.54% 84.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3887775 8.23% 92.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1886175 3.99% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 877063 1.86% 98.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 578555 1.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10763393 23.31% 23.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8065577 17.47% 40.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7395154 16.02% 56.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7189034 15.57% 72.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5495666 11.90% 84.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3896907 8.44% 92.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1882413 4.08% 96.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 886108 1.92% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 591455 1.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47237958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46165707 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 110786 4.40% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1390381 55.25% 59.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1015261 40.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111137 4.37% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1401194 55.04% 59.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1033519 40.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57217754 52.88% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91589 0.08% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 191 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29118364 26.91% 79.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21768675 20.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57171551 52.88% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91476 0.08% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 254 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29115621 26.93% 79.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21740151 20.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108196580 # Type of FU issued -system.cpu.iq.rate 2.229851 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2516428 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023258 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 266467665 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125074926 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106294504 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 531 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 794 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110712739 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 269 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2177452 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108119060 # Type of FU issued +system.cpu.iq.rate 2.276440 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2545850 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023547 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 265268953 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124855497 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106214423 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 658 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1042 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 198 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110664579 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 331 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2183386 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2633672 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7610 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29131 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2110854 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2612315 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8134 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 27815 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2076938 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 45 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1828626 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 932107 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 39617 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112937916 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 341621 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29944086 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22669898 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25185 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2553 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3723 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29131 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 450221 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 202626 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 652847 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107016957 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28768203 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1179623 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1811204 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 969930 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37593 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112821828 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 344750 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29922759 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22636012 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24938 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1077 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4742 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 27815 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 448633 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 200270 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 648903 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106941825 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28766464 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1177235 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9854 # number of nop insts executed -system.cpu.iew.exec_refs 50224831 # number of memory reference insts executed -system.cpu.iew.exec_branches 14719282 # Number of branches executed -system.cpu.iew.exec_stores 21456628 # Number of stores executed -system.cpu.iew.exec_rate 2.205540 # Inst execution rate -system.cpu.iew.wb_sent 106535697 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106294668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53446146 # num instructions producing a value -system.cpu.iew.wb_consumers 103592779 # num instructions consuming a value +system.cpu.iew.exec_nop 9834 # number of nop insts executed +system.cpu.iew.exec_refs 50197967 # number of memory reference insts executed +system.cpu.iew.exec_branches 14707935 # Number of branches executed +system.cpu.iew.exec_stores 21431503 # Number of stores executed +system.cpu.iew.exec_rate 2.251654 # Inst execution rate +system.cpu.iew.wb_sent 106459563 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106214621 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53551409 # num instructions producing a value +system.cpu.iew.wb_consumers 103987749 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.190654 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.515925 # average fanout of values written-back +system.cpu.iew.wb_rate 2.236342 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514978 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12289679 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569161 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45409333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.216482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.738259 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12173182 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37122 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 565028 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44354504 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.269197 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.754788 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15949772 35.12% 35.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11950425 26.32% 61.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3594230 7.92% 69.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2920439 6.43% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880725 4.14% 79.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1913412 4.21% 84.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 683428 1.51% 85.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 576988 1.27% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5939914 13.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15099779 34.04% 34.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11755524 26.50% 60.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3528202 7.95% 68.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2907503 6.56% 75.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1884478 4.25% 79.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1967896 4.44% 83.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685684 1.55% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580329 1.31% 86.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5945109 13.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45409333 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929711 # Number of instructions committed -system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 44354504 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929861 # Number of instructions committed +system.cpu.commit.committedOps 100649108 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869458 # Number of memory references committed -system.cpu.commit.loads 27310414 # Number of loads committed +system.cpu.commit.refs 47869518 # Number of memory references committed +system.cpu.commit.loads 27310444 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13744811 # Number of branches committed +system.cpu.commit.branches 13744841 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486123 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5939914 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5945109 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 152382757 # The number of ROB reads -system.cpu.rob.rob_writes 227716793 # The number of ROB writes -system.cpu.timesIdled 52521 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1283924 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924159 # Number of Instructions Simulated -system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated -system.cpu.cpi 0.684138 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.684138 # CPI: Total CPI of All Threads -system.cpu.ipc 1.461694 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.461694 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 515060291 # number of integer regfile reads -system.cpu.int_regfile_writes 104149739 # number of integer regfile writes -system.cpu.fp_regfile_reads 734 # number of floating regfile reads -system.cpu.fp_regfile_writes 618 # number of floating regfile writes -system.cpu.misc_regfile_reads 145340198 # number of misc regfile reads -system.cpu.misc_regfile_writes 38452 # number of misc regfile writes -system.cpu.icache.replacements 30556 # number of replacements -system.cpu.icache.tagsinuse 1813.467317 # Cycle average of tags in use -system.cpu.icache.total_refs 11916104 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 32594 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 365.591949 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 151206386 # The number of ROB reads +system.cpu.rob.rob_writes 227466743 # The number of ROB writes +system.cpu.timesIdled 61795 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1329085 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924309 # Number of Instructions Simulated +system.cpu.committedOps 100643556 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924309 # Number of Instructions Simulated +system.cpu.cpi 0.669655 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.669655 # CPI: Total CPI of All Threads +system.cpu.ipc 1.493307 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.493307 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 514746035 # number of integer regfile reads +system.cpu.int_regfile_writes 104090442 # number of integer regfile writes +system.cpu.fp_regfile_reads 1004 # number of floating regfile reads +system.cpu.fp_regfile_writes 868 # number of floating regfile writes +system.cpu.misc_regfile_reads 145207051 # number of misc regfile reads +system.cpu.misc_regfile_writes 38512 # number of misc regfile writes +system.cpu.icache.replacements 28686 # number of replacements +system.cpu.icache.tagsinuse 1815.800680 # Cycle average of tags in use +system.cpu.icache.total_refs 11888473 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30726 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 386.918994 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1813.467317 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.885482 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.885482 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11916104 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11916104 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11916104 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11916104 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11916104 # number of overall hits -system.cpu.icache.overall_hits::total 11916104 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33993 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33993 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33993 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33993 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33993 # number of overall misses -system.cpu.icache.overall_misses::total 33993 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 409410000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 409410000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 409410000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 409410000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 409410000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 409410000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11950097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11950097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11950097 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11950097 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11950097 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11950097 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002845 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002845 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002845 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002845 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002845 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002845 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12043.950225 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12043.950225 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12043.950225 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12043.950225 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12043.950225 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12043.950225 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1815.800680 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.886621 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.886621 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11888474 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11888474 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11888474 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11888474 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11888474 # number of overall hits +system.cpu.icache.overall_hits::total 11888474 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31905 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31905 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31905 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31905 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31905 # number of overall misses +system.cpu.icache.overall_misses::total 31905 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 328897000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 328897000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 328897000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 328897000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 328897000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 328897000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11920379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11920379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11920379 # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39490.096662 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39490.096662 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20497 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20497 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19255 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19255 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46196088 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46196088 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46196088 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46196088 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003997 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078836 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078836 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036154 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036154 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036154 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036154 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20342.991178 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20342.991178 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34612.904607 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34612.904607 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8535.714286 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8535.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33713.205595 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33713.205595 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 209500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 197000 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35914.925722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35914.925722 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29702.807604 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29702.807604 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29702.807604 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29702.807604 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 128103 # number of writebacks +system.cpu.dcache.writebacks::total 128103 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49707 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49707 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457877 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107026 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107026 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 30724 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 162583 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 193307 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 30724 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 162583 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 193307 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.166905 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.417625 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.328346 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955983 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955983 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166905 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.772018 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.675842 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166905 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.772018 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.675842 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35347.601404 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36737.910525 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36486.251324 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36285.148805 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36285.148805 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35347.601404 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36368.842468 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36328.757319 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35347.601404 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36368.842468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36328.757319 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,69 +655,69 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 84650 # number of writebacks -system.cpu.l2cache.writebacks::total 84650 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 27 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 88 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5120 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23120 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 28240 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102318 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102318 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5120 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125438 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 130558 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5120 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125438 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 130558 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164141000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 758230000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 922371000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1129000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1129000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3246844000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3246844000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164141000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4005074000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4169215000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164141000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4005074000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 4169215000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415566 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320094 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.692308 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.692308 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771219 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.668712 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771219 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.668712 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32058.789062 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32795.415225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32661.862606 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31361.111111 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31361.111111 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31732.872026 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31732.872026 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32058.789062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31928.713787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31933.814856 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32058.789062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31928.713787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31933.814856 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 84652 # number of writebacks +system.cpu.l2cache.writebacks::total 84652 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 36 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 100 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5092 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23138 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 28230 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102315 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102315 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5092 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130545 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5092 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125453 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130545 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164482000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 778171500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 942653500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 567000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 567000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3395437000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3395437000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164482000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4173608500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4338090500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164482000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4173608500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4338090500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416473 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.327187 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955983 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955983 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771624 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.675325 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165734 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771624 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.675325 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32302.042419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33631.752960 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33391.905774 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33186.111518 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33186.111518 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32302.042419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33268.303668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33230.613965 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32302.042419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33268.303668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33230.613965 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index c163d61b7..88647a82b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133513 # Number of seconds simulated -sim_ticks 133513136000 # Number of ticks simulated -final_tick 133513136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132746 # Number of seconds simulated +sim_ticks 132746076000 # Number of ticks simulated +final_tick 132746076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 903503 # Simulator instruction rate (inst/s) -host_op_rate 1281191 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1714129830 # Simulator tick rate (ticks/s) -host_mem_usage 235208 # Number of bytes of host memory used -host_seconds 77.89 # Real time elapsed on the host +host_inst_rate 594787 # Simulator instruction rate (inst/s) +host_op_rate 843423 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1121948184 # Simulator tick rate (ticks/s) +host_mem_usage 240564 # Number of bytes of host memory used +host_seconds 118.32 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 125054 # Nu system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2050195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 59945083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61995278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2050195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2050195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40470864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40470864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40470864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2050195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 59945083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 102466142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2062042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60291470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 62353512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2062042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2062042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40704721 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40704721 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40704721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2062042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60291470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 103058233 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 267026272 # number of cpu cycles simulated +system.cpu.numCycles 265492152 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 47862847 # nu system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267026272 # Number of busy cycles +system.cpu.num_busy_cycles 265492152 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1735.470121 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1736.430287 # Cycle average of tags in use system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1735.470121 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847398 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847398 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1736.430287 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847866 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847866 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 445311000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 445311000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 445311000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 445311000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 445311000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 445311000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 425522000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 425522000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 425522000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 425522000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 425522000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 425522000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23551.459700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23551.459700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23551.459700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23551.459700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23551.459700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23551.459700 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22504.865665 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22504.865665 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22504.865665 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22504.865665 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 388587000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 388587000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 388587000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 388587000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 388587000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 388587000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387706000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 387706000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387706000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 387706000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387706000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 387706000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20551.459700 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20551.459700 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20551.459700 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20551.459700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20551.459700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20551.459700 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20504.865665 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20504.865665 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.664624 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.962537 # Cycle average of tags in use system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1111220000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.664624 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.962537 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995352 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995352 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1699159000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1699159000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5797120000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5797120000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7496279000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7496279000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7496279000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7496279000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1642566000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1642566000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689754000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689754000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7332320000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7332320000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7332320000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7332320000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32080.183514 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32080.183514 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54162.493460 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54162.493460 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46852.329404 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46852.329404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46852.329404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46852.329404 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31011.705622 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31011.705622 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53159.372898 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53159.372898 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45827.572845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45827.572845 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1540261000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1540261000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5476024000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5476024000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7016285000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7016285000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7016285000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7016285000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536634000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536634000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475690000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475690000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012324000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7012324000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012324000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7012324000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.183514 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29080.183514 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51162.493460 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51162.493460 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43852.329404 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43852.329404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43852.329404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43852.329404 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29011.705622 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29011.705622 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.372898 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.372898 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 96735 # number of replacements -system.cpu.l2cache.tagsinuse 28857.116422 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 28875.776749 # Cycle average of tags in use system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26427.849240 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 949.438432 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1479.828749 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.806514 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.028975 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.045161 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.880649 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 26451.163706 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 950.000997 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1474.612046 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.807225 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.028992 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.045002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.881219 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14631 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 30253 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 44884 # number of ReadReq hits @@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 129331 # nu system.cpu.l2cache.overall_misses::cpu.inst 4277 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125054 # number of overall misses system.cpu.l2cache.overall_misses::total 129331 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222404000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181076000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1403480000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321732000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5321732000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 222404000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6502808000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6725212000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 222404000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6502808000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6725212000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222488000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181138000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1403626000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321748000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5321748000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 222488000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6502886000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6725374000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 222488000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6502886000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6725374000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) @@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.722899 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.226201 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.781597 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.722899 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52019.639935 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.729714 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.409411 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.156340 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.156340 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52019.639935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.623731 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52001.252600 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52019.639935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.623731 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52001.252600 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 129331 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4277 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125054 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 129331 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093640000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093640000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5173240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5173240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171164000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908582000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079746000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093656000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093656000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171164000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002238000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5173402000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171164000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002238000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5173402000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.428822 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.375518 # mshr miss rate for ReadReq accesses @@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.722899 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.722899 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40019.639935 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.729714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.409411 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.156340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.156340 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index fbfcfb090..1d85fdbdf 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.204097 # Number of seconds simulated -sim_ticks 204097178000 # Number of ticks simulated -final_tick 204097178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202343 # Number of seconds simulated +sim_ticks 202342809000 # Number of ticks simulated +final_tick 202342809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1441199 # Simulator instruction rate (inst/s) -host_op_rate 1459859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2188591939 # Simulator tick rate (ticks/s) -host_mem_usage 238748 # Number of bytes of host memory used -host_seconds 93.26 # Real time elapsed on the host +host_inst_rate 1232815 # Simulator instruction rate (inst/s) +host_op_rate 1248778 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1856050290 # Simulator tick rate (ticks/s) +host_mem_usage 230736 # Number of bytes of host memory used +host_seconds 109.02 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 123533 # Nu system.physmem.num_reads::total 133934 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3261505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38736998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41998503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3261505 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3261505 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25974764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25974764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25974764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3261505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38736998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67973267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3289783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39072859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 42362642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3289783 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3289783 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26199972 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26199972 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26199972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3289783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39072859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 68562614 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 408194356 # number of cpu cycles simulated +system.cpu.numCycles 404685618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 408194356 # Number of busy cycles +system.cpu.num_busy_cycles 404685618 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.409949 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2004.814192 # Cycle average of tags in use system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 145330286000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.409949 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978716 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978716 # Average percentage of cache occupancy +system.cpu.icache.warmup_cycle 144074079000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 2004.814192 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.978913 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3060544000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3060544000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3060544000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3060544000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3060544000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3060544000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2868177000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2868177000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2868177000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2868177000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2868177000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2868177000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16364.445205 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16364.445205 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16364.445205 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16364.445205 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16364.445205 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16364.445205 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15335.876679 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15335.876679 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15335.876679 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15335.876679 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2499472000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2499472000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2499472000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2499472000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2499472000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2499472000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2494129000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2494129000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2494129000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2494129000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2494129000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2494129000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13364.445205 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13364.445205 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13364.445205 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13364.445205 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13364.445205 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13364.445205 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.876679 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.876679 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.413116 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.652500 # Cycle average of tags in use system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 812030000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.413116 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997904 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.652500 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997962 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997962 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1571682000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1571682000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5728295000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5728295000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 430000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 430000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7299977000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7299977000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7299977000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7299977000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1523847000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1523847000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5622992000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5622992000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7146839000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7146839000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7146839000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7146839000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34543.220730 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34543.220730 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54470.113347 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54470.113347 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 28666.666667 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 28666.666667 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48452.353929 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48452.353929 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48452.353929 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48452.353929 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33491.878942 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33491.878942 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53468.791602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53468.791602 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47435.926538 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47435.926538 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1435185000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1435185000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412803000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412803000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 385000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 385000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6847988000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6847988000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6847988000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6847988000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1432849000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1432849000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6845513000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6845513000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6845513000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6845513000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31543.220730 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31543.220730 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51470.113347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51470.113347 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25666.666667 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25666.666667 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45452.353929 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45452.353929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45452.353929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45452.353929 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31491.878942 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31491.878942 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 101560 # number of replacements -system.cpu.l2cache.tagsinuse 29278.942435 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29290.996090 # Cycle average of tags in use system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 24760.228137 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3263.271559 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1255.442739 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.755622 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.099587 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.038313 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.893522 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 24775.786415 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3266.546663 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1248.663012 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.756097 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.099687 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.038106 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.893890 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 176623 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 23301 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 199924 # number of ReadReq hits @@ -292,17 +292,17 @@ system.cpu.l2cache.demand_misses::total 133934 # nu system.cpu.l2cache.overall_misses::cpu.inst 10401 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123533 # number of overall misses system.cpu.l2cache.overall_misses::total 133934 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 540852000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1154296000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1695148000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 540875000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1154340000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1695215000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5269420000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5269420000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 540852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6423716000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6964568000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 540852000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6423716000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6964568000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 540875000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6423760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6964635000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 540875000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6423760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6964635000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) @@ -327,17 +327,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.396604 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.055613 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.819848 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.396604 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.211326 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.982161 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.055278 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.500246 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.500246 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,17 +359,17 @@ system.cpu.l2cache.demand_mshr_misses::total 133934 system.cpu.l2cache.overall_mshr_misses::cpu.inst 10401 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123533 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 133934 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 416040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 887920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1303960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 416063000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 887964000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1304027000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4053400000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4053400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 416040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4941320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5357360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 416040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4941320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5357360000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 416063000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4941364000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5357427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 416063000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4941364000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5357427000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.487879 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.140197 # mshr miss rate for ReadReq accesses @@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.396604 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.819848 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.396604 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.211326 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.982161 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.055278 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |