diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/long/se/50.vortex/ref | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/long/se/50.vortex/ref')
3 files changed, 1725 insertions, 1725 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 8052f41c2..2f98c15fc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043266 # Number of seconds simulated -sim_ticks 43266024500 # Number of ticks simulated -final_tick 43266024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042726 # Number of seconds simulated +sim_ticks 42726055500 # Number of ticks simulated +final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92573 # Simulator instruction rate (inst/s) -host_op_rate 92573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45339086 # Simulator tick rate (ticks/s) -host_mem_usage 308556 # Number of bytes of host memory used -host_seconds 954.28 # Real time elapsed on the host +host_inst_rate 156388 # Simulator instruction rate (inst/s) +host_op_rate 156388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75637274 # Simulator tick rate (ticks/s) +host_mem_usage 259292 # Number of bytes of host memory used +host_seconds 564.88 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 454720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory -system.physmem.bytes_read::total 10593088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 454720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 454720 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454848 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7107 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165517 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10509863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 234326313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 244836176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10509863 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10509863 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 168626725 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 168626725 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 168626725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10509863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 234326313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 413462901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165517 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 10645682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 237287713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 247933395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10645682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10645682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 170757818 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 170757818 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 170757818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10645682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 237287713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165519 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279514 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10593088 # Total number of bytes read from memory +system.physmem.cpureqs 279530 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10593216 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10593088 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10222 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10694 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10217 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10334 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10242 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7300 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7039 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7379 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7080 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7193 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10574 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10269 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9936 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10514 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7006 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6934 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43266004500 # Total gap between requests +system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry +system.physmem.totGap 42726035000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165517 # Categorize read packet sizes +system.physmem.readPktSize::6 165519 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 113997 # categorize write packet sizes +system.physmem.writePktSize::6 114011 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 71923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 62480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 76428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see @@ -161,45 +161,45 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9309879146 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11706015146 # Sum of mem lat for all requests -system.physmem.totBusLat 662068000 # Total cycles spent in databus access -system.physmem.totBankLat 1734068000 # Total cycles spent in bank access -system.physmem.avgQLat 56247.27 # Average queueing delay per request -system.physmem.avgBankLat 10476.68 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70723.94 # Average memory access latency -system.physmem.avgRdBW 244.84 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 168.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 244.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 168.63 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.58 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.27 # Average read queue length over time -system.physmem.avgWrQLen 10.35 # Average write queue length over time -system.physmem.readRowHits 151965 # Number of row buffer hits during reads -system.physmem.writeRowHits 41713 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.59 # Row buffer hit rate for writes -system.physmem.avgGap 154790.12 # Average gap between requests -system.cpu.branchPred.lookups 18742312 # Number of BP lookups -system.cpu.branchPred.condPredicted 12317439 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4774431 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15498318 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4661486 # Number of BTB hits +system.physmem.totQLat 7053628221 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9647149471 # Sum of mem lat for all requests +system.physmem.totBusLat 827595000 # Total cycles spent in databus access +system.physmem.totBankLat 1765926250 # Total cycles spent in bank access +system.physmem.avgQLat 42615.22 # Average queueing delay per request +system.physmem.avgBankLat 10669.02 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 58284.24 # Average memory access latency +system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 170.76 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.27 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.23 # Average read queue length over time +system.physmem.avgWrQLen 10.42 # Average write queue length over time +system.physmem.readRowHits 148856 # Number of row buffer hits during reads +system.physmem.writeRowHits 71620 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes +system.physmem.avgGap 152857.21 # Average gap between requests +system.cpu.branchPred.lookups 18742591 # Number of BP lookups +system.cpu.branchPred.condPredicted 12317071 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4774939 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 15471437 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4667620 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.077367 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1660962 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 30.169273 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1660963 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -209,18 +209,18 @@ system.cpu.dtb.read_hits 20277550 # DT system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 20367698 # DTB read accesses -system.cpu.dtb.write_hits 14728696 # DTB write hits +system.cpu.dtb.write_hits 14728779 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14735948 # DTB write accesses -system.cpu.dtb.data_hits 35006246 # DTB hits +system.cpu.dtb.write_accesses 14736031 # DTB write accesses +system.cpu.dtb.data_hits 35006329 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103646 # DTB accesses -system.cpu.itb.fetch_hits 12367278 # ITB hits -system.cpu.itb.fetch_misses 11044 # ITB misses +system.cpu.dtb.data_accesses 35103729 # DTB accesses +system.cpu.itb.fetch_hits 12368275 # ITB hits +system.cpu.itb.fetch_misses 11063 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378322 # ITB accesses +system.cpu.itb.fetch_accesses 12379338 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,34 +234,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 86532050 # number of cpu cycles simulated +system.cpu.numCycles 85452112 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8071751 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10670561 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74169472 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8078019 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10664572 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74169588 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126488722 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 66053 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126488838 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66061 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293683 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14165611 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35060577 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4447125 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 216806 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4663931 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9108659 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.863863 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777842 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293691 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14166165 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060657 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4447555 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216884 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4664439 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9108157 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.867537 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44777871 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77186042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77185122 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 230961 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16958681 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69573369 # Number of cycles cpu stages are processed. -system.cpu.activity 80.401850 # Percentage of cycles cpu is active +system.cpu.timesIdled 229327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed. +system.cpu.activity 81.422683 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -273,194 +273,194 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.979527 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.967302 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.979527 # CPI: Total CPI of All Threads -system.cpu.ipc 1.020901 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.967302 # CPI: Total CPI of All Threads +system.cpu.ipc 1.033803 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.020901 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33881250 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52650800 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.845432 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44079875 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42452175 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 49.059481 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 43502532 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43029518 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.726683 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 64419596 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22112454 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.554062 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40482959 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46049091 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 53.216226 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 84282 # number of replacements -system.cpu.icache.tagsinuse 1908.908494 # Cycle average of tags in use -system.cpu.icache.total_refs 12250113 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 86328 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.901967 # Average number of references to valid blocks. +system.cpu.ipc_total 1.033803 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32797293 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52654819 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.619096 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 42999337 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42452775 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 49.680194 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 42422406 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43029706 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 50.355345 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 63339640 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22112472 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.877034 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 39402909 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 84308 # number of replacements +system.cpu.icache.tagsinuse 1908.296965 # Cycle average of tags in use +system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1908.908494 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.932084 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.932084 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12250113 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250113 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250113 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250113 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250113 # number of overall hits -system.cpu.icache.overall_hits::total 12250113 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117156 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117156 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117156 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117156 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117156 # number of overall misses -system.cpu.icache.overall_misses::total 117156 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1822166500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1822166500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1822166500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1822166500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1822166500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1822166500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367269 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367269 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15553.334870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15553.334870 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15553.334870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15553.334870 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 309 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1908.296965 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12251160 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12251160 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12251160 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12251160 # number of overall hits +system.cpu.icache.overall_hits::total 12251160 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117106 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117106 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117106 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses +system.cpu.icache.overall_misses::total 117106 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1888398500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1888398500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1888398500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1888398500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1888398500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1888398500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12368266 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12368266 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12368266 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12368266 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16125.548648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16125.548648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16125.548648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16125.548648 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.263158 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 6.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.066667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30828 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30828 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30828 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30828 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30828 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86328 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 86328 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 86328 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 86328 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 86328 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 86328 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1279244500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1279244500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1279244500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1279244500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1279244500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1279244500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006980 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14818.419285 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14818.419285 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30752 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30752 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30752 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30752 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30752 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30752 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86354 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 86354 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 86354 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 86354 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 86354 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 86354 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336296000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1336296000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336296000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1336296000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336296000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1336296000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006982 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006982 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006982 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15474.627695 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15474.627695 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 131593 # number of replacements -system.cpu.l2cache.tagsinuse 30981.522130 # Cycle average of tags in use -system.cpu.l2cache.total_refs 151339 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 163652 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.924761 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 131595 # number of replacements +system.cpu.l2cache.tagsinuse 30966.013927 # Cycle average of tags in use +system.cpu.l2cache.total_refs 151363 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.924896 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27280.254395 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2018.521657 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1682.746078 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.832527 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 27281.106507 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2018.513793 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1666.393626 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.832553 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.061600 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051353 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.945481 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 79223 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.945008 # 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number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 397918500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15808490000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16206408500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 397918500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15808490000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16206408500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 86328 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 165519 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 454675000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513576000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1968251000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996247000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11996247000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 454675000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13509823000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13964498000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 454675000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13509823000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13964498000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 146903 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 168350 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 168350 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 86328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 86354 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204345 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290673 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 86328 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290699 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 86354 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204345 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290673 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082302 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 290699 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082301 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454329 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.235707 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235678 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082302 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082301 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.775218 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569427 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082302 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.569383 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082301 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569427 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56005.418719 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55958.486247 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 55968.116444 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109010.218426 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109010.218426 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56005.418719 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99793.513118 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 97913.860812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56005.418719 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99793.513118 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97913.860812 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.569383 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 63975.657802 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54997.129465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 56839.869470 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91650.663529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91650.663529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84367.945674 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84367.945674 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -471,84 +471,84 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks system.cpu.l2cache.writebacks::total 113997 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7105 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7107 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34626 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34628 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7105 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7107 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165517 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7105 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165519 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7107 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165517 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307703601 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1187367459 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1495071060 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12647339647 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12647339647 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307703601 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13834707106 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14142410707 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307703601 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13834707106 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14142410707 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366278633 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1171229430 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537508063 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407065579 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407065579 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366278633 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578295009 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11944573642 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366278633 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578295009 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11944573642 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235707 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569427 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51537.728015 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42557.662512 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44400.718003 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79509.405375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79509.405375 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200249 # number of replacements -system.cpu.dcache.tagsinuse 4078.683111 # Cycle average of tags in use -system.cpu.dcache.total_refs 33755002 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use +system.cpu.dcache.total_refs 33754882 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204345 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.186337 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 248488000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.683111 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995772 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995772 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574731 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574731 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33755002 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33755002 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33755002 # number of overall hits -system.cpu.dcache.overall_hits::total 33755002 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038646 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038646 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135013 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135013 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135013 # number of overall misses -system.cpu.dcache.overall_misses::total 1135013 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3942448000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3942448000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 91414151500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 91414151500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95356599500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95356599500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95356599500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95356599500 # number of overall miss cycles +system.cpu.dcache.avg_refs 165.185750 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 253407000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4078.188712 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995652 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995652 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180269 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180269 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574613 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574613 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754882 # number of overall hits +system.cpu.dcache.overall_hits::total 33754882 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038764 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038764 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135133 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135133 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135133 # number of overall misses +system.cpu.dcache.overall_misses::total 1135133 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3868219500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3868219500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76703201000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76703201000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80571420500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80571420500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80571420500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80571420500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -559,38 +559,38 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032531 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032531 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032531 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032531 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40910.768209 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40910.768209 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88012.808503 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 88012.808503 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84013.662839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84013.662839 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6187652 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 65 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116324 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.666283 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.666283 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73840.834877 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73840.834877 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70979.718236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70979.718236 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5030029 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.193253 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 65 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.221477 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks system.cpu.dcache.writebacks::total 168350 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35602 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35602 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895066 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895066 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35604 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35604 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895184 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895184 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930788 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -599,14 +599,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204345 system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1934793000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1934793000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14541156500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14541156500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16475949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16475949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16475949500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16475949500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268407000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268407000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14177104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14177104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14177104000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14177104000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -615,14 +615,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31840.582572 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31840.582572 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101275.640758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101275.640758 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31411.124825 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31411.124825 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85446.489762 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85446.489762 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index ee0778484..2c49ec916 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024415 # Number of seconds simulated -sim_ticks 24414646000 # Number of ticks simulated -final_tick 24414646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023883 # Number of seconds simulated +sim_ticks 23882696000 # Number of ticks simulated +final_tick 23882696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131517 # Simulator instruction rate (inst/s) -host_op_rate 131517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40342582 # Simulator tick rate (ticks/s) -host_mem_usage 309584 # Number of bytes of host memory used -host_seconds 605.18 # Real time elapsed on the host +host_inst_rate 224964 # Simulator instruction rate (inst/s) +host_op_rate 224964 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67503934 # Simulator tick rate (ticks/s) +host_mem_usage 262380 # Number of bytes of host memory used +host_seconds 353.80 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 490368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153920 # Number of bytes read from this memory -system.physmem.bytes_read::total 10644288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158655 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166317 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20084993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 415894623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 435979616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20084993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20084993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 298876338 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 298876338 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 298876338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20084993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 415894623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 734855955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166317 # Total number of read requests seen -system.physmem.writeReqs 114015 # Total number of write requests seen -system.physmem.cpureqs 280332 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10644288 # Total number of bytes read from memory -system.physmem.bytesWritten 7296960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10644288 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 490816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10154176 # Number of bytes read from this memory +system.physmem.bytes_read::total 10644992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7669 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158659 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166328 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20551114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 425168750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 445719863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20551114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20551114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 305536025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 305536025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 305536025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20551114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 425168750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 751255888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166328 # Total number of read requests seen +system.physmem.writeReqs 114016 # Total number of write requests seen +system.physmem.cpureqs 280344 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10644992 # Total number of bytes read from memory +system.physmem.bytesWritten 7297024 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10644992 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10583 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10017 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10445 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9953 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10252 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6953 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6884 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7381 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6936 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7376 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7191 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10530 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10412 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10395 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10156 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10115 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6836 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7275 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24414612500 # Total gap between requests +system.physmem.totGap 23882663000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166317 # Categorize read packet sizes +system.physmem.readPktSize::6 166328 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 114015 # categorize write packet sizes +system.physmem.writePktSize::6 114016 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 67939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63061 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,14 +138,14 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4949 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see @@ -161,66 +161,66 @@ system.physmem.wrQLenPdf::19 4957 # Wh system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9394568799 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11745778799 # Sum of mem lat for all requests -system.physmem.totBusLat 665260000 # Total cycles spent in databus access -system.physmem.totBankLat 1685950000 # Total cycles spent in bank access -system.physmem.avgQLat 56486.60 # Average queueing delay per request -system.physmem.avgBankLat 10137.09 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70623.69 # Average memory access latency -system.physmem.avgRdBW 435.98 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 298.88 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 435.98 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 298.88 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 4.59 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.48 # Average read queue length over time -system.physmem.avgWrQLen 10.01 # Average write queue length over time -system.physmem.readRowHits 152275 # Number of row buffer hits during reads -system.physmem.writeRowHits 40821 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.80 # Row buffer hit rate for writes -system.physmem.avgGap 87091.78 # Average gap between requests -system.cpu.branchPred.lookups 16536427 # Number of BP lookups -system.cpu.branchPred.condPredicted 10675204 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 418905 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11705282 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7341882 # Number of BTB hits +system.physmem.totQLat 7244561154 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9788827404 # Sum of mem lat for all requests +system.physmem.totBusLat 831635000 # Total cycles spent in databus access +system.physmem.totBankLat 1712631250 # Total cycles spent in bank access +system.physmem.avgQLat 43556.13 # Average queueing delay per request +system.physmem.avgBankLat 10296.77 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 58852.91 # Average memory access latency +system.physmem.avgRdBW 445.72 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 305.54 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 445.72 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 305.54 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 5.87 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.41 # Average read queue length over time +system.physmem.avgWrQLen 10.04 # Average write queue length over time +system.physmem.readRowHits 149202 # Number of row buffer hits during reads +system.physmem.writeRowHits 70865 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.15 # Row buffer hit rate for writes +system.physmem.avgGap 85190.56 # Average gap between requests +system.cpu.branchPred.lookups 16542352 # Number of BP lookups +system.cpu.branchPred.condPredicted 10681130 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 417709 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11519084 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7344749 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.722812 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1987114 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42052 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.761572 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1990053 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 40943 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22403664 # DTB read hits -system.cpu.dtb.read_misses 220373 # DTB read misses -system.cpu.dtb.read_acv 50 # DTB read access violations -system.cpu.dtb.read_accesses 22624037 # DTB read accesses -system.cpu.dtb.write_hits 15711393 # DTB write hits -system.cpu.dtb.write_misses 41143 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15752536 # DTB write accesses -system.cpu.dtb.data_hits 38115057 # DTB hits -system.cpu.dtb.data_misses 261516 # DTB misses -system.cpu.dtb.data_acv 54 # DTB access violations -system.cpu.dtb.data_accesses 38376573 # DTB accesses -system.cpu.itb.fetch_hits 13911095 # ITB hits -system.cpu.itb.fetch_misses 34570 # ITB misses +system.cpu.dtb.read_hits 22396635 # DTB read hits +system.cpu.dtb.read_misses 219070 # DTB read misses +system.cpu.dtb.read_acv 53 # DTB read access violations +system.cpu.dtb.read_accesses 22615705 # DTB read accesses +system.cpu.dtb.write_hits 15704107 # DTB write hits +system.cpu.dtb.write_misses 40999 # DTB write misses +system.cpu.dtb.write_acv 6 # DTB write access violations +system.cpu.dtb.write_accesses 15745106 # DTB write accesses +system.cpu.dtb.data_hits 38100742 # DTB hits +system.cpu.dtb.data_misses 260069 # DTB misses +system.cpu.dtb.data_acv 59 # DTB access violations +system.cpu.dtb.data_accesses 38360811 # DTB accesses +system.cpu.itb.fetch_hits 13916224 # ITB hits +system.cpu.itb.fetch_misses 34938 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13945665 # ITB accesses +system.cpu.itb.fetch_accesses 13951162 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,238 +234,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 48829295 # number of cpu cycles simulated +system.cpu.numCycles 47765395 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15791672 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105370615 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16536427 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9328996 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19544366 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2001802 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6569447 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 313140 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13911095 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206120 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43680847 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.412284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.135635 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15792461 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105331722 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16542352 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9334802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19546012 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2000871 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6407929 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 309888 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13916224 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 206477 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43516697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.420490 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.137268 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24136481 55.26% 55.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1528556 3.50% 58.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1370450 3.14% 61.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1506920 3.45% 65.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4142263 9.48% 74.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1846581 4.23% 79.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 675220 1.55% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1067886 2.44% 83.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7406490 16.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23970685 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1532413 3.52% 58.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1373284 3.16% 61.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510754 3.47% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4137026 9.51% 74.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1849440 4.25% 78.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 675147 1.55% 80.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069291 2.46% 83.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7398657 17.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43680847 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.338658 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.157938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16869436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6110909 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18556945 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 793975 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1349582 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3748874 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107098 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103640564 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 305578 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1349582 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17328003 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3849727 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84405 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18840913 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2228217 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102377631 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2729 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2099672 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61646345 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123373260 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122920505 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 452755 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43516697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346325 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.205189 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16865376 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5950414 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18541793 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 811002 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1348112 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3746218 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106835 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103623462 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 302130 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1348112 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17322335 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3664232 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84922 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18847631 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2249465 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102361026 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 441 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2593 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2123305 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61634933 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123335826 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122884489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 451337 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9099464 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5534 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4609870 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23237420 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16278692 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1191956 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 452268 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90762555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5288 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88451556 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 99102 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10723978 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4670719 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 705 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43680847 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.024951 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.111086 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9088052 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5535 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4634659 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23233430 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16268738 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1206800 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 454955 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90740192 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5270 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88424187 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 96369 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10688335 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4670210 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43516697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.031960 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.108941 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15440168 35.35% 35.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6886071 15.76% 51.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5612203 12.85% 63.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4740584 10.85% 74.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4695591 10.75% 85.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649897 6.07% 91.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1923598 4.40% 96.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1315990 3.01% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 416745 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15243033 35.03% 35.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6914940 15.89% 50.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5620995 12.92% 63.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4761900 10.94% 74.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4675938 10.75% 85.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2651856 6.09% 91.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1932644 4.44% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1300467 2.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 414924 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43680847 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43516697 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126167 6.80% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 781555 42.12% 48.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 947649 51.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 125783 6.76% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 785729 42.22% 48.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 949726 51.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49366923 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43857 0.05% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121501 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49355625 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43814 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121422 0.14% 56.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121281 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 51 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22854121 25.84% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15904789 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121345 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38953 0.04% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22849621 25.84% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15893267 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88451556 # Type of FU issued -system.cpu.iq.rate 1.811444 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1855371 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020976 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 221933846 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101092156 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86564383 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 604586 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 417604 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294342 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90004545 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 302382 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1470214 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88424187 # Type of FU issued +system.cpu.iq.rate 1.851219 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1861238 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021049 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221719097 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101035757 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86539045 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603581 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 415879 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294278 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89983556 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301869 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1467344 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2960782 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4826 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1665315 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2956792 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4757 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1655361 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2876 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 81924 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2846 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 90923 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1349582 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2855245 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 77128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100251958 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 208716 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23237420 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16278692 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5288 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60129 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 488 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 198098 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161281 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 359379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87608240 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22627118 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 843316 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1348112 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2689881 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74163 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100228982 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217751 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23233430 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16268738 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5270 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60091 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 514 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 196583 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160586 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 357169 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87578672 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22618883 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 845515 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9484115 # number of nop insts executed -system.cpu.iew.exec_refs 38379967 # number of memory reference insts executed -system.cpu.iew.exec_branches 15086881 # Number of branches executed -system.cpu.iew.exec_stores 15752849 # Number of stores executed -system.cpu.iew.exec_rate 1.794174 # Inst execution rate -system.cpu.iew.wb_sent 87251382 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86858725 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33364118 # num instructions producing a value -system.cpu.iew.wb_consumers 43780682 # num instructions consuming a value +system.cpu.iew.exec_nop 9483520 # number of nop insts executed +system.cpu.iew.exec_refs 38364354 # number of memory reference insts executed +system.cpu.iew.exec_branches 15084185 # Number of branches executed +system.cpu.iew.exec_stores 15745471 # Number of stores executed +system.cpu.iew.exec_rate 1.833517 # Inst execution rate +system.cpu.iew.wb_sent 87223381 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86833323 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33358386 # num instructions producing a value +system.cpu.iew.wb_consumers 43765374 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.778824 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762074 # average fanout of values written-back +system.cpu.iew.wb_rate 1.817913 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762210 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8914358 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8889050 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 313984 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42331265 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.086889 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.804714 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 313123 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42168585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.094940 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.806680 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19478152 46.01% 46.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7019307 16.58% 62.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3402930 8.04% 70.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2062880 4.87% 75.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2059752 4.87% 80.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1161194 2.74% 83.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1088223 2.57% 85.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718067 1.70% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5340760 12.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19301880 45.77% 45.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7026183 16.66% 62.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3423669 8.12% 70.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2056444 4.88% 75.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2047690 4.86% 80.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1162920 2.76% 83.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1093248 2.59% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 719437 1.71% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5337114 12.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42331265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42168585 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +476,192 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5340760 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5337114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132928193 # The number of ROB reads -system.cpu.rob.rob_writes 195862433 # The number of ROB writes -system.cpu.timesIdled 69428 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5148448 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132743851 # The number of ROB reads +system.cpu.rob.rob_writes 195810249 # The number of ROB writes +system.cpu.timesIdled 70469 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4248698 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.613497 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.613497 # CPI: Total CPI of All Threads -system.cpu.ipc 1.630000 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.630000 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115949669 # number of integer regfile reads -system.cpu.int_regfile_writes 57525330 # number of integer regfile writes -system.cpu.fp_regfile_reads 249508 # number of floating regfile reads -system.cpu.fp_regfile_writes 240213 # number of floating regfile writes -system.cpu.misc_regfile_reads 38023 # number of misc regfile reads +system.cpu.cpi 0.600130 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600130 # CPI: Total CPI of All Threads +system.cpu.ipc 1.666306 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.666306 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115907691 # number of integer regfile reads +system.cpu.int_regfile_writes 57507162 # number of integer regfile writes +system.cpu.fp_regfile_reads 249392 # number of floating regfile reads +system.cpu.fp_regfile_writes 240337 # number of floating regfile writes +system.cpu.misc_regfile_reads 38035 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 91621 # number of replacements -system.cpu.icache.tagsinuse 1930.572235 # Cycle average of tags in use -system.cpu.icache.total_refs 13805106 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93669 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.381802 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19945764000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1930.572235 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942662 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942662 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13805106 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13805106 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13805106 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13805106 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13805106 # number of overall hits -system.cpu.icache.overall_hits::total 13805106 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105989 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105989 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105989 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105989 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105989 # number of overall misses -system.cpu.icache.overall_misses::total 105989 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1780097998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1780097998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1780097998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1780097998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1780097998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1780097998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13911095 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13911095 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13911095 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13911095 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13911095 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13911095 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007619 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007619 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007619 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007619 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007619 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007619 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16795.120229 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16795.120229 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16795.120229 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16795.120229 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16795.120229 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16795.120229 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 364 # number of cycles access was blocked +system.cpu.icache.replacements 91216 # number of replacements +system.cpu.icache.tagsinuse 1928.922459 # Cycle average of tags in use +system.cpu.icache.total_refs 13810559 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93264 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 148.080277 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19641578000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1928.922459 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.941857 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.941857 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13810559 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13810559 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13810559 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13810559 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13810559 # number of overall hits +system.cpu.icache.overall_hits::total 13810559 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105664 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105664 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105664 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105664 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105664 # number of overall misses +system.cpu.icache.overall_misses::total 105664 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1863781999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1863781999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1863781999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1863781999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1863781999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1863781999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13916223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13916223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13916223 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13916223 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13916223 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13916223 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007593 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007593 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007593 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007593 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007593 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007593 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17638.760590 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17638.760590 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17638.760590 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17638.760590 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17638.760590 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17638.760590 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.071429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12319 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12319 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12319 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12319 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12319 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12319 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93670 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93670 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93670 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93670 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93670 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93670 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1391219000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1391219000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1391219000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1391219000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1391219000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1391219000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006733 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006733 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006733 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14852.343333 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14852.343333 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14852.343333 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14852.343333 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14852.343333 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14852.343333 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12399 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12399 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12399 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12399 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12399 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12399 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93265 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12254323403 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 404789823 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11849533580 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12254323403 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082239 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448548 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228664 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082239 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771962 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.556672 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082239 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771962 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.556672 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52775.726597 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45481.784730 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47056.445114 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80905.360211 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80905.360211 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52775.726597 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74685.543083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73675.206386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52775.726597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74685.543083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73675.206386 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201507 # number of replacements -system.cpu.dcache.tagsinuse 4077.368240 # Cycle average of tags in use -system.cpu.dcache.total_refs 34205521 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205603 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.366838 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 173993000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4077.368240 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995451 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995451 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20631452 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20631452 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574012 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34205464 # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 93436551833 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 93436551833 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105887185833 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105887185833 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105887185833 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105887185833 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20898497 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20898497 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201431 # number of replacements +system.cpu.dcache.tagsinuse 4076.502318 # Cycle average of tags in use +system.cpu.dcache.total_refs 34195386 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205527 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.379045 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 178801000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.502318 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995240 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995240 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20621336 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20621336 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13573997 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13573997 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34195333 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 79088080451 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 79088080451 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91095684951 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91095684951 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91095684951 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91095684951 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20888243 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20888243 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35511874 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35511874 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35511874 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35511874 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35501620 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35501620 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35501620 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35501620 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012778 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012778 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071124 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071124 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036788 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036788 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036788 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036788 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46623.730083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46623.730083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89897.727779 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89897.727779 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81052.032542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81052.032542 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5486905 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071125 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071125 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036795 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036795 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036795 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036795 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44987.971466 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44987.971466 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76091.593499 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76091.593499 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69736.348100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69736.348100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69736.348100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69736.348100 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4377310 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112436 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112282 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.800251 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.984966 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168957 # number of writebacks -system.cpu.dcache.writebacks::total 168957 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204872 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 204872 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895935 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895935 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100807 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100807 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100807 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100807 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62173 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62173 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143430 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143430 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205603 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205603 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205603 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205603 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2029919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2029919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14640535990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14640535990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16670455490 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16670455490 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16670455490 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16670455490 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005790 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005790 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32649.534364 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32649.534364 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102074.433452 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102074.433452 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168913 # number of writebacks +system.cpu.dcache.writebacks::total 168913 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204795 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204795 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895965 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895965 # 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number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2016329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2016329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12443477492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12443477492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14459806992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14459806992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14459806992 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14459806992 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002974 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002974 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32462.801069 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32462.801069 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86765.523076 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86765.523076 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 57be29288..bdf692e24 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026275 # Number of seconds simulated -sim_ticks 26275145500 # Number of ticks simulated -final_tick 26275145500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025578 # Number of seconds simulated +sim_ticks 25577832000 # Number of ticks simulated +final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87619 # Simulator instruction rate (inst/s) -host_op_rate 124343 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32467681 # Simulator tick rate (ticks/s) -host_mem_usage 316828 # Number of bytes of host memory used -host_seconds 809.27 # Real time elapsed on the host +host_inst_rate 153227 # Simulator instruction rate (inst/s) +host_op_rate 217448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55271946 # Simulator tick rate (ticks/s) +host_mem_usage 270340 # Number of bytes of host memory used +host_seconds 462.76 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory -system.physmem.bytes_read::total 8240576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128759 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11345779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302280495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 313626275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11345779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11345779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 204474910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 204474910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 204474910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11345779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302280495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 518101184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128759 # Total number of read requests seen -system.physmem.writeReqs 83947 # Total number of write requests seen -system.physmem.cpureqs 213029 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8240576 # Total number of bytes read from memory -system.physmem.bytesWritten 5372608 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8240576 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372608 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372416 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128779 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83944 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83944 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11662599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 310563929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 322226528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11662599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11662599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 210041883 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 210041883 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 210041883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11662599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 310563929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 532268411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128779 # Total number of read requests seen +system.physmem.writeReqs 83944 # Total number of write requests seen +system.physmem.cpureqs 213035 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8241856 # Total number of bytes read from memory +system.physmem.bytesWritten 5372416 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8241856 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372416 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 323 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8094 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7925 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 7976 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8062 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8171 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7989 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8189 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8178 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8151 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8058 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7986 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7982 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5173 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5371 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5150 # Track writes on a per bank basis +system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7993 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8127 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8038 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5371 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5133 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26275013500 # Total gap between requests +system.physmem.totGap 25577735000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128759 # Categorize read packet sizes +system.physmem.readPktSize::6 128779 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 83947 # categorize write packet sizes +system.physmem.writePktSize::6 83944 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,14 +102,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 323 # categorize neither packet sizes +system.physmem.neitherpktsize::6 312 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2062 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,11 +138,11 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -155,52 +155,52 @@ system.physmem.wrQLenPdf::13 3650 # Wh system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4891352059 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6777204059 # Sum of mem lat for all requests -system.physmem.totBusLat 515028000 # Total cycles spent in databus access -system.physmem.totBankLat 1370824000 # Total cycles spent in bank access -system.physmem.avgQLat 37989.02 # Average queueing delay per request -system.physmem.avgBankLat 10646.60 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52635.62 # Average memory access latency -system.physmem.avgRdBW 313.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 204.47 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 313.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 204.47 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.24 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.26 # Average read queue length over time -system.physmem.avgWrQLen 9.34 # Average write queue length over time -system.physmem.readRowHits 118922 # Number of row buffer hits during reads -system.physmem.writeRowHits 27176 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.37 # Row buffer hit rate for writes -system.physmem.avgGap 123527.37 # Average gap between requests -system.cpu.branchPred.lookups 16626972 # Number of BP lookups -system.cpu.branchPred.condPredicted 12763144 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 604576 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10780847 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7773827 # Number of BTB hits +system.physmem.totQLat 3204614448 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5248634448 # Sum of mem lat for all requests +system.physmem.totBusLat 643885000 # Total cycles spent in databus access +system.physmem.totBankLat 1400135000 # Total cycles spent in bank access +system.physmem.avgQLat 24884.99 # Average queueing delay per request +system.physmem.avgBankLat 10872.55 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 40757.55 # Average memory access latency +system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 210.04 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 4.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.21 # Average read queue length over time +system.physmem.avgWrQLen 9.73 # Average write queue length over time +system.physmem.readRowHits 116758 # Number of row buffer hits during reads +system.physmem.writeRowHits 52879 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes +system.physmem.avgGap 120239.63 # Average gap between requests +system.cpu.branchPred.lookups 16629564 # Number of BP lookups +system.cpu.branchPred.condPredicted 12762911 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 603280 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10503277 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7769578 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.107757 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825491 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113784 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.972894 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1825196 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113459 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,136 +244,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 52550292 # number of cpu cycles simulated +system.cpu.numCycles 51155665 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12554350 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85230964 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16626972 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9599318 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21200413 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2370934 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10497631 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 506 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11689041 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 183016 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 45992800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.594519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335814 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12532709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10561174 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179650 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46029302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335381 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24812491 53.95% 53.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2139973 4.65% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1966955 4.28% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042614 4.44% 67.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1467231 3.19% 70.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1381601 3.00% 73.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958651 2.08% 75.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1187660 2.58% 78.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10035624 21.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24855702 54.00% 54.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466538 3.19% 70.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1380808 3.00% 73.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 959441 2.08% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1192836 2.59% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 45992800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316401 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.621893 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14631573 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8854890 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19476912 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1392472 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1636953 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3331046 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104815 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116877182 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363170 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1636953 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16335988 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2535467 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 864548 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19115469 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5504375 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114992065 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17001 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4650627 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 317 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115303250 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529787373 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529782097 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5276 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46029302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14615111 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8910636 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19475070 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1390460 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116875392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16327930 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2553995 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 876400 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19102314 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5530638 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115006216 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4672566 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115315088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529845526 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529838425 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16170578 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20502 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20496 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13002691 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29626313 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22450124 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3876856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4338192 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111565223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36031 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107269202 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 275818 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10829565 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25919062 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2245 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 45992800 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.332304 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.990217 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16182416 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13070329 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4365711 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 274406 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46029302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.330365 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.988633 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10779099 23.44% 23.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8049451 17.50% 40.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7422892 16.14% 57.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7126081 15.49% 72.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5395767 11.73% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3928809 8.54% 92.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1841047 4.00% 96.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 874903 1.90% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 574751 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10776543 23.41% 23.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8085599 17.57% 40.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7427656 16.14% 57.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7135117 15.50% 72.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5408591 11.75% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3911102 8.50% 92.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1839411 4.00% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 45992800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46029302 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 114108 4.61% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1356583 54.78% 59.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1005840 40.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1003479 40.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56641700 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91676 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56638968 52.80% 52.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91700 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 165 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 212 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued @@ -399,84 +399,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28901726 26.94% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21633928 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28903478 26.95% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21630689 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107269202 # Type of FU issued -system.cpu.iq.rate 2.041267 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2476532 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023087 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263283068 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122458972 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105581252 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 486 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 768 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109745491 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 243 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2188417 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued +system.cpu.iq.rate 2.096836 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2464043 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022972 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263297262 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105577839 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109728805 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2319205 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6776 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29966 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1894386 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2321749 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6850 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30026 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1892744 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 503 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1636953 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1044060 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45930 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111611011 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 291580 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29626313 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22450124 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20111 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6644 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5462 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29966 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393316 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181236 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 574552 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106238160 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28602099 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1031042 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1048423 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45681 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106234972 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030082 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9757 # number of nop insts executed -system.cpu.iew.exec_refs 49948126 # number of memory reference insts executed -system.cpu.iew.exec_branches 14604066 # Number of branches executed -system.cpu.iew.exec_stores 21346027 # Number of stores executed -system.cpu.iew.exec_rate 2.021647 # Inst execution rate -system.cpu.iew.wb_sent 105801461 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105581404 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53258894 # num instructions producing a value -system.cpu.iew.wb_consumers 103486689 # num instructions consuming a value +system.cpu.iew.exec_nop 9761 # number of nop insts executed +system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed +system.cpu.iew.exec_branches 14602542 # Number of branches executed +system.cpu.iew.exec_stores 21344564 # Number of stores executed +system.cpu.iew.exec_rate 2.076700 # Inst execution rate +system.cpu.iew.wb_sent 105797759 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105578008 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53282087 # num instructions producing a value +system.cpu.iew.wb_consumers 103565148 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.009150 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514645 # average fanout of values written-back +system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10979497 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 501718 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44355847 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.268752 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.766108 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44391277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.266941 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764740 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15312059 34.52% 34.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11621987 26.20% 60.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3450685 7.78% 68.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2867250 6.46% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1878784 4.24% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1958737 4.42% 83.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685559 1.55% 85.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 561142 1.27% 86.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6019644 13.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15317735 34.51% 34.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11646185 26.24% 60.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462928 7.80% 68.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1875712 4.23% 79.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1949355 4.39% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685853 1.55% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 564106 1.27% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6015739 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44355847 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44391277 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,204 +487,204 @@ system.cpu.commit.branches 13741505 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6019644 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6015739 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149922829 # The number of ROB reads -system.cpu.rob.rob_writes 224870236 # The number of ROB writes -system.cpu.timesIdled 74082 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6557492 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 149959303 # The number of ROB reads +system.cpu.rob.rob_writes 224865260 # The number of ROB writes +system.cpu.timesIdled 74068 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5126363 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.741109 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.741109 # CPI: Total CPI of All Threads -system.cpu.ipc 1.349329 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.349329 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511669135 # number of integer regfile reads -system.cpu.int_regfile_writes 103349973 # number of integer regfile writes -system.cpu.fp_regfile_reads 690 # number of floating regfile reads -system.cpu.fp_regfile_writes 602 # number of floating regfile writes -system.cpu.misc_regfile_reads 49186281 # number of misc regfile reads +system.cpu.cpi 0.721441 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads +system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511661177 # number of integer regfile reads +system.cpu.int_regfile_writes 103341315 # number of integer regfile writes +system.cpu.fp_regfile_reads 804 # number of floating regfile reads +system.cpu.fp_regfile_writes 688 # number of floating regfile writes +system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.icache.replacements 29504 # number of replacements -system.cpu.icache.tagsinuse 1815.541660 # Cycle average of tags in use -system.cpu.icache.total_refs 11653533 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31535 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 369.542825 # Average number of references to valid blocks. +system.cpu.icache.replacements 28586 # number of replacements +system.cpu.icache.tagsinuse 1814.278230 # Cycle average of tags in use +system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1815.541660 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.886495 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.886495 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11653539 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11653539 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11653539 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11653539 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11653539 # number of overall hits -system.cpu.icache.overall_hits::total 11653539 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35502 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35502 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35502 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35502 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35502 # number of overall misses -system.cpu.icache.overall_misses::total 35502 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 704211999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 704211999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 704211999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 704211999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 704211999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 704211999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11689041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11689041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11689041 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11689041 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11689041 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11689041 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003037 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003037 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003037 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003037 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003037 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003037 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19835.840206 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19835.840206 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19835.840206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19835.840206 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1814.278230 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11645446 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11645446 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11645446 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11645446 # number of overall hits +system.cpu.icache.overall_hits::total 11645446 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34686 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34686 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34686 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses +system.cpu.icache.overall_misses::total 34686 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 739119000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 739119000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 739119000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 739119000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 739119000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 739119000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11680132 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11680132 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11680132 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002970 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002970 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21308.856599 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21308.856599 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21308.856599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21308.856599 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 96.590909 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.440000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3638 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3638 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3638 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3638 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3638 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3638 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31864 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31864 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31864 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31864 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31864 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31864 # 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number of cycles access was blocked @@ -693,195 +693,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83947 # number of writebacks -system.cpu.l2cache.writebacks::total 83947 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8227454893 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8443777804 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216322911 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8227454893 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8443777804 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394097 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305382 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.949853 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.949853 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955504 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955504 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763949 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.664386 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763949 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.664386 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46441.157364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63081.982283 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60157.185571 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10046.024845 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10046.024845 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66982.456844 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66982.456844 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 83944 # number of writebacks +system.cpu.l2cache.writebacks::total 83944 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 76 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594827676 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6846161374 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251333698 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594827676 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6846161374 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.939759 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.939759 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158352 # number of replacements -system.cpu.dcache.tagsinuse 4073.285602 # Cycle average of tags in use -system.cpu.dcache.total_refs 44355767 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.045941 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 278219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.285602 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994454 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994454 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26058145 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26070698 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26070698 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44323215 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44323215 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44323215 # number of overall hits -system.cpu.dcache.overall_hits::total 44323215 # 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number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44337922 # number of overall hits +system.cpu.dcache.overall_hits::total 44337922 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124470 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124470 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1707147 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707147 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707147 # number of overall misses +system.cpu.dcache.overall_misses::total 1707147 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247957000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4247957000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98254010480 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98254010480 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102501967480 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102501967480 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102501967480 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102501967480 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16039 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16039 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16026 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16026 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46033030 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46033030 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46033030 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46033030 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004773 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004773 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002556 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002556 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037143 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037143 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037143 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037143 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37079.782212 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37079.782212 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76051.505163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76051.505163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20682.926829 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20682.926829 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73202.751455 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73202.751455 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3167 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 649 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46045069 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46045069 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46045069 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46045069 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079732 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079732 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002808 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002808 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34128.360247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34128.360247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62080.898680 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62080.898680 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60042.847792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60042.847792 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.784173 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 43.266667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.352459 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129085 # number of writebacks -system.cpu.dcache.writebacks::total 129085 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69523 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69523 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1477505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1547028 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1547028 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1547028 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1547028 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55461 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55461 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107326 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107326 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162787 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162787 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162787 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162787 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2049044000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2049044000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8282203488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8282203488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10331247488 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10331247488 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10331247488 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10331247488 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36945.673536 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36945.673536 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77168.658927 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77168.658927 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks +system.cpu.dcache.writebacks::total 129109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69057 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69057 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544391 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544391 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544391 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544391 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107343 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162756 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878248000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878248000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6802862990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6802862990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681110990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8681110990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681110990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8681110990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33895.439698 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33895.439698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63375.003400 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63375.003400 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |