diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/se/50.vortex/ref | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/se/50.vortex/ref')
18 files changed, 1787 insertions, 1787 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index ef879d8e7..fc9577d62 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 23e06e448..e501186a7 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:15:35 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:54:39 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 47017029500 because target called exit() +Exiting @ tick 47910283500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 0041bdcc8..52b1e9eb7 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.047017 # Number of seconds simulated -sim_ticks 47017029500 # Number of ticks simulated -final_tick 47017029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.047910 # Number of seconds simulated +sim_ticks 47910283500 # Number of ticks simulated +final_tick 47910283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156470 # Simulator instruction rate (inst/s) -host_op_rate 156470 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83276889 # Simulator tick rate (ticks/s) -host_mem_usage 227180 # Number of bytes of host memory used -host_seconds 564.59 # Real time elapsed on the host +host_inst_rate 137428 # Simulator instruction rate (inst/s) +host_op_rate 137428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74532010 # Simulator tick rate (ticks/s) +host_mem_usage 227148 # Number of bytes of host memory used +host_seconds 642.82 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 515072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10272768 # Number of bytes read from this memory -system.physmem.bytes_read::total 10787840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 515072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 515072 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 515328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10272960 # Number of bytes read from this memory +system.physmem.bytes_read::total 10788288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 515328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 515328 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160512 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168560 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 8052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160515 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168567 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10955009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 218490366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 229445376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10955009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10955009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 157866205 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 157866205 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 157866205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10955009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 218490366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 387311580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10756104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 214420773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 225176877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10756104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10756104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 154922899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 154922899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 154922899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10756104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 214420773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380099775 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277221 # DTB read hits +system.cpu.dtb.read_hits 20277225 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367369 # DTB read accesses -system.cpu.dtb.write_hits 14736814 # DTB write hits +system.cpu.dtb.read_accesses 20367373 # DTB read accesses +system.cpu.dtb.write_hits 14736863 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14744066 # DTB write accesses -system.cpu.dtb.data_hits 35014035 # DTB hits +system.cpu.dtb.write_accesses 14744115 # DTB write accesses +system.cpu.dtb.data_hits 35014088 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111435 # DTB accesses -system.cpu.itb.fetch_hits 12478267 # ITB hits -system.cpu.itb.fetch_misses 13087 # ITB misses +system.cpu.dtb.data_accesses 35111488 # DTB accesses +system.cpu.itb.fetch_hits 12475946 # ITB hits +system.cpu.itb.fetch_misses 12952 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12491354 # ITB accesses +system.cpu.itb.fetch_accesses 12488898 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 94034060 # number of cpu cycles simulated +system.cpu.numCycles 95820568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18830633 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12442208 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5026177 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16228748 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5052031 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660951 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 18829757 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12442338 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5025331 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16200752 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5042995 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660949 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.130134 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8480322 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10350311 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74324480 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 31.128154 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8471214 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10358543 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74332888 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126643730 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65335 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126652138 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65238 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292965 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14127744 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064158 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4682153 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 233524 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4915677 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8856497 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.692818 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44775466 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292868 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14120784 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064786 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4680831 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 234000 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4914831 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8857404 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.686517 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44775821 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78068863 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78582823 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 305152 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23747130 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70286930 # Number of cycles cpu stages are processed. -system.cpu.activity 74.746246 # Percentage of cycles cpu is active +system.cpu.timesIdled 467369 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25529650 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70290918 # Number of cycles cpu stages are processed. +system.cpu.activity 73.356816 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.064448 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.084671 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.064448 # CPI: Total CPI of All Threads -system.cpu.ipc 0.939454 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.084671 # CPI: Total CPI of All Threads +system.cpu.ipc 0.921939 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.939454 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 40602486 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53431574 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 56.821511 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 51377982 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42656078 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.362370 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 50907944 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43126116 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.862229 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 71905105 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22128955 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.532915 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47936936 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46097124 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.021731 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85298 # number of replacements -system.cpu.icache.tagsinuse 1887.307132 # Cycle average of tags in use -system.cpu.icache.total_refs 12360070 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87344 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.510235 # Average number of references to valid blocks. +system.cpu.ipc_total 0.921939 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 42393437 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53427131 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 55.757477 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 53162471 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42658097 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 44.518727 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 52693934 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43126634 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.007700 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 73699390 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22121178 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.086043 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 49718373 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46102195 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 48.113047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85335 # number of replacements +system.cpu.icache.tagsinuse 1885.674809 # Cycle average of tags in use +system.cpu.icache.total_refs 12357256 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87381 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.418111 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1887.307132 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.921537 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.921537 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12360070 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12360070 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12360070 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12360070 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12360070 # number of overall hits -system.cpu.icache.overall_hits::total 12360070 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118149 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118149 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118149 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118149 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118149 # number of overall misses -system.cpu.icache.overall_misses::total 118149 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2012242500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2012242500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2012242500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2012242500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2012242500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2012242500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12478219 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12478219 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12478219 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12478219 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12478219 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12478219 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17031.396796 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17031.396796 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17031.396796 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17031.396796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17031.396796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17031.396796 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1885.674809 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.920740 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.920740 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12357256 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12357256 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12357256 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12357256 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12357256 # number of overall hits +system.cpu.icache.overall_hits::total 12357256 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118639 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118639 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118639 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118639 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118639 # number of overall misses +system.cpu.icache.overall_misses::total 118639 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081821000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2081821000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2081821000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2081821000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2081821000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2081821000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12475895 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12475895 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12475895 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12475895 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12475895 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12475895 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009509 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009509 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009509 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009509 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009509 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009509 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.526530 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17547.526530 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17547.526530 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17547.526530 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1223500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1176500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 109 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 105 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 11224.770642 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 11204.761905 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30805 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30805 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30805 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30805 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30805 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30805 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87344 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87344 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87344 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87344 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87344 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87344 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1308493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1308493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1308493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1308493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1308493500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1308493500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14980.920269 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14980.920269 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14980.920269 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14980.920269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14980.920269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14980.920269 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31258 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 31258 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 31258 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 31258 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 31258 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 31258 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87381 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87381 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87381 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87381 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87381 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87381 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364843500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1364843500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364843500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1364843500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364843500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1364843500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.453886 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.453886 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.021699 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126085 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4073.238674 # Cycle average of tags in use +system.cpu.dcache.total_refs 34125947 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000666 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 487962000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.021699 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994390 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994390 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180546 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180546 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945539 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945539 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34126085 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34126085 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34126085 # number of overall hits -system.cpu.dcache.overall_hits::total 34126085 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96092 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96092 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667838 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667838 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 763930 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 763930 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 763930 # number of overall misses -system.cpu.dcache.overall_misses::total 763930 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3967104000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3967104000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35310638000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35310638000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39277742000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39277742000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39277742000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39277742000 # number of overall miss cycles +system.cpu.dcache.avg_refs 166.999990 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 499859000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4073.238674 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994443 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994443 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180530 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180530 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945417 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945417 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34125947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34125947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34125947 # number of overall hits +system.cpu.dcache.overall_hits::total 34125947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96108 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96108 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667960 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667960 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 764068 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 764068 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 764068 # number of overall misses +system.cpu.dcache.overall_misses::total 764068 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4228645500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 42086848500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 42086848500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46315494000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46315494000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46315494000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46315494000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -260,40 +260,40 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004739 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004739 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021895 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021895 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021895 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021895 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41284.435749 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41284.435749 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52873.059035 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52873.059035 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51415.367900 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51415.367900 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51415.367900 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51415.367900 # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045709 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045709 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021899 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021899 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.891872 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.891872 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63008.037158 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63008.037158 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60616.979117 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60616.979117 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6330819000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6945858000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124116 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124169 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51007.275452 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 55938.744775 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 165812 # number of writebacks -system.cpu.dcache.writebacks::total 165812 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35325 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35325 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524258 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524258 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559583 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559583 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559583 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559583 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 165805 # number of writebacks +system.cpu.dcache.writebacks::total 165805 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35341 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35341 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524380 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524380 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559721 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559721 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559721 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559721 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1914810500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1914810500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7237342000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7237342000 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8052 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160515 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168567 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329154000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1181438500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1510592500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5254733000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5254733000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329154000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6436171500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6765325500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329154000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6436171500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6765325500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486439 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253579 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911511 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911511 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.577872 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.577872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40072.626740 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40008.603720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40022.339518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.807185 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.807185 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40072.626740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40014.484898 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40017.260916 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40072.626740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40014.484898 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40017.260916 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785502 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.577822 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785502 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.577822 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40878.539493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40093.613194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40262.067219 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40097.773335 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40097.773335 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 6543d2325..0698ab8df 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 109541527..3d5324180 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:20:14 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:05:33 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 21029927000 because target called exit() +Exiting @ tick 21619648000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 3719775b2..6999de96c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021030 # Number of seconds simulated -sim_ticks 21029927000 # Number of ticks simulated -final_tick 21029927000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021620 # Number of seconds simulated +sim_ticks 21619648000 # Number of ticks simulated +final_tick 21619648000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 262496 # Simulator instruction rate (inst/s) -host_op_rate 262496 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69357396 # Simulator tick rate (ticks/s) -host_mem_usage 228212 # Number of bytes of host memory used -host_seconds 303.21 # Real time elapsed on the host +host_inst_rate 236725 # Simulator instruction rate (inst/s) +host_op_rate 236725 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64301983 # Simulator tick rate (ticks/s) +host_mem_usage 228176 # Number of bytes of host memory used +host_seconds 336.22 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 558848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10293248 # Number of bytes read from this memory -system.physmem.bytes_read::total 10852096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 558848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 558848 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7426112 # Number of bytes written to this memory -system.physmem.bytes_written::total 7426112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8732 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160832 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169564 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116033 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116033 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 26573939 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 489457144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 516031083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 26573939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 26573939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 353121150 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 353121150 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 353121150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 26573939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 489457144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 869152232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 559360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10295744 # Number of bytes read from this memory +system.physmem.bytes_read::total 10855104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 559360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 559360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7426560 # Number of bytes written to this memory +system.physmem.bytes_written::total 7426560 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160871 # Number of read requests responded to by this memory +system.physmem.num_reads::total 169611 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116040 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116040 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25872762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 476221630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 502094391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25872762 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25872762 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 343509756 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 343509756 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 343509756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25872762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 476221630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845604147 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22489459 # DTB read hits -system.cpu.dtb.read_misses 217588 # DTB read misses -system.cpu.dtb.read_acv 44 # DTB read access violations -system.cpu.dtb.read_accesses 22707047 # DTB read accesses -system.cpu.dtb.write_hits 15786869 # DTB write hits -system.cpu.dtb.write_misses 41269 # DTB write misses +system.cpu.dtb.read_hits 22479620 # DTB read hits +system.cpu.dtb.read_misses 218266 # DTB read misses +system.cpu.dtb.read_acv 51 # DTB read access violations +system.cpu.dtb.read_accesses 22697886 # DTB read accesses +system.cpu.dtb.write_hits 15794697 # DTB write hits +system.cpu.dtb.write_misses 42457 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 15828138 # DTB write accesses -system.cpu.dtb.data_hits 38276328 # DTB hits -system.cpu.dtb.data_misses 258857 # DTB misses -system.cpu.dtb.data_acv 44 # DTB access violations -system.cpu.dtb.data_accesses 38535185 # DTB accesses -system.cpu.itb.fetch_hits 14133999 # ITB hits -system.cpu.itb.fetch_misses 38583 # ITB misses +system.cpu.dtb.write_accesses 15837154 # DTB write accesses +system.cpu.dtb.data_hits 38274317 # DTB hits +system.cpu.dtb.data_misses 260723 # DTB misses +system.cpu.dtb.data_acv 51 # DTB access violations +system.cpu.dtb.data_accesses 38535040 # DTB accesses +system.cpu.itb.fetch_hits 14126097 # ITB hits +system.cpu.itb.fetch_misses 39352 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14172582 # ITB accesses +system.cpu.itb.fetch_accesses 14165449 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,105 +67,105 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 42059856 # number of cpu cycles simulated +system.cpu.numCycles 43239299 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16727417 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10795081 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 475795 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12310974 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7475407 # Number of BTB hits +system.cpu.BPredUnit.lookups 16709943 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10781072 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 476192 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12038225 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7471491 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1997632 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44950 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15195386 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106731428 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16727417 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9473039 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19807941 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2142694 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4831440 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 318425 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14133999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 219929 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 41712717 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.558726 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.170110 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1995310 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44665 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15444845 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106679218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16709943 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9466801 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19799027 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2146422 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5702055 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 320776 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14126097 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 222277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 42829816 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.490770 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.154588 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21904776 52.51% 52.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1546832 3.71% 56.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1409518 3.38% 59.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1517307 3.64% 63.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4200862 10.07% 73.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1863663 4.47% 77.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 687442 1.65% 79.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1091312 2.62% 82.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7491005 17.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23030789 53.77% 53.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1545838 3.61% 57.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1407824 3.29% 60.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1518177 3.54% 64.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4200095 9.81% 74.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1866083 4.36% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 683567 1.60% 79.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1088540 2.54% 82.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7488903 17.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 41712717 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.397705 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.537608 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16282600 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4400388 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18871589 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 713555 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1444585 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3801857 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109351 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104838793 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 305565 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1444585 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16762775 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2290284 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 81927 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19061483 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2071663 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103408033 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 177 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1890 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1956072 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62335498 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124694291 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124234000 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 460291 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 42829816 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.386453 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.467182 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16586159 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5216387 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18831807 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 747368 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1448095 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3802176 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109343 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104798684 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 306113 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1448095 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17060162 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2943499 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 82970 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19071081 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2224009 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103374463 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 294 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 47714 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2072135 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62309566 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124647358 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124190382 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 456976 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9788617 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5545 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5542 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4401091 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23371275 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16383320 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1113297 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 382577 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91444399 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5409 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89052036 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 123621 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11266129 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4895344 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 826 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 41712717 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.134889 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.120974 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9762685 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5585 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5583 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4545963 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23367723 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16390642 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1133008 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 393146 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91432081 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5446 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89033358 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 121532 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11257440 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4905922 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 863 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 42829816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.078770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.113525 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13445094 32.23% 32.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6815105 16.34% 48.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5522712 13.24% 61.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4804260 11.52% 73.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4760133 11.41% 84.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2656664 6.37% 91.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1952953 4.68% 95.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1309211 3.14% 98.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 446585 1.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 14329925 33.46% 33.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7119620 16.62% 50.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5526453 12.90% 62.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4793299 11.19% 74.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4689695 10.95% 85.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2671983 6.24% 91.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1950910 4.56% 95.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1326668 3.10% 99.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 421263 0.98% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 41712717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42829816 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 129648 6.83% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 128939 6.83% 6.83% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available @@ -194,120 +194,120 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 800646 42.16% 48.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 968600 51.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 795203 42.12% 48.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 964007 51.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49748943 55.87% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43836 0.05% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121395 0.14% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 122222 0.14% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38945 0.04% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22978145 25.80% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15998405 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49729867 55.86% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43817 0.05% 55.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121200 0.14% 56.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 122187 0.14% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22972171 25.80% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16005027 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89052036 # Type of FU issued -system.cpu.iq.rate 2.117269 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1898894 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021323 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 221228638 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102311745 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87003241 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 610666 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420329 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 297405 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90645490 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305440 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1454782 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89033358 # Type of FU issued +system.cpu.iq.rate 2.059084 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1888149 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021207 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222297193 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102291434 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86992301 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 609020 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 419648 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 296730 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90616918 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 304589 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1450786 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3094637 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5405 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17198 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1769943 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3091085 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5211 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17173 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1777265 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2465 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2461 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 40 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1444585 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1378750 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 59667 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100988081 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 245674 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23371275 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16383320 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5409 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 41936 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 387 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17198 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 251719 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 174529 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 426248 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88078074 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22710515 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 973962 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1448095 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1762662 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 92194 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100976081 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 242299 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23367723 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16390642 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5446 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 53221 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 430 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17173 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 250537 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 173902 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 424439 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88065648 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22701440 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 967710 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9538273 # number of nop insts executed -system.cpu.iew.exec_refs 38539046 # number of memory reference insts executed -system.cpu.iew.exec_branches 15143390 # Number of branches executed -system.cpu.iew.exec_stores 15828531 # Number of stores executed -system.cpu.iew.exec_rate 2.094113 # Inst execution rate -system.cpu.iew.wb_sent 87713914 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87300646 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33458604 # num instructions producing a value -system.cpu.iew.wb_consumers 43597958 # num instructions consuming a value +system.cpu.iew.exec_nop 9538554 # number of nop insts executed +system.cpu.iew.exec_refs 38538948 # number of memory reference insts executed +system.cpu.iew.exec_branches 15139399 # Number of branches executed +system.cpu.iew.exec_stores 15837508 # Number of stores executed +system.cpu.iew.exec_rate 2.036704 # Inst execution rate +system.cpu.iew.wb_sent 87702246 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87289031 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33442850 # num instructions producing a value +system.cpu.iew.wb_consumers 43872911 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.075629 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767435 # average fanout of values written-back +system.cpu.iew.wb_rate 2.018743 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762266 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitCommittedOps 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9531604 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9533571 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 368829 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 40268132 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.193811 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.828127 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 369490 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 41381721 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.134775 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.804212 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17348502 43.08% 43.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7047839 17.50% 60.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3405424 8.46% 69.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2108778 5.24% 74.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2046687 5.08% 79.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1183274 2.94% 82.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1130602 2.81% 85.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 707287 1.76% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5289739 13.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18296264 44.21% 44.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7146737 17.27% 61.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3523583 8.51% 70.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2099457 5.07% 75.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2039541 4.93% 80.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1177840 2.85% 82.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1135730 2.74% 85.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 713898 1.73% 87.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5248671 12.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 40268132 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 41381721 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5289739 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5248671 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131533327 # The number of ROB reads -system.cpu.rob.rob_writes 197192647 # The number of ROB writes -system.cpu.timesIdled 15699 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 347139 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132689951 # The number of ROB reads +system.cpu.rob.rob_writes 197200056 # The number of ROB writes +system.cpu.timesIdled 24548 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 409483 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.528445 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.528445 # CPI: Total CPI of All Threads -system.cpu.ipc 1.892345 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.892345 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116616744 # number of integer regfile reads -system.cpu.int_regfile_writes 57879304 # number of integer regfile writes -system.cpu.fp_regfile_reads 252339 # number of floating regfile reads -system.cpu.fp_regfile_writes 241658 # number of floating regfile writes -system.cpu.misc_regfile_reads 38301 # number of misc regfile reads +system.cpu.cpi 0.543264 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.543264 # CPI: Total CPI of All Threads +system.cpu.ipc 1.840727 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.840727 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116607964 # number of integer regfile reads +system.cpu.int_regfile_writes 57862089 # number of integer regfile writes +system.cpu.fp_regfile_reads 251339 # number of floating regfile reads +system.cpu.fp_regfile_writes 241385 # number of floating regfile writes +system.cpu.misc_regfile_reads 38087 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 93371 # number of replacements -system.cpu.icache.tagsinuse 1930.973067 # Cycle average of tags in use -system.cpu.icache.total_refs 14034495 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 95419 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.082814 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 17612659000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1930.973067 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942858 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942858 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14034495 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14034495 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14034495 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14034495 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14034495 # number of overall hits -system.cpu.icache.overall_hits::total 14034495 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 99504 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 99504 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 99504 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 99504 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 99504 # number of overall misses -system.cpu.icache.overall_misses::total 99504 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 887461000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 887461000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 887461000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 887461000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 887461000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 887461000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14133999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14133999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14133999 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14133999 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14133999 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14133999 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007040 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007040 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007040 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007040 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007040 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007040 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8918.847484 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8918.847484 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8918.847484 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8918.847484 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8918.847484 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8918.847484 # average overall miss latency +system.cpu.icache.replacements 92930 # number of replacements +system.cpu.icache.tagsinuse 1930.212243 # Cycle average of tags in use +system.cpu.icache.total_refs 14026666 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 94978 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.683316 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18067713000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1930.212243 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942486 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942486 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14026666 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14026666 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14026666 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14026666 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14026666 # number of overall hits +system.cpu.icache.overall_hits::total 14026666 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 99431 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 99431 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 99431 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 99431 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 99431 # number of overall misses +system.cpu.icache.overall_misses::total 99431 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1030437000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1030437000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1030437000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1030437000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1030437000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1030437000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14126097 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14126097 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14126097 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14126097 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14126097 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14126097 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007039 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007039 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007039 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007039 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007039 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007039 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10363.337390 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10363.337390 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10363.337390 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10363.337390 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10363.337390 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10363.337390 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,286 +390,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4084 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4084 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4084 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4084 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4084 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4084 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95420 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 95420 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 95420 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 95420 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 95420 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 95420 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 511334500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 511334500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 511334500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 511334500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 511334500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 511334500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006751 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006751 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006751 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5358.776986 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5358.776986 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5358.776986 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 5358.776986 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5358.776986 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 5358.776986 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4452 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4452 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4452 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4452 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4452 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4452 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94979 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 94979 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 94979 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 94979 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 94979 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 94979 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 637690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 637690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 637690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 637690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 637690000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 637690000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006724 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006724 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006724 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6714.010465 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6714.010465 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6714.010465 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6714.010465 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6714.010465 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6714.010465 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201494 # number of replacements -system.cpu.dcache.tagsinuse 4076.242085 # Cycle average of tags in use -system.cpu.dcache.total_refs 34356241 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205590 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.110467 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 156434000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.242085 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995176 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995176 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20778024 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20778024 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13578147 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13578147 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 70 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34356171 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34356171 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34356171 # number of overall hits -system.cpu.dcache.overall_hits::total 34356171 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 254081 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 254081 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1035230 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1035230 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1289311 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1289311 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1289311 # number of overall misses -system.cpu.dcache.overall_misses::total 1289311 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7948579000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7948579000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 34030906498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 34030906498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41979485498 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41979485498 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41979485498 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41979485498 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21032105 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21032105 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201568 # number of replacements +system.cpu.dcache.tagsinuse 4075.950137 # Cycle average of tags in use +system.cpu.dcache.total_refs 34352337 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205664 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.031357 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 168155000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4075.950137 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995105 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995105 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20774825 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20774825 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13577434 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13577434 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 78 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 78 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34352259 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34352259 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34352259 # number of overall hits +system.cpu.dcache.overall_hits::total 34352259 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 251443 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 251443 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1035943 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1035943 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1287386 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1287386 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1287386 # number of overall misses +system.cpu.dcache.overall_misses::total 1287386 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8531732000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8531732000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 45960422000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45960422000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54492154000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54492154000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54492154000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54492154000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21026268 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21026268 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 70 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 70 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35645482 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35645482 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35645482 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35645482 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012081 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012081 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070841 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.070841 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036170 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036170 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036170 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036170 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31283.641831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31283.641831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32872.797830 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32872.797830 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32559.627195 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32559.627195 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32559.627195 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32559.627195 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 100500 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 78 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 78 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35639645 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35639645 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35639645 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35639645 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011959 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011959 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070890 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.070890 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036122 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036122 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036122 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036122 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33931.077819 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33931.077819 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44365.782673 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44365.782673 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42327.750962 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42327.750962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42327.750962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42327.750962 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 103000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5911.764706 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6058.823529 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 166286 # number of writebacks -system.cpu.dcache.writebacks::total 166286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191915 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 191915 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891806 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 891806 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1083721 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1083721 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1083721 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1083721 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62166 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62166 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143424 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143424 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205590 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205590 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205590 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205590 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1142650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1142650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4721135000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4721135000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5863785000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5863785000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5863785000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5863785000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002956 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002956 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005768 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005768 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005768 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005768 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18380.626066 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18380.626066 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32917.329038 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32917.329038 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28521.742303 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28521.742303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28521.742303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28521.742303 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 166337 # number of writebacks +system.cpu.dcache.writebacks::total 166337 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 189183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 189183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 892539 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 892539 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1081722 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1081722 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1081722 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1081722 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62260 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62260 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143404 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143404 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205664 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205664 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205664 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205664 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1244458000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1244458000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5521780000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5521780000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6766238000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6766238000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6766238000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6766238000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002961 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002961 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005771 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005771 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005771 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005771 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19988.082236 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19988.082236 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38505.062620 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38505.062620 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32899.476817 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32899.476817 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32899.476817 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32899.476817 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 137157 # number of replacements -system.cpu.l2cache.tagsinuse 29150.308284 # Cycle average of tags in use -system.cpu.l2cache.total_refs 155579 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 168030 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.925900 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 137209 # number of replacements +system.cpu.l2cache.tagsinuse 29108.919988 # Cycle average of tags in use +system.cpu.l2cache.total_refs 155222 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 168087 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.923462 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25379.974502 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1916.859149 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1853.474632 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.774535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.058498 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.056564 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.889597 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 86688 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32293 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 118981 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 166286 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 166286 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12465 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12465 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 86688 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 44758 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 131446 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 86688 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 44758 # number of overall hits -system.cpu.l2cache.overall_hits::total 131446 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8732 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 29871 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 38603 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 25319.531401 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1909.557763 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1879.830824 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.772691 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.058275 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.057368 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.888334 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 86239 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 32344 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4629566000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 281019000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5571700500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5852719500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 281019000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5571700500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5852719500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480451 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.245814 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31646.921087 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35350.722734 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35350.722734 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32153.203661 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34634.586097 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34506.721262 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32153.203661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34634.586097 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34506.721262 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini index db5db2a63..e15c6aa9f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout index 1808f3b15..d2ae983de 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:25:28 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:09:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 134036748000 because target called exit() +Exiting @ tick 134581343000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 9facba206..5c01fa696 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.134037 # Number of seconds simulated -sim_ticks 134036748000 # Number of ticks simulated -final_tick 134036748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.134581 # Number of seconds simulated +sim_ticks 134581343000 # Number of ticks simulated +final_tick 134581343000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2004374 # Simulator instruction rate (inst/s) -host_op_rate 2004373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3041175629 # Simulator tick rate (ticks/s) -host_mem_usage 226164 # Number of bytes of host memory used -host_seconds 44.07 # Real time elapsed on the host +host_inst_rate 1566292 # Simulator instruction rate (inst/s) +host_op_rate 1566291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2386143258 # Simulator tick rate (ticks/s) +host_mem_usage 226128 # Number of bytes of host memory used +host_seconds 56.40 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 160477 # Nu system.physmem.num_reads::total 168060 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115955 # Number of write requests responded to by this memory system.physmem.num_writes::total 115955 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3620738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 76624718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 80245456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3620738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3620738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 55366309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55366309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55366309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3620738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 76624718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 135611765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3606087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 76314649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 79920736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3606087 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3606087 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55142264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55142264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55142264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3606087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 76314649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 135063001 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 268073496 # number of cpu cycles simulated +system.cpu.numCycles 269162686 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 268073496 # Number of busy cycles +system.cpu.num_busy_cycles 269162686 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.539157 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.699205 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.539157 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913837 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913837 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1871.699205 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.913916 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.913916 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1388590000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1388590000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1388590000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1388590000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1388590000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1388590000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1390813000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1390813000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1390813000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1390813000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1390813000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1390813000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18166.701554 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18166.701554 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18166.701554 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18166.701554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18166.701554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18166.701554 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18195.784709 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18195.784709 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18195.784709 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18195.784709 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18195.784709 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18195.784709 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1159282000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1159282000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1159282000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1159282000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1159282000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1159282000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1161505000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1161505000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1161505000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1161505000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1161505000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1161505000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15166.701554 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15166.701554 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15166.701554 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15166.701554 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15166.701554 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15166.701554 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15195.784709 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15195.784709 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15195.784709 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15195.784709 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15195.784709 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15195.784709 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.827650 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.801621 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.827650 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995808 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995808 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 947396000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4078.801621 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995801 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995801 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2087582000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2087582000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7513268000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7513268000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9600850000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9600850000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9600850000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9600850000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2092728000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2092728000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7513894000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7513894000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9606622000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9606622000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9606622000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9606622000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34354.441629 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34354.441629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52328.824750 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52328.824750 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46983.762675 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46983.762675 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46983.762675 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46983.762675 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34439.127143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34439.127143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52333.184750 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52333.184750 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47012.009161 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47012.009161 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47012.009161 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47012.009161 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1905284000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1905284000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7082534000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7082534000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987818000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8987818000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8987818000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8987818000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1910430000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1910430000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7083160000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7083160000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8993590000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8993590000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8993590000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8993590000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.441629 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31354.441629 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49328.824750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49328.824750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43983.762675 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43983.762675 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43983.762675 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43983.762675 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31439.127143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31439.127143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49333.184750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49333.184750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44012.009161 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44012.009161 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44012.009161 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44012.009161 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 135625 # number of replacements -system.cpu.l2cache.tagsinuse 29002.202656 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29002.571879 # Cycle average of tags in use system.cpu.l2cache.total_refs 136279 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 166491 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.818537 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25777.846112 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1647.476120 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1576.880424 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.786677 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.050277 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.048123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.885077 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 25772.303239 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1646.708734 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1583.559905 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.786508 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.050254 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.048326 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.885088 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 68853 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31317 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 100170 # number of ReadReq hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 33fd8bc7c..0878a1dc0 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 462a53b1f..c4aefb2c9 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:13:16 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 16:29:16 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 23981004500 because target called exit() +Exiting @ tick 24460150500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 8d4101747..f26f3a389 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023981 # Number of seconds simulated -sim_ticks 23981004500 # Number of ticks simulated -final_tick 23981004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024460 # Number of seconds simulated +sim_ticks 24460150500 # Number of ticks simulated +final_tick 24460150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169152 # Simulator instruction rate (inst/s) -host_op_rate 240031 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57193739 # Simulator tick rate (ticks/s) -host_mem_usage 242580 # Number of bytes of host memory used -host_seconds 419.29 # Real time elapsed on the host -sim_insts 70924419 # Number of instructions simulated -sim_ops 100643666 # Number of ops (including micro ops) simulated +host_inst_rate 167024 # Simulator instruction rate (inst/s) +host_op_rate 237012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57603012 # Simulator tick rate (ticks/s) +host_mem_usage 242500 # Number of bytes of host memory used +host_seconds 424.63 # Real time elapsed on the host +sim_insts 70923824 # Number of instructions simulated +sim_ops 100643071 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8029184 # Number of bytes read from this memory -system.physmem.bytes_read::total 8356160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8028736 # Number of bytes read from this memory +system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417856 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417856 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 5417152 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417152 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125456 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130565 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84654 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84654 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13634792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 334814332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 348449124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13634792 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13634792 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 225922813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 225922813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 225922813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13634792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 334814332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 574371937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 125449 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84643 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84643 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13367702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 328237392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 341605094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13367702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13367702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 221468466 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 221468466 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 221468466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13367702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 328237392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 563073559 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +77,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 47962010 # number of cpu cycles simulated +system.cpu.numCycles 48920302 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16947214 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12982117 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 655322 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11804628 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7961599 # Number of BTB hits +system.cpu.BPredUnit.lookups 16960531 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12985874 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 661473 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11570513 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7976664 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1880669 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114490 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12764738 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87540471 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16947214 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9842268 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21772804 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2768546 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10027678 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 361 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12061426 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 218802 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46590944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.639937 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.350838 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1883015 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 115088 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12843999 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87580035 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16960531 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9859679 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21787094 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2782746 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10982319 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 606 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12079139 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 221673 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47647021 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582724 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336366 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24839551 53.31% 53.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2175787 4.67% 57.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1999394 4.29% 62.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2026993 4.35% 66.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1551688 3.33% 69.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1408138 3.02% 72.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 990048 2.12% 75.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1240896 2.66% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10358449 22.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25881368 54.32% 54.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2178299 4.57% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2007274 4.21% 63.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2021463 4.24% 67.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1548956 3.25% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1412983 2.97% 73.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 995678 2.09% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1240946 2.60% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10360054 21.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46590944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.353347 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.825204 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14883106 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8408681 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19993372 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1386692 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1919093 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3458129 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108409 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120163882 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 373498 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1919093 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16645469 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2316120 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 802815 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19569476 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5337971 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117636894 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9686 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4512387 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 221 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117778889 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541771281 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 541766916 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4365 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159536 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18619353 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37368 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37363 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12895568 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30067923 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22776958 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3590168 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4248242 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113315749 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51911 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108455143 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 350648 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12554662 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29999283 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14767 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46590944 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.327816 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.997244 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 47647021 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346697 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.790259 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15031484 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9298191 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19969978 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1421734 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1925634 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3462876 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109476 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 120212842 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 378015 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1925634 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16795731 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2963104 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 805180 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19544890 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5612482 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117675747 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12709 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4780104 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 263 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117787272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541948309 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541940540 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99158584 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18628688 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37002 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 36987 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13169886 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30082364 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22781735 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3607820 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4315548 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113341575 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51734 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108469975 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 351751 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12575588 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30093615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14709 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47647021 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.276532 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995144 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11127507 23.88% 23.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8067707 17.32% 41.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7375197 15.83% 57.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7162683 15.37% 72.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5557871 11.93% 84.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3930157 8.44% 92.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1905355 4.09% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881142 1.89% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 583325 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11903537 24.98% 24.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8354851 17.53% 42.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7454693 15.65% 58.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7158692 15.02% 73.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5519097 11.58% 84.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3907609 8.20% 92.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1895733 3.98% 96.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 881641 1.85% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 571168 1.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46590944 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47647021 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112830 4.40% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1425910 55.61% 60.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1025351 39.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112989 4.45% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1419251 55.85% 60.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1008989 39.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57362458 52.89% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91498 0.08% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57363382 52.88% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91507 0.08% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 129 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 228 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued @@ -239,160 +239,160 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29209051 26.93% 79.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21792000 20.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29217041 26.94% 79.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21797810 20.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108455143 # Type of FU issued -system.cpu.iq.rate 2.261272 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2564091 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023642 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 266415556 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125949072 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106420629 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 111019028 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 206 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2223683 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108469975 # Type of FU issued +system.cpu.iq.rate 2.217279 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2541231 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023428 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 267479180 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125995514 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106424512 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 773 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1272 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 111010818 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 388 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2214998 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2757457 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7931 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28755 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2217862 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2772017 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7458 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29087 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2222758 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1919093 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 944512 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 30820 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113447794 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342667 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30067923 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22776958 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 35363 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1047 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28755 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 424789 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 263529 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 688318 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107242187 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28840669 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1212956 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1925634 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 929341 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37355 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113473181 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 343640 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30082364 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22781735 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35157 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2560 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3541 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29087 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 428613 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 264355 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 692968 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107247329 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28841677 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1222646 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80134 # number of nop insts executed -system.cpu.iew.exec_refs 50312690 # number of memory reference insts executed -system.cpu.iew.exec_branches 14662886 # Number of branches executed -system.cpu.iew.exec_stores 21472021 # Number of stores executed -system.cpu.iew.exec_rate 2.235982 # Inst execution rate -system.cpu.iew.wb_sent 106754958 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106420762 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53610539 # num instructions producing a value -system.cpu.iew.wb_consumers 104702454 # num instructions consuming a value +system.cpu.iew.exec_nop 79872 # number of nop insts executed +system.cpu.iew.exec_refs 50315882 # number of memory reference insts executed +system.cpu.iew.exec_branches 14663606 # Number of branches executed +system.cpu.iew.exec_stores 21474205 # Number of stores executed +system.cpu.iew.exec_rate 2.192287 # Inst execution rate +system.cpu.iew.wb_sent 106761196 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106424699 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53424049 # num instructions producing a value +system.cpu.iew.wb_consumers 103788661 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.218855 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512028 # average fanout of values written-back +system.cpu.iew.wb_rate 2.175471 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514739 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 70929971 # The number of committed instructions -system.cpu.commit.commitCommittedOps 100649218 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 12799085 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37144 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 611847 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44671852 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.253079 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.750865 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 70929376 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100648623 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 12825262 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37025 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 616891 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45721388 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.201347 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.733819 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15424353 34.53% 34.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11724908 26.25% 60.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3540913 7.93% 68.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2916552 6.53% 75.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1906207 4.27% 79.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1948042 4.36% 83.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 684228 1.53% 85.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 590770 1.32% 86.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5935879 13.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16264410 35.57% 35.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11914734 26.06% 61.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3626051 7.93% 69.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2926022 6.40% 75.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880797 4.11% 80.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1911030 4.18% 84.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 689200 1.51% 85.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 582969 1.28% 87.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5926175 12.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44671852 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929971 # Number of instructions committed -system.cpu.commit.committedOps 100649218 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45721388 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929376 # Number of instructions committed +system.cpu.commit.committedOps 100648623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869562 # Number of memory references committed -system.cpu.commit.loads 27310466 # Number of loads committed +system.cpu.commit.refs 47869324 # Number of memory references committed +system.cpu.commit.loads 27310347 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13671985 # Number of branches committed +system.cpu.commit.branches 13671866 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486211 # Number of committed integer instructions. +system.cpu.commit.int_insts 91485735 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5935879 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5926175 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 152158977 # The number of ROB reads -system.cpu.rob.rob_writes 228826081 # The number of ROB writes -system.cpu.timesIdled 61655 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1371066 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924419 # Number of Instructions Simulated -system.cpu.committedOps 100643666 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924419 # Number of Instructions Simulated -system.cpu.cpi 0.676241 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.676241 # CPI: Total CPI of All Threads -system.cpu.ipc 1.478762 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.478762 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516206868 # number of integer regfile reads -system.cpu.int_regfile_writes 104370444 # number of integer regfile writes -system.cpu.fp_regfile_reads 520 # number of floating regfile reads -system.cpu.fp_regfile_writes 444 # number of floating regfile writes -system.cpu.misc_regfile_reads 146052754 # number of misc regfile reads -system.cpu.misc_regfile_writes 38556 # number of misc regfile writes -system.cpu.icache.replacements 29824 # number of replacements -system.cpu.icache.tagsinuse 1820.810833 # Cycle average of tags in use -system.cpu.icache.total_refs 12028408 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31867 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 377.456554 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 153243799 # The number of ROB reads +system.cpu.rob.rob_writes 228884039 # The number of ROB writes +system.cpu.timesIdled 52429 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1273281 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70923824 # Number of Instructions Simulated +system.cpu.committedOps 100643071 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70923824 # Number of Instructions Simulated +system.cpu.cpi 0.689758 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.689758 # CPI: Total CPI of All Threads +system.cpu.ipc 1.449783 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.449783 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516242048 # number of integer regfile reads +system.cpu.int_regfile_writes 104369908 # number of integer regfile writes +system.cpu.fp_regfile_reads 886 # number of floating regfile reads +system.cpu.fp_regfile_writes 750 # number of floating regfile writes +system.cpu.misc_regfile_reads 146091713 # number of misc regfile reads +system.cpu.misc_regfile_writes 38318 # number of misc regfile writes +system.cpu.icache.replacements 30244 # number of replacements +system.cpu.icache.tagsinuse 1815.033473 # Cycle average of tags in use +system.cpu.icache.total_refs 12045499 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32282 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 373.133604 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1820.810833 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.889068 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.889068 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12028408 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12028408 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12028408 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12028408 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12028408 # number of overall hits -system.cpu.icache.overall_hits::total 12028408 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33018 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33018 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33018 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33018 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33018 # number of overall misses -system.cpu.icache.overall_misses::total 33018 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 367424500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 367424500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 367424500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 367424500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 367424500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 367424500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12061426 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12061426 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12061426 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12061426 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12061426 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12061426 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002737 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002737 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002737 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11128.005936 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11128.005936 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11128.005936 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11128.005936 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1815.033473 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.886247 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.886247 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12045501 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12045501 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12045501 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12045501 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12045501 # number of overall hits +system.cpu.icache.overall_hits::total 12045501 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33638 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33638 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33638 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33638 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33638 # number of overall misses +system.cpu.icache.overall_misses::total 33638 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 406685000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 406685000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 406685000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 406685000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 406685000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 406685000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12079139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12079139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12079139 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12079139 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12079139 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12079139 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002785 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002785 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002785 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002785 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002785 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002785 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12090.046971 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12090.046971 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12090.046971 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12090.046971 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,254 +401,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1111 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1111 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1111 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1111 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1111 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31907 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31907 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31907 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31907 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31907 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31907 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244055000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 244055000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244055000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 244055000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244055000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 244055000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002645 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002645 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002645 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7648.948507 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7648.948507 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1313 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1313 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1313 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1313 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1313 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1313 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32325 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32325 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32325 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32325 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32325 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32325 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 274223500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 274223500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 274223500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 274223500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 274223500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 274223500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8483.325599 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8483.325599 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158597 # number of replacements -system.cpu.dcache.tagsinuse 4071.944277 # Cycle average of tags in use -system.cpu.dcache.total_refs 44611539 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162693 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.206874 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 262057000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4071.944277 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994127 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994127 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 52578719498 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 447000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54693550998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54693550998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54693550998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54693550998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26375363 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26375363 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 158501 # number of replacements +system.cpu.dcache.tagsinuse 4071.855185 # Cycle average of tags in use +system.cpu.dcache.total_refs 44605412 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162597 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 274.331089 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 272454000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4071.855185 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26278291 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26278291 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18287500 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18287500 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20317 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20317 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19158 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19158 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44565791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44565791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44565791 # number of overall hits +system.cpu.dcache.overall_hits::total 44565791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 106674 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 106674 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1562401 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1562401 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1669075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1669075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1669075 # number of overall misses +system.cpu.dcache.overall_misses::total 1669075 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2574319000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2574319000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63349260500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63349260500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 629500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 629500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 65923579500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 65923579500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 65923579500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 65923579500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26384965 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26384965 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20573 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20573 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19277 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19277 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46225264 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46225264 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46225264 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46225264 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003995 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003995 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078000 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078000 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001896 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001896 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035774 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035774 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035774 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.035774 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20070.718143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20070.718143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33959.153402 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33959.153402 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11461.538462 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11461.538462 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33074.201982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33074.201982 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20360 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20360 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19158 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19158 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46234866 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46234866 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46234866 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46234866 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004043 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004043 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078711 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078711 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002112 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002112 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036100 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036100 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036100 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036100 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24132.581510 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24132.581510 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40546.095721 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40546.095721 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14639.534884 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14639.534884 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39497.074427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39497.074427 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 202500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19600 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128124 # number of writebacks -system.cpu.dcache.writebacks::total 128124 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49671 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49671 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1441258 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1441258 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 39 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 39 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1490929 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1490929 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1490929 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1490929 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55698 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55698 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 128059 # number of writebacks +system.cpu.dcache.writebacks::total 128059 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51068 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51068 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1455366 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1455366 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1506434 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1506434 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1506434 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1506434 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55606 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55606 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107035 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107035 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162733 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162733 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162733 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162733 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 907626500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 907626500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3661924998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3661924998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4569551498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4569551498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4569551498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4569551498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 162641 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162641 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162641 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162641 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 982100000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 982100000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3836030000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3836030000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4818130000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4818130000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4818130000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4818130000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002107 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002107 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003520 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003520 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16295.495350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16295.495350 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34212.407138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34212.407138 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28080.054433 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28080.054433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28080.054433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28080.054433 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17661.763119 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17661.763119 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35839.024618 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35839.024618 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 97993 # number of replacements -system.cpu.l2cache.tagsinuse 28658.689941 # Cycle average of tags in use -system.cpu.l2cache.total_refs 86749 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128784 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.673601 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 97988 # number of replacements +system.cpu.l2cache.tagsinuse 28616.670846 # Cycle average of tags in use +system.cpu.l2cache.total_refs 87010 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 128775 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.675675 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25863.719355 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1158.363470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1636.607116 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.789298 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035350 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.049945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.874594 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26734 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32452 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 59186 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128124 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128124 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4717 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4717 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26734 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 37169 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 63903 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26734 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 37169 # number of overall hits -system.cpu.l2cache.overall_hits::total 63903 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 5128 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.110002 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31175.455937 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31171.803316 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 125449 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130558 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163941000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 752838000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 916779000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1147000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1147000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3241185000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3241185000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163941000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3994023000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4157964000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163941000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3994023000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4157964000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416346 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321544 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.840909 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.840909 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955972 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955972 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771533 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.669971 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771533 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.669971 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32088.667058 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32536.865762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32455.800616 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31679.731407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31679.731407 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index c08fcfcdd..4c2746778 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index b1460f18e..564b30c1c 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:20:08 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 16:37:12 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 132924820000 because target called exit() +Exiting @ tick 133513136000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index b1eb24a6a..250f6daa7 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132925 # Number of seconds simulated -sim_ticks 132924820000 # Number of ticks simulated -final_tick 132924820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133513 # Number of seconds simulated +sim_ticks 133513136000 # Number of ticks simulated +final_tick 133513136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1112405 # Simulator instruction rate (inst/s) -host_op_rate 1577419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2101158995 # Simulator tick rate (ticks/s) -host_mem_usage 240528 # Number of bytes of host memory used -host_seconds 63.26 # Real time elapsed on the host +host_inst_rate 1170283 # Simulator instruction rate (inst/s) +host_op_rate 1659492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2220265254 # Simulator tick rate (ticks/s) +host_mem_usage 240448 # Number of bytes of host memory used +host_seconds 60.13 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 125054 # Nu system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2059269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60210396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 62269665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2059269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2059269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40649985 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40649985 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40649985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2059269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60210396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 102919650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2050195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 59945083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61995278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2050195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2050195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40470864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40470864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40470864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2050195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59945083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 102466142 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 265849640 # number of cpu cycles simulated +system.cpu.numCycles 267026272 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 47862847 # nu system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 265849640 # Number of busy cycles +system.cpu.num_busy_cycles 267026272 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.286948 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1735.470121 # Cycle average of tags in use system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.286948 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847796 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847796 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1735.470121 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847398 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847398 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 444346000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 444346000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 444346000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 444346000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 444346000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 444346000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 445311000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 445311000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 445311000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 445311000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 445311000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 445311000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23500.423101 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23500.423101 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23500.423101 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23500.423101 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23500.423101 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23500.423101 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23551.459700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23551.459700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23551.459700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23551.459700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23551.459700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23551.459700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387622000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 387622000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387622000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 387622000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387622000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 387622000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 388587000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 388587000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 388587000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 388587000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 388587000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 388587000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20500.423101 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20500.423101 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20500.423101 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20500.423101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20500.423101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20500.423101 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20551.459700 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20551.459700 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20551.459700 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20551.459700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20551.459700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20551.459700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.906689 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.664624 # Cycle average of tags in use system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1079631000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.906689 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995339 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995339 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 1111220000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.664624 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1695470000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1695470000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5796770000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5796770000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7492240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7492240000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7492240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7492240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1699159000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1699159000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5797120000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5797120000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7496279000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7496279000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7496279000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7496279000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32010.535060 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32010.535060 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54159.223410 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54159.223410 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46827.085339 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46827.085339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46827.085339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46827.085339 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32080.183514 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32080.183514 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54162.493460 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54162.493460 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46852.329404 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46852.329404 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46852.329404 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46852.329404 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536572000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536572000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012246000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7012246000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012246000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7012246000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1540261000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1540261000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5476024000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5476024000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7016285000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7016285000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7016285000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7016285000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29010.535060 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29010.535060 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.223410 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.223410 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.085339 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.085339 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.085339 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.085339 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.183514 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29080.183514 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51162.493460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51162.493460 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43852.329404 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43852.329404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43852.329404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43852.329404 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 96735 # number of replacements -system.cpu.l2cache.tagsinuse 28872.647154 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 28857.116422 # Cycle average of tags in use system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26446.371833 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 949.934371 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1476.340950 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.807079 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.028990 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.045054 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.881123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 26427.849240 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 949.438432 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1479.828749 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.806514 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.028975 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.045161 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.880649 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14631 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 30253 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 44884 # number of ReadReq hits diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 480848980..221d86591 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout index 2acf8263c..98fb0b2cd 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:06:58 -gem5 started Jun 28 2012 22:58:54 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 12:32:55 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 202680458000 because target called exit() +Exiting @ tick 204097192000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index b1d40b1a6..a6ef18324 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202680 # Number of seconds simulated -sim_ticks 202680458000 # Number of ticks simulated -final_tick 202680458000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.204097 # Number of seconds simulated +sim_ticks 204097192000 # Number of ticks simulated +final_tick 204097192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1918134 # Simulator instruction rate (inst/s) -host_op_rate 1942970 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2892641209 # Simulator tick rate (ticks/s) -host_mem_usage 229316 # Number of bytes of host memory used -host_seconds 70.07 # Real time elapsed on the host +host_inst_rate 1236624 # Simulator instruction rate (inst/s) +host_op_rate 1252636 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1877926206 # Simulator tick rate (ticks/s) +host_mem_usage 229284 # Number of bytes of host memory used +host_seconds 108.68 # Real time elapsed on the host sim_insts 134398975 # Number of instructions simulated sim_ops 136139203 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 123533 # Nu system.physmem.num_reads::total 133934 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3284303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39007767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 42292069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3284303 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3284303 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26156325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26156325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26156325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3284303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39007767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 68448395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3261505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38736995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41998500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3261505 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3261505 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 25974762 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25974762 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 25974762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3261505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38736995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67973262 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 405360916 # number of cpu cycles simulated +system.cpu.numCycles 408194384 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398975 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 58160249 # nu system.cpu.num_load_insts 37275868 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 405360916 # Number of busy cycles +system.cpu.num_busy_cycles 408194384 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.741762 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2004.409813 # Cycle average of tags in use system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 144318639000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.741762 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978878 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978878 # Average percentage of cache occupancy +system.cpu.icache.warmup_cycle 145330300000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 2004.409813 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.978716 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.978716 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366560 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3055178000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3055178000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3055178000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3055178000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3055178000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3055178000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3060544000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3060544000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3060544000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3060544000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3060544000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3060544000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553584 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553584 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553584 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16335.753700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16335.753700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16335.753700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16335.753700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16335.753700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16335.753700 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16364.445205 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16364.445205 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16364.445205 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16364.445205 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16364.445205 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16364.445205 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2494106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2494106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2494106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2494106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2494106000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2494106000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2499472000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2499472000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2499472000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2499472000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2499472000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2499472000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.753700 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.753700 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.753700 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.753700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.753700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.753700 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13364.445205 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13364.445205 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13364.445205 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13364.445205 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13364.445205 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13364.445205 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.606333 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.412837 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 776708000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.606333 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997951 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997951 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 812044000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.412837 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997904 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185802 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185802 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1569302000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1569302000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5728156000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5728156000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 420000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 420000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7297458000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7297458000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7297458000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7297458000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1571682000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1571682000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5728295000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5728295000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 430000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 430000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7299977000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7299977000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7299977000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7299977000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34490.911888 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34490.911888 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54468.791602 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54468.791602 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 28000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 28000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48435.634496 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48435.634496 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48435.634496 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48435.634496 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34543.220730 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34543.220730 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54470.113347 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54470.113347 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 28666.666667 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 28666.666667 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48452.353929 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48452.353929 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48452.353929 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48452.353929 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1432805000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1432805000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412664000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412664000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6845469000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6845469000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6845469000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6845469000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1435185000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1435185000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412803000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412803000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 385000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 385000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6847988000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6847988000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6847988000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6847988000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.911888 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31490.911888 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.634496 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.634496 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.634496 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.634496 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31543.220730 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31543.220730 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51470.113347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51470.113347 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25666.666667 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25666.666667 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45452.353929 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45452.353929 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45452.353929 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45452.353929 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 101560 # number of replacements -system.cpu.l2cache.tagsinuse 29288.840921 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29278.940429 # Cycle average of tags in use system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 24773.097821 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3265.951230 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1249.791870 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.756015 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.099669 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.038141 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.893824 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 24760.226438 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3263.271337 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1255.442654 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.755622 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.099587 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.038313 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.893522 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 176623 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 23301 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 199924 # number of ReadReq hits |