diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/long/se/50.vortex/ref | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/long/se/50.vortex/ref')
9 files changed, 2361 insertions, 1750 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 62028d00d..9b354cbb8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042726 # Number of seconds simulated -sim_ticks 42725646500 # Number of ticks simulated -final_tick 42725646500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043732 # Number of seconds simulated +sim_ticks 43731802500 # Number of ticks simulated +final_tick 43731802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44211 # Simulator instruction rate (inst/s) -host_op_rate 44211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21382391 # Simulator tick rate (ticks/s) -host_mem_usage 280712 # Number of bytes of host memory used -host_seconds 1998.17 # Real time elapsed on the host +host_inst_rate 69429 # Simulator instruction rate (inst/s) +host_op_rate 69429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34369620 # Simulator tick rate (ticks/s) +host_mem_usage 233240 # Number of bytes of host memory used +host_seconds 1272.40 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 454528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory -system.physmem.bytes_read::total 10592896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 454528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 454528 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10592960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454592 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7102 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7103 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165514 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10638294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 237289985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 247928279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10638294 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10638294 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 170759452 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 170759452 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 170759452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10638294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 237289985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 418687731 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165514 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 10394998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 231830554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 242225552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10394998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10394998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166830718 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166830718 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166830718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10394998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 231830554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 409056270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165515 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279511 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10592896 # Total number of bytes read from memory +system.physmem.cpureqs 279512 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10592960 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10592896 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10572 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10442 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10515 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7006 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7262 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7040 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6934 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10439 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10013 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9796 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10510 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10590 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10187 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10581 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10594 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7259 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6998 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7226 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6938 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7284 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 42725626000 # Total gap between requests +system.physmem.totGap 43731782000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165514 # Categorize read packet sizes +system.physmem.readPktSize::6 165515 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 113997 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 62488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 76381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 72899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,12 +124,12 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see @@ -147,65 +147,209 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 7078163250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9669555750 # Sum of mem lat for all requests -system.physmem.totBusLat 827570000 # Total cycles spent in databus access -system.physmem.totBankLat 1763822500 # Total cycles spent in bank access -system.physmem.avgQLat 42764.74 # Average queueing delay per request -system.physmem.avgBankLat 10656.64 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 48863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 366.074289 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.394514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 748.149039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 19835 40.59% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7665 15.69% 56.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4199 8.59% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2953 6.04% 70.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2157 4.41% 75.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1715 3.51% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1297 2.65% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1110 2.27% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 804 1.65% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 685 1.40% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 483 0.99% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 536 1.10% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 409 0.84% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 338 0.69% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 255 0.52% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 348 0.71% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 228 0.47% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 211 0.43% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 159 0.33% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 209 0.43% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 394 0.81% 94.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 305 0.62% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 602 1.23% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 201 0.41% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 151 0.31% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 39 0.08% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 155 0.32% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 66 0.14% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 55 0.11% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 29 0.06% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 79 0.16% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 42 0.09% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 46 0.09% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 24 0.05% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 45 0.09% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 30 0.06% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 23 0.05% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 17 0.03% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 14 0.03% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 23 0.05% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 11 0.02% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 12 0.02% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 11 0.02% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 10 0.02% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 6 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 12 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 5 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 7 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 6 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 6 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 7 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 9 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 6 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 6 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 5 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 6 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 3 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 6 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 164 0.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48863 # Bytes accessed per row activation +system.physmem.totQLat 6289978250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8777494500 # Sum of mem lat for all requests +system.physmem.totBusLat 827575000 # Total cycles spent in databus access +system.physmem.totBankLat 1659941250 # Total cycles spent in bank access +system.physmem.avgQLat 38002.47 # Average queueing delay per request +system.physmem.avgBankLat 10028.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58421.38 # Average memory access latency -system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 170.76 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53031.41 # Average memory access latency +system.physmem.avgRdBW 242.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 166.83 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 242.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 166.83 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.27 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.23 # Average read queue length over time -system.physmem.avgWrQLen 10.41 # Average write queue length over time -system.physmem.readRowHits 148885 # Number of row buffer hits during reads -system.physmem.writeRowHits 71702 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.90 # Row buffer hit rate for writes -system.physmem.avgGap 152858.48 # Average gap between requests -system.cpu.branchPred.lookups 18741806 # Number of BP lookups -system.cpu.branchPred.condPredicted 12317440 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4774691 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15571063 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4663219 # Number of BTB hits +system.physmem.busUtil 3.20 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.20 # Average read queue length over time +system.physmem.avgWrQLen 10.42 # Average write queue length over time +system.physmem.readRowHits 153768 # Number of row buffer hits during reads +system.physmem.writeRowHits 76872 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.90 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.43 # Row buffer hit rate for writes +system.physmem.avgGap 156457.62 # Average gap between requests +system.membus.throughput 409056270 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 34624 # Transaction distribution +system.membus.trans_dist::ReadResp 34624 # Transaction distribution +system.membus.trans_dist::Writeback 113997 # Transaction distribution +system.membus.trans_dist::ReadExReq 130891 # Transaction distribution +system.membus.trans_dist::ReadExResp 130891 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 445027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 445027 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17888768 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17888768 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17888768 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1215256500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 1522914250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.5 # Layer utilization (%) +system.cpu.branchPred.lookups 18742056 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318265 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4775163 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 15487144 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4660091 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.947981 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1660960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 30.090061 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1660966 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277542 # DTB read hits +system.cpu.dtb.read_hits 20277593 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367690 # DTB read accesses -system.cpu.dtb.write_hits 14728781 # DTB write hits +system.cpu.dtb.read_accesses 20367741 # DTB read accesses +system.cpu.dtb.write_hits 14728959 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736033 # DTB write accesses -system.cpu.dtb.data_hits 35006323 # DTB hits +system.cpu.dtb.write_accesses 14736211 # DTB write accesses +system.cpu.dtb.data_hits 35006552 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103723 # DTB accesses -system.cpu.itb.fetch_hits 12368482 # ITB hits -system.cpu.itb.fetch_misses 10998 # ITB misses +system.cpu.dtb.data_accesses 35103952 # DTB accesses +system.cpu.itb.fetch_hits 12367361 # ITB hits +system.cpu.itb.fetch_misses 10891 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12379480 # ITB accesses +system.cpu.itb.fetch_accesses 12378252 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,34 +363,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 85451294 # number of cpu cycles simulated +system.cpu.numCycles 87463606 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8073687 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10668119 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74170009 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8070350 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10671706 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74169774 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126489259 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 66071 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126489024 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66036 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293701 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14164942 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35060353 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4447581 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 216610 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4664191 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9108383 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.865790 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777788 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293666 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14166320 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060384 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4447706 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216957 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4664663 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9107934 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.869161 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44778070 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77182336 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77195811 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 229187 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15880194 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69571100 # Number of cycles cpu stages are processed. -system.cpu.activity 81.416087 # Percentage of cycles cpu is active +system.cpu.timesIdled 233969 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17892398 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69571208 # Number of cycles cpu stages are processed. +system.cpu.activity 79.543036 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -258,194 +402,214 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.967293 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.990072 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.967293 # CPI: Total CPI of All Threads -system.cpu.ipc 1.033813 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.990072 # CPI: Total CPI of All Threads +system.cpu.ipc 1.010028 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.033813 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32800214 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52651080 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.615310 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 42999576 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42451718 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 49.679433 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 42421796 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43029498 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 50.355584 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 63338785 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22112509 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.877325 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 39402182 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46049112 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 53.889309 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 84283 # number of replacements -system.cpu.icache.tagsinuse 1908.281182 # Cycle average of tags in use -system.cpu.icache.total_refs 12251335 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 86329 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.914478 # Average number of references to valid blocks. +system.cpu.ipc_total 1.010028 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34814257 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52649349 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.195722 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45010578 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42453028 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.537935 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44433795 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43029811 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.197390 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65350614 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22112992 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.282507 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41414421 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46049185 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.649539 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 84399 # number of replacements +system.cpu.icache.tagsinuse 1906.561640 # Cycle average of tags in use +system.cpu.icache.total_refs 12250118 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 86445 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.709966 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1908.281182 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.931778 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.931778 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12251335 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12251335 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12251335 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12251335 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12251335 # number of overall hits -system.cpu.icache.overall_hits::total 12251335 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117137 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117137 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117137 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117137 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117137 # number of overall misses -system.cpu.icache.overall_misses::total 117137 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1898913500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1898913500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1898913500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1898913500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1898913500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1898913500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12368472 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12368472 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12368472 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12368472 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12368472 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12368472 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009471 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009471 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009471 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009471 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009471 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009471 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16211.047748 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16211.047748 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16211.047748 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16211.047748 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16211.047748 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16211.047748 # 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miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569413 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082267 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775215 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569413 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64029.498733 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55055.575742 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 56896.340583 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91814.472508 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91814.472508 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64029.498733 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85428.330057 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84510.132804 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64029.498733 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85428.330057 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84510.132804 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082168 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.569187 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082168 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.569187 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81013.796987 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73115.075760 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74735.472505 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104943.796747 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104943.796747 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81013.796987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99414.176325 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98624.532520 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81013.796987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99414.176325 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98624.532520 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -456,84 +620,84 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks system.cpu.l2cache.writebacks::total 113997 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7102 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7103 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34623 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34624 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7102 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7103 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165514 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7102 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165515 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165514 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366405391 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1172806844 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1539212235 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10428442785 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10428442785 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366405391 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11601249629 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11967655020 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366405391 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11601249629 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11967655020 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082267 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51591.860180 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73234.664224 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72305.998405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51591.860180 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73234.664224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72305.998405 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082168 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569187 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082168 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569187 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68591.405040 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60689.391737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62310.463840 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92801.970724 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92801.970724 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68591.405040 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87223.035502 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86423.467662 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68591.405040 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87223.035502 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86423.467662 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 200250 # number of replacements -system.cpu.dcache.tagsinuse 4078.188542 # Cycle average of tags in use -system.cpu.dcache.total_refs 33754850 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 204346 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.184785 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 253407000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.188542 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995651 # 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number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135165 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135165 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135165 # number of overall misses -system.cpu.dcache.overall_misses::total 1135165 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3869387500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3869387500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76774000000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76774000000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80643387500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80643387500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80643387500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80643387500 # number of overall miss cycles +system.cpu.dcache.replacements 200251 # number of replacements +system.cpu.dcache.tagsinuse 4076.684340 # Cycle average of tags in use +system.cpu.dcache.total_refs 33754860 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 165.184025 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 292193000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.684340 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995284 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995284 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180280 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180280 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574580 # 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number of WriteReq accesses(hits+misses) @@ -542,56 +706,56 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004754 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004754 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.707255 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.707255 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73908.778388 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73908.778388 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71041.115168 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71041.115168 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5035459 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116380 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51581.108989 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51581.108989 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83950.870093 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 83950.870093 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81203.152433 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81203.152433 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5824366 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116607 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.267391 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.948682 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks -system.cpu.dcache.writebacks::total 168351 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35632 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35632 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895187 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895187 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930819 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930819 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930819 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930819 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks +system.cpu.dcache.writebacks::total 168352 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35591 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35591 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895217 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895217 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930808 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930808 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930808 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930808 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1910017000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1910017000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12290144000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12290144000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14200161000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14200161000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14200161000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14200161000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2407208517 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2407208517 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14006251501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14006251501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16413460018 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16413460018 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16413460018 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16413460018 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -600,14 +764,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31432.330580 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31432.330580 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85597.882713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85597.882713 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39613.746227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39613.746227 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97550.156714 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97550.156714 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 8eb5d8593..42c254d5a 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023932 # Number of seconds simulated -sim_ticks 23931821000 # Number of ticks simulated -final_tick 23931821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024943 # Number of seconds simulated +sim_ticks 24942850000 # Number of ticks simulated +final_tick 24942850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61921 # Simulator instruction rate (inst/s) -host_op_rate 61921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18618559 # Simulator tick rate (ticks/s) -host_mem_usage 281736 # Number of bytes of host memory used -host_seconds 1285.37 # Real time elapsed on the host +host_inst_rate 187895 # Simulator instruction rate (inst/s) +host_op_rate 187895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58883311 # Simulator tick rate (ticks/s) +host_mem_usage 236320 # Number of bytes of host memory used +host_seconds 423.60 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154048 # Number of bytes read from this memory -system.physmem.bytes_read::total 10644032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158657 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166313 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20474163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 424290655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 444764818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20474163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20474163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 304906175 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 304906175 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 304906175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20474163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 424290655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 749670992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166313 # Total number of read requests seen -system.physmem.writeReqs 114015 # Total number of write requests seen -system.physmem.cpureqs 280328 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10644032 # Total number of bytes read from memory -system.physmem.bytesWritten 7296960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10644032 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 490496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153472 # Number of bytes read from this memory +system.physmem.bytes_read::total 10643968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296640 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296640 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7664 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158648 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166312 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114010 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114010 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19664794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 407069441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 426734234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19664794 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19664794 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 292534333 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 292534333 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 292534333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19664794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 407069441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 719268568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166312 # Total number of read requests seen +system.physmem.writeReqs 114010 # Total number of write requests seen +system.physmem.cpureqs 280322 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10643968 # Total number of bytes read from memory +system.physmem.bytesWritten 7296640 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10643968 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296640 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10321 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10258 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10491 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9976 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10114 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7242 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7009 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7276 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10460 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10055 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9845 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10323 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10639 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10621 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10623 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7257 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7176 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6990 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23931788000 # Total gap between requests +system.physmem.totGap 24942817000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166313 # Categorize read packet sizes +system.physmem.readPktSize::6 166312 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114015 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 67890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114010 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 73936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,12 +124,12 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see @@ -146,66 +146,208 @@ system.physmem.wrQLenPdf::18 4957 # Wh system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 7245305500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9792324250 # Sum of mem lat for all requests -system.physmem.totBusLat 831555000 # Total cycles spent in databus access -system.physmem.totBankLat 1715463750 # Total cycles spent in bank access -system.physmem.avgQLat 43564.80 # Average queueing delay per request -system.physmem.avgBankLat 10314.79 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 49789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 360.286489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.159256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 741.433360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 20689 41.55% 41.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7785 15.64% 57.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4196 8.43% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3037 6.10% 71.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2069 4.16% 75.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1703 3.42% 79.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1326 2.66% 81.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1152 2.31% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 751 1.51% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 622 1.25% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 468 0.94% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 538 1.08% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 428 0.86% 89.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 311 0.62% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 271 0.54% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 335 0.67% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 282 0.57% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 173 0.35% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 131 0.26% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 297 0.60% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 411 0.83% 94.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 172 0.35% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 311 0.62% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 639 1.28% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 258 0.52% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 81 0.16% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 48 0.10% 97.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 163 0.33% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 101 0.20% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 35 0.07% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 33 0.07% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 83 0.17% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 54 0.11% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 28 0.06% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 37 0.07% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 43 0.09% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 20 0.04% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 23 0.05% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 20 0.04% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 10 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 11 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 8 0.02% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 16 0.03% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 8 0.02% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 7 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 17 0.03% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 7 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 10 0.02% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 8 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 7 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 8 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 5 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 6 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 8 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 13 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 5 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 9 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 5 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 10 0.02% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 165 0.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49789 # Bytes accessed per row activation +system.physmem.totQLat 6526905250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8951626500 # Sum of mem lat for all requests +system.physmem.totBusLat 831550000 # Total cycles spent in databus access +system.physmem.totBankLat 1593171250 # Total cycles spent in bank access +system.physmem.avgQLat 39245.42 # Average queueing delay per request +system.physmem.avgBankLat 9579.53 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58879.59 # Average memory access latency -system.physmem.avgRdBW 444.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 304.91 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 444.76 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 304.91 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53824.94 # Average memory access latency +system.physmem.avgRdBW 426.73 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 292.53 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 426.73 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 292.53 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.86 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.41 # Average read queue length over time -system.physmem.avgWrQLen 9.84 # Average write queue length over time -system.physmem.readRowHits 149147 # Number of row buffer hits during reads -system.physmem.writeRowHits 70867 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.16 # Row buffer hit rate for writes -system.physmem.avgGap 85370.67 # Average gap between requests -system.cpu.branchPred.lookups 16571170 # Number of BP lookups -system.cpu.branchPred.condPredicted 10694499 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 427048 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11996955 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7368452 # Number of BTB hits +system.physmem.busUtil 5.62 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.36 # Average read queue length over time +system.physmem.avgWrQLen 10.09 # Average write queue length over time +system.physmem.readRowHits 154174 # Number of row buffer hits during reads +system.physmem.writeRowHits 76335 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.95 # Row buffer hit rate for writes +system.physmem.avgGap 88979.16 # Average gap between requests +system.membus.throughput 719268568 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35517 # Transaction distribution +system.membus.trans_dist::ReadResp 35517 # Transaction distribution +system.membus.trans_dist::Writeback 114010 # Transaction distribution +system.membus.trans_dist::ReadExReq 130795 # Transaction distribution +system.membus.trans_dist::ReadExResp 130795 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 446634 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 446634 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17940608 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940608 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1221780000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 4.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 1527507000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.1 # Layer utilization (%) +system.cpu.branchPred.lookups 16555988 # Number of BP lookups +system.cpu.branchPred.condPredicted 10692092 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 419935 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11595461 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7351910 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.419352 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1995064 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41482 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.403344 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1990234 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41425 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22414538 # DTB read hits -system.cpu.dtb.read_misses 219003 # DTB read misses -system.cpu.dtb.read_acv 44 # DTB read access violations -system.cpu.dtb.read_accesses 22633541 # DTB read accesses -system.cpu.dtb.write_hits 15711620 # DTB write hits -system.cpu.dtb.write_misses 41172 # DTB write misses +system.cpu.dtb.read_hits 22410816 # DTB read hits +system.cpu.dtb.read_misses 219473 # DTB read misses +system.cpu.dtb.read_acv 42 # DTB read access violations +system.cpu.dtb.read_accesses 22630289 # DTB read accesses +system.cpu.dtb.write_hits 15705108 # DTB write hits +system.cpu.dtb.write_misses 41065 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 15752792 # DTB write accesses -system.cpu.dtb.data_hits 38126158 # DTB hits -system.cpu.dtb.data_misses 260175 # DTB misses -system.cpu.dtb.data_acv 46 # DTB access violations -system.cpu.dtb.data_accesses 38386333 # DTB accesses -system.cpu.itb.fetch_hits 13959521 # ITB hits -system.cpu.itb.fetch_misses 35718 # ITB misses +system.cpu.dtb.write_accesses 15746173 # DTB write accesses +system.cpu.dtb.data_hits 38115924 # DTB hits +system.cpu.dtb.data_misses 260538 # DTB misses +system.cpu.dtb.data_acv 44 # DTB access violations +system.cpu.dtb.data_accesses 38376462 # DTB accesses +system.cpu.itb.fetch_hits 13936543 # ITB hits +system.cpu.itb.fetch_misses 35109 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13995239 # ITB accesses +system.cpu.itb.fetch_accesses 13971652 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,139 +361,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 47863646 # number of cpu cycles simulated +system.cpu.numCycles 49885704 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15840434 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105551509 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16571170 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9363516 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19590320 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2026285 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6404003 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7727 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314524 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13959521 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 209834 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43625903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.419469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.136822 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15828757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105472202 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16555988 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9342144 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19569330 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2015634 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7564714 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 312127 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13936543 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 209148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44745227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.357172 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120107 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24035583 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1538195 3.53% 58.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1379254 3.16% 61.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1510848 3.46% 65.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4145444 9.50% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1853786 4.25% 79.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 680324 1.56% 80.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1070140 2.45% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7412329 16.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25175897 56.26% 56.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1533640 3.43% 59.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1372500 3.07% 62.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510966 3.38% 66.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4145174 9.26% 75.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1852523 4.14% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674526 1.51% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069811 2.39% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7410190 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43625903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346216 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.205254 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16922417 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5946391 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18583818 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 809277 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1364000 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3756330 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107588 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103803150 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 305479 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1364000 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17385205 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3661755 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85469 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18882151 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2247323 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102504062 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 474 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2634 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2121433 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61730148 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123523109 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123071072 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 452037 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44745227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.331878 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.114277 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16915257 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7099488 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18565359 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 807394 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1357729 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3748109 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107416 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103728039 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304294 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1357729 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17378057 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4787405 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84706 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18857243 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2280087 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102449322 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 562 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2762 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2150788 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61699088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123470125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123020099 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 450026 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9183267 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5533 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4628434 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23258454 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16285736 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1194307 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 458239 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90833658 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5326 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88506663 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 99992 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10775029 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4713260 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43625903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.028764 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109591 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9152207 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5534 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4701242 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23248702 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16281518 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1196604 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 458974 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90797694 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5272 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88473068 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 98121 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10747304 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4709427 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 689 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44745227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.977263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.106527 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15319091 35.11% 35.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6943764 15.92% 51.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5619916 12.88% 63.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4753240 10.90% 74.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4687288 10.74% 85.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2648310 6.07% 91.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1927283 4.42% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1307141 3.00% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 419870 0.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16442789 36.75% 36.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6947095 15.53% 52.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5617294 12.55% 64.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4751397 10.62% 75.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4688341 10.48% 85.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2649423 5.92% 91.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1924303 4.30% 96.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1305783 2.92% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 418802 0.94% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43625903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44745227 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126036 6.75% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 786436 42.09% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 955888 51.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126164 6.77% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 785807 42.18% 48.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 951202 51.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49401565 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43900 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49382358 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43890 0.05% 55.87% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121291 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121091 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38958 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121219 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121003 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38951 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -373,84 +515,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22873159 25.84% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15906558 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22865563 25.84% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15899938 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88506663 # Type of FU issued -system.cpu.iq.rate 1.849142 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1868360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021110 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222003769 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101216135 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86588999 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603812 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 415953 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90073048 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301975 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1468681 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88473068 # Type of FU issued +system.cpu.iq.rate 1.773515 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1863173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021059 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223048793 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101154216 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86567905 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603864 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414189 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294216 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90034241 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 302000 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1467603 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2981816 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4834 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18324 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1672359 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2972064 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5071 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18375 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1668141 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2816 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 91767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2922 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 100269 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1364000 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2689383 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74209 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100326423 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 230599 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23258454 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16285736 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5326 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60174 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 487 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18324 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 205931 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161115 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 367046 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87639637 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22636834 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 867026 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1357729 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3744152 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 78814 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100285943 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 219681 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23248702 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16281518 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5272 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60147 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 593 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18375 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 199378 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160408 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 359786 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87617560 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22633363 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 855508 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9487439 # number of nop insts executed -system.cpu.iew.exec_refs 38389952 # number of memory reference insts executed -system.cpu.iew.exec_branches 15091410 # Number of branches executed -system.cpu.iew.exec_stores 15753118 # Number of stores executed -system.cpu.iew.exec_rate 1.831027 # Inst execution rate -system.cpu.iew.wb_sent 87274889 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86883155 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33355142 # num instructions producing a value -system.cpu.iew.wb_consumers 43763107 # num instructions consuming a value +system.cpu.iew.exec_nop 9482977 # number of nop insts executed +system.cpu.iew.exec_refs 38379854 # number of memory reference insts executed +system.cpu.iew.exec_branches 15087965 # Number of branches executed +system.cpu.iew.exec_stores 15746491 # Number of stores executed +system.cpu.iew.exec_rate 1.756366 # Inst execution rate +system.cpu.iew.wb_sent 87252732 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86862121 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33357056 # num instructions producing a value +system.cpu.iew.wb_consumers 43763173 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.815222 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762175 # average fanout of values written-back +system.cpu.iew.wb_rate 1.741223 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762217 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8976597 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8947131 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 322215 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42261903 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.090315 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.803165 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 315269 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43387498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.036086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.786442 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19374336 45.84% 45.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7031479 16.64% 62.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3426891 8.11% 70.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2063946 4.88% 75.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2064090 4.88% 80.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1160431 2.75% 83.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1098411 2.60% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 723960 1.71% 87.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5318359 12.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20491808 47.23% 47.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7040185 16.23% 63.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3430647 7.91% 71.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2065344 4.76% 76.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2060078 4.75% 80.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1160326 2.67% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1096269 2.53% 86.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 719123 1.66% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5323718 12.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42261903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43387498 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,192 +603,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5318359 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5323718 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132943471 # The number of ROB reads -system.cpu.rob.rob_writes 196001226 # The number of ROB writes -system.cpu.timesIdled 70501 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4237743 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 134034241 # The number of ROB reads +system.cpu.rob.rob_writes 195936054 # The number of ROB writes +system.cpu.timesIdled 84426 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5140477 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.601364 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.601364 # CPI: Total CPI of All Threads -system.cpu.ipc 1.662885 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.662885 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115989230 # number of integer regfile reads -system.cpu.int_regfile_writes 57546941 # number of integer regfile writes -system.cpu.fp_regfile_reads 249538 # number of floating regfile reads -system.cpu.fp_regfile_writes 239891 # number of floating regfile writes -system.cpu.misc_regfile_reads 38020 # number of misc regfile reads +system.cpu.cpi 0.626770 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.626770 # CPI: Total CPI of All Threads +system.cpu.ipc 1.595482 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.595482 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115957750 # number of integer regfile reads +system.cpu.int_regfile_writes 57532597 # number of integer regfile writes +system.cpu.fp_regfile_reads 249573 # number of floating regfile reads +system.cpu.fp_regfile_writes 239887 # number of floating regfile writes +system.cpu.misc_regfile_reads 38017 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 91116 # number of replacements -system.cpu.icache.tagsinuse 1928.908016 # Cycle average of tags in use -system.cpu.icache.total_refs 13854125 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93164 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 148.706850 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19689670000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1928.908016 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.941850 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.941850 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13854125 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13854125 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13854125 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13854125 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13854125 # number of overall hits -system.cpu.icache.overall_hits::total 13854125 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105395 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105395 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105395 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105395 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105395 # number of overall misses -system.cpu.icache.overall_misses::total 105395 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1863166499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1863166499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1863166499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1863166499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1863166499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1863166499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13959520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13959520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13959520 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13959520 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13959520 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13959520 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007550 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007550 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007550 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007550 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007550 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007550 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.940120 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17677.940120 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.940120 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17677.940120 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.940120 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17677.940120 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 817 # number of cycles access was blocked +system.cpu.toL2Bus.throughput 1201112463 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155760 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143412 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143412 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 187195 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580089 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 767284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5990208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23968960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 29959168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29959168 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 402997500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 140404482 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 308361998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.icache.replacements 91549 # number of replacements +system.cpu.icache.tagsinuse 1926.731072 # Cycle average of tags in use +system.cpu.icache.total_refs 13830286 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93597 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.764202 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20183588000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1926.731072 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.940787 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.940787 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13830286 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13830286 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13830286 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13830286 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13830286 # number of overall hits +system.cpu.icache.overall_hits::total 13830286 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106255 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106255 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106255 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106255 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106255 # number of overall misses +system.cpu.icache.overall_misses::total 106255 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2059581499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2059581499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2059581499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2059581499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2059581499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2059581499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13936541 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13936541 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13936541 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13936541 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13936541 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13936541 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007624 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007624 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007624 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007624 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007624 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007624 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19383.384302 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19383.384302 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19383.384302 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19383.384302 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19383.384302 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19383.384302 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 622 # 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number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114015 # number of writebacks -system.cpu.l2cache.writebacks::total 114015 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7657 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35516 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130798 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130798 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7657 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158657 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166314 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7657 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158657 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166314 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 406509618 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1270706940 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1677216558 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10579175855 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10579175855 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406509618 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11849882795 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12256392413 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406509618 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11849882795 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12256392413 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082188 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448038 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228627 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912075 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912075 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082188 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771727 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.556696 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082188 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771727 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.556696 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53089.933133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45612.080118 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47224.252675 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80881.786075 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80881.786075 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53089.933133 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74688.685624 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73694.291599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53089.933133 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74688.685624 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73694.291599 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114010 # number of writebacks +system.cpu.l2cache.writebacks::total 114010 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7665 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27853 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35518 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130795 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130795 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7665 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158648 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166313 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7665 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158648 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166313 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 533046000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1768410500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2301456500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12396543000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12396543000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 533046000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14164953500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14697999500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 533046000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14164953500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14697999500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081893 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228030 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081893 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771732 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555911 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081893 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771732 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555911 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69542.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63490.844792 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64796.905794 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94778.416606 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94778.416606 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69542.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89285.421184 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88375.529874 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69542.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89285.421184 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88375.529874 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201491 # number of replacements -system.cpu.dcache.tagsinuse 4076.541723 # Cycle average of tags in use -system.cpu.dcache.total_refs 34211115 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205587 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.406996 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 178802000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.541723 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995249 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995249 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20636989 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20636989 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574068 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574068 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 58 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 58 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34211057 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34211057 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34211057 # number of overall hits -system.cpu.dcache.overall_hits::total 34211057 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039309 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039309 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306495 # number of overall misses -system.cpu.dcache.overall_misses::total 1306495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12035490500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12035490500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 79072087779 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 79072087779 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91107578279 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91107578279 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91107578279 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91107578279 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20904175 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20904175 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201478 # number of replacements +system.cpu.dcache.tagsinuse 4074.502987 # Cycle average of tags in use +system.cpu.dcache.total_refs 34204494 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205574 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.385311 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 214402000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4074.502987 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994752 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994752 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20630348 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20630348 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574089 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574089 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34204437 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34204437 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34204437 # number of overall hits +system.cpu.dcache.overall_hits::total 34204437 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 266891 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 266891 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039288 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039288 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306179 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306179 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306179 # number of overall misses +system.cpu.dcache.overall_misses::total 1306179 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15635191500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15635191500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89961325949 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89961325949 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105596517449 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105596517449 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105596517449 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105596517449 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20897239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20897239 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35517552 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35517552 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35517552 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35517552 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012781 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012781 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036784 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036784 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036784 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036784 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45045.363530 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45045.363530 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76081.403874 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76081.403874 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69734.348986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69734.348986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69734.348986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69734.348986 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4381626 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112316 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35510616 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35510616 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35510616 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35510616 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012772 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012772 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071119 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071119 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036783 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036783 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036783 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036783 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58582.685441 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58582.685441 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86560.535625 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 86560.535625 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80843.833387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80843.833387 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5220473 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 159 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112927 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.011592 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.228741 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 159 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168939 # number of writebacks -system.cpu.dcache.writebacks::total 168939 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205002 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205002 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895906 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895906 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100908 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100908 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100908 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100908 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62184 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62184 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143403 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143403 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205587 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205587 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205587 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205587 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2020761500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2020761500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12440224991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12440224991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14460986491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14460986491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14460986491 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14460986491 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168941 # number of writebacks +system.cpu.dcache.writebacks::total 168941 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204728 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204728 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895877 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895877 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100605 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100605 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100605 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100605 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62163 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62163 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143411 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143411 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205574 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205574 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205574 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205574 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2517427002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2517427002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14256184493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14256184493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16773611495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16773611495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16773611495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16773611495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005788 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005788 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005788 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005788 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32496.486234 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32496.486234 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86750.102794 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86750.102794 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40497.192896 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40497.192896 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99407.887073 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99407.887073 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index e11282e38..db9503e0b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2426632 # Simulator instruction rate (inst/s) -host_op_rate 2426631 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1214706702 # Simulator tick rate (ticks/s) -host_mem_usage 272072 # Number of bytes of host memory used -host_seconds 36.40 # Real time elapsed on the host +host_inst_rate 2564036 # Simulator instruction rate (inst/s) +host_op_rate 2564035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1283487470 # Simulator tick rate (ticks/s) +host_mem_usage 224620 # Number of bytes of host memory used +host_seconds 34.45 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 2072610067 # Wr system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 12937468537 # Throughput (bytes/s) +system.membus.data_through_bus 572107835 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index a53da63fa..9b4737e22 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu sim_ticks 133634727000 # Number of ticks simulated final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 996502 # Simulator instruction rate (inst/s) -host_op_rate 996501 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1507427540 # Simulator tick rate (ticks/s) -host_mem_usage 280652 # Number of bytes of host memory used -host_seconds 88.65 # Real time elapsed on the host +host_inst_rate 671194 # Simulator instruction rate (inst/s) +host_op_rate 671194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1015328507 # Simulator tick rate (ticks/s) +host_mem_usage 233108 # Number of bytes of host memory used +host_seconds 131.62 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 54587966 # To system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 133682617 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 34272 # Transaction distribution +system.membus.trans_dist::ReadResp 34272 # Transaction distribution +system.membus.trans_dist::Writeback 113982 # Transaction distribution +system.membus.trans_dist::ReadExReq 130881 # Transaction distribution +system.membus.trans_dist::ReadExResp 130881 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 444288 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17864640 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -405,5 +421,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 215108158 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 152872 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577063 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 729935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 4891904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23854016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 28745920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 5f2b5197b..419a13ff5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025535 # Number of seconds simulated -sim_ticks 25534556000 # Number of ticks simulated -final_tick 25534556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026649 # Number of seconds simulated +sim_ticks 26649062500 # Number of ticks simulated +final_tick 26649062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124211 # Simulator instruction rate (inst/s) -host_op_rate 176271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44729688 # Simulator tick rate (ticks/s) -host_mem_usage 254184 # Number of bytes of host memory used -host_seconds 570.86 # Real time elapsed on the host +host_inst_rate 95593 # Simulator instruction rate (inst/s) +host_op_rate 135659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35926621 # Simulator tick rate (ticks/s) +host_mem_usage 255136 # Number of bytes of host memory used +host_seconds 741.76 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 297536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943488 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 297536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 297536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4649 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124117 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128766 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11652288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 311087767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 322740055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11652288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11652288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 210400369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 210400369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 210400369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11652288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 311087767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 533140424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128767 # Total number of read requests seen -system.physmem.writeReqs 83945 # Total number of write requests seen -system.physmem.cpureqs 213037 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8241024 # Total number of bytes read from memory -system.physmem.bytesWritten 5372480 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8241024 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372480 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128762 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11193790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 298039152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 309232942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11193790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11193790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 201613096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 201613096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 201613096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11193790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 298039152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 510846038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128763 # Total number of read requests seen +system.physmem.writeReqs 83950 # Total number of write requests seen +system.physmem.cpureqs 213025 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8240768 # Total number of bytes read from memory +system.physmem.bytesWritten 5372800 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8240768 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372800 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 325 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 7974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8060 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8166 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8116 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8007 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8002 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7985 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8125 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8030 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7988 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7949 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5143 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5312 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8141 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8168 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8450 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8090 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7962 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8062 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7813 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 7880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8005 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5268 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5049 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5031 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5089 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5253 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5145 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5343 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5363 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5451 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25534539500 # Total gap between requests +system.physmem.totGap 26649044000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128767 # Categorize read packet sizes +system.physmem.readPktSize::6 128763 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83945 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 70152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2075 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83950 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 75538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 51656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,11 +124,11 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3648 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -142,50 +142,196 @@ system.physmem.wrQLenPdf::14 3650 # Wh system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3209361000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5253486000 # Sum of mem lat for all requests -system.physmem.totBusLat 643825000 # Total cycles spent in databus access -system.physmem.totBankLat 1400300000 # Total cycles spent in bank access -system.physmem.avgQLat 24924.17 # Average queueing delay per request -system.physmem.avgBankLat 10874.85 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40799.02 # Average memory access latency -system.physmem.avgRdBW 322.74 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 210.40 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 322.74 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 210.40 # Average consumed write bandwidth in MB/s +system.physmem.bytesPerActivate::samples 34891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 390.104497 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.978164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 858.430673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 13421 38.47% 38.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5383 15.43% 53.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3065 8.78% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2226 6.38% 69.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1625 4.66% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1388 3.98% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1071 3.07% 80.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 870 2.49% 83.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 590 1.69% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 488 1.40% 86.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 448 1.28% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 588 1.69% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 296 0.85% 90.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 306 0.88% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 186 0.53% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 205 0.59% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 126 0.36% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 210 0.60% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 103 0.30% 93.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 233 0.67% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 114 0.33% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 336 0.96% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 140 0.40% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 305 0.87% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 63 0.18% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 139 0.40% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 46 0.13% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 83 0.24% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 24 0.07% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 56 0.16% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 58 0.17% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 11 0.03% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 27 0.08% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 19 0.05% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 23 0.07% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 10 0.03% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 17 0.05% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 8 0.02% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 14 0.04% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 16 0.05% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 16 0.05% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 9 0.03% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 15 0.04% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 7 0.02% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 7 0.02% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 12 0.03% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 11 0.03% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 7 0.02% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 3 0.01% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 9 0.03% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 3 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 7 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 3 0.01% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 2 0.01% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 7 0.02% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 2 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 4 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 3 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 7 0.02% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 3 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 4 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 4 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 2 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 2 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 3 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 3 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 3 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 2 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 3 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 4 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 238 0.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 34891 # Bytes accessed per row activation +system.physmem.totQLat 2799338750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4801886250 # Sum of mem lat for all requests +system.physmem.totBusLat 643800000 # Total cycles spent in databus access +system.physmem.totBankLat 1358747500 # Total cycles spent in bank access +system.physmem.avgQLat 21740.58 # Average queueing delay per request +system.physmem.avgBankLat 10552.48 # Average bank access latency per request +system.physmem.avgBusLat 4999.96 # Average bus latency per request +system.physmem.avgMemAccLat 37293.02 # Average memory access latency +system.physmem.avgRdBW 309.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 201.61 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 309.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 201.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 4.17 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.21 # Average read queue length over time -system.physmem.avgWrQLen 9.90 # Average write queue length over time -system.physmem.readRowHits 116738 # Number of row buffer hits during reads -system.physmem.writeRowHits 52892 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.01 # Row buffer hit rate for writes -system.physmem.avgGap 120042.78 # Average gap between requests -system.cpu.branchPred.lookups 16612549 # Number of BP lookups -system.cpu.branchPred.condPredicted 12751503 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 599939 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10534593 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7757405 # Number of BTB hits +system.physmem.busUtil 3.99 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.18 # Average read queue length over time +system.physmem.avgWrQLen 10.01 # Average write queue length over time +system.physmem.readRowHits 120254 # Number of row buffer hits during reads +system.physmem.writeRowHits 57565 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.57 # Row buffer hit rate for writes +system.physmem.avgGap 125281.69 # Average gap between requests +system.membus.throughput 510846038 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26509 # Transaction distribution +system.membus.trans_dist::ReadResp 26508 # Transaction distribution +system.membus.trans_dist::Writeback 83950 # Transaction distribution +system.membus.trans_dist::UpgradeReq 312 # Transaction distribution +system.membus.trans_dist::UpgradeResp 312 # Transaction distribution +system.membus.trans_dist::ReadExReq 102254 # Transaction distribution +system.membus.trans_dist::ReadExResp 102254 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 342099 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 342099 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13613568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 13613568 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13613568 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 926784500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1200135938 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.5 # Layer utilization (%) +system.cpu.branchPred.lookups 16620839 # Number of BP lookups +system.cpu.branchPred.condPredicted 12757336 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 602395 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10635009 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7765773 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.637444 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1822464 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113740 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.020841 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1824331 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113161 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +375,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 51069113 # number of cpu cycles simulated +system.cpu.numCycles 53298126 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12514697 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85141272 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16612549 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9579869 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21174766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2353264 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10532727 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 498 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11663165 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 178973 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 45949088 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.594403 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.336122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12535190 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85154971 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16620839 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9590104 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21184086 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2355794 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10829442 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 551 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11674707 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 181091 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46276167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.576733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.331391 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24794811 53.96% 53.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2137100 4.65% 58.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1960912 4.27% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2040333 4.44% 67.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1467005 3.19% 70.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1375299 2.99% 73.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 957293 2.08% 75.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1188429 2.59% 78.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10027906 21.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25111993 54.27% 54.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2139332 4.62% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1963886 4.24% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2043329 4.42% 67.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1467358 3.17% 70.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1375070 2.97% 73.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 956833 2.07% 75.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1188482 2.57% 78.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10029884 21.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 45949088 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.325295 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.667177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14598304 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8880725 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19456140 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1390682 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1623237 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3327841 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105063 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116768795 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 361627 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1623237 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16304724 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2541710 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 873068 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19090805 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5515544 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114897326 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 145 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17204 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4661371 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 307 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115217977 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529361609 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529355204 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6405 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46276167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.311847 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.597710 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14619512 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9177970 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19466340 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1388431 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1623914 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3328977 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104776 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116789336 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 361687 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1623914 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16330804 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2680643 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1000847 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19093672 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5546287 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114905556 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 219 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17136 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4693151 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1312 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115218637 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529387920 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529379803 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8117 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16085305 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20097 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20095 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13032825 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29592002 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22430174 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3871274 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4372916 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111465960 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35763 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107205680 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 272682 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10729594 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25689497 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1977 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 45949088 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.333141 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.988541 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16085965 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20302 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20297 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13065620 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29609265 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22417131 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3885027 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4397806 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111472584 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35916 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107208843 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 271699 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10738438 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25737967 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2130 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46276167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.316718 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.989507 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10727082 23.35% 23.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8071187 17.57% 40.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7423916 16.16% 57.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7121409 15.50% 72.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5405071 11.76% 84.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3914661 8.52% 92.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1842461 4.01% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 872329 1.90% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 570972 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11020528 23.81% 23.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8094858 17.49% 41.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7429249 16.05% 57.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7154901 15.46% 72.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5386733 11.64% 84.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3906460 8.44% 92.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1842144 3.98% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 871664 1.88% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 569630 1.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 45949088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46276167 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112030 4.53% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1365113 55.14% 59.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 998480 40.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112593 4.57% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1348878 54.73% 59.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1003122 40.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56613296 52.81% 52.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91558 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56608598 52.80% 52.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91438 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 214 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued @@ -384,84 +530,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28880685 26.94% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21619920 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28894537 26.95% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21614012 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107205680 # Type of FU issued -system.cpu.iq.rate 2.099227 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2475625 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023092 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263108167 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122259769 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105531182 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 588 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 948 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 171 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109681012 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2183832 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107208843 # Type of FU issued +system.cpu.iq.rate 2.011494 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2464595 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022989 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263429476 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122274650 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105524045 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 671 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1168 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 196 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109673111 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2189921 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2284894 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30581 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1874436 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2302157 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6684 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29801 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1861393 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 495 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 27 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 724 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1623237 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1048241 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45255 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111511491 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 294294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29592002 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22430174 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19843 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6298 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5233 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30581 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 389128 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 180293 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 569421 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106181674 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28584421 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1024006 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1623914 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1145014 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 48197 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111518283 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 295309 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29609265 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22417131 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19996 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6449 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5406 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29801 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 392238 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181031 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573269 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106181942 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28595303 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1026901 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9768 # number of nop insts executed -system.cpu.iew.exec_refs 49919693 # number of memory reference insts executed -system.cpu.iew.exec_branches 14596236 # Number of branches executed -system.cpu.iew.exec_stores 21335272 # Number of stores executed -system.cpu.iew.exec_rate 2.079176 # Inst execution rate -system.cpu.iew.wb_sent 105750982 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105531353 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53247115 # num instructions producing a value -system.cpu.iew.wb_consumers 103478594 # num instructions consuming a value +system.cpu.iew.exec_nop 9783 # number of nop insts executed +system.cpu.iew.exec_refs 49924361 # number of memory reference insts executed +system.cpu.iew.exec_branches 14597950 # Number of branches executed +system.cpu.iew.exec_stores 21329058 # Number of stores executed +system.cpu.iew.exec_rate 1.992227 # Inst execution rate +system.cpu.iew.wb_sent 105744224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105524241 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53247487 # num instructions producing a value +system.cpu.iew.wb_consumers 103444790 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.066442 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514571 # average fanout of values written-back +system.cpu.iew.wb_rate 1.979887 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514743 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10879947 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10886753 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 496884 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44325851 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.270288 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.765576 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 499558 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44652253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.253692 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.763005 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15270109 34.45% 34.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11622339 26.22% 60.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3461273 7.81% 68.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2876315 6.49% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1875935 4.23% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1955485 4.41% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 687541 1.55% 85.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 562645 1.27% 86.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6014209 13.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15559873 34.85% 34.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11688259 26.18% 61.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3454288 7.74% 68.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2872185 6.43% 75.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1868727 4.19% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1932277 4.33% 83.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 683931 1.53% 85.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 562545 1.26% 86.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6030168 13.50% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44325851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44652253 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,204 +618,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6014209 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6030168 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149798718 # The number of ROB reads -system.cpu.rob.rob_writes 224657070 # The number of ROB writes -system.cpu.timesIdled 74104 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5120025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150115967 # The number of ROB reads +system.cpu.rob.rob_writes 224671489 # The number of ROB writes +system.cpu.timesIdled 79206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7021959 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.720220 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.720220 # CPI: Total CPI of All Threads -system.cpu.ipc 1.388464 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.388464 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511419502 # number of integer regfile reads -system.cpu.int_regfile_writes 103305182 # number of integer regfile writes -system.cpu.fp_regfile_reads 846 # number of floating regfile reads -system.cpu.fp_regfile_writes 738 # number of floating regfile writes -system.cpu.misc_regfile_reads 49163804 # number of misc regfile reads +system.cpu.cpi 0.751656 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.751656 # CPI: Total CPI of All Threads +system.cpu.ipc 1.330396 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.330396 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511415343 # number of integer regfile reads +system.cpu.int_regfile_writes 103300902 # number of integer regfile writes +system.cpu.fp_regfile_reads 1012 # number of floating regfile reads +system.cpu.fp_regfile_writes 876 # number of floating regfile writes +system.cpu.misc_regfile_reads 49160884 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.icache.replacements 28595 # number of replacements -system.cpu.icache.tagsinuse 1814.564534 # Cycle average of tags in use -system.cpu.icache.total_refs 11628419 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30629 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379.653890 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 776266857 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 87116 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 87115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129077 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 62962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454559 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 517521 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1998208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18655488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 20653696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20653696 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 33088 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 290859995 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 47617981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 243817935 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.icache.replacements 29381 # number of replacements +system.cpu.icache.tagsinuse 1810.408207 # Cycle average of tags in use +system.cpu.icache.total_refs 11639182 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 31418 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 370.462219 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.564534 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.886018 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.886018 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11628429 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11628429 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11628429 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11628429 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11628429 # number of overall hits -system.cpu.icache.overall_hits::total 11628429 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34736 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34736 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34736 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34736 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34736 # number of overall misses -system.cpu.icache.overall_misses::total 34736 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739850999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739850999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 739850999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739850999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 739850999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739850999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11663165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11663165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11663165 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11663165 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11663165 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11663165 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002978 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002978 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002978 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002978 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002978 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21299.257226 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21299.257226 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21299.257226 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21299.257226 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21299.257226 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21299.257226 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1371 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1810.408207 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.883988 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.883988 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11639193 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11639193 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11639193 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 845054999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 845054999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11674706 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11674706 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11674706 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11674706 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11674706 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11674706 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003042 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003042 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003042 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003042 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003042 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003042 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23795.652268 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23795.652268 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23795.652268 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23795.652268 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1082 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 598675499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 598675499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 598675499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002655 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002655 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002655 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19337.063921 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19337.063921 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19337.063921 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19337.063921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19337.063921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19337.063921 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31740 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31740 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31740 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31740 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31740 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31740 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 686303518 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 686303518 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 686303518 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 686303518 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 686303518 # 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average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21622.669124 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21622.669124 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21622.669124 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 95632 # number of replacements -system.cpu.l2cache.tagsinuse 30087.760177 # Cycle average of tags in use -system.cpu.l2cache.total_refs 88021 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 126747 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.694462 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 95633 # number of replacements +system.cpu.l2cache.tagsinuse 29922.978563 # Cycle average of tags in use +system.cpu.l2cache.total_refs 88824 # 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number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26045310 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18267055 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18267055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15985 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15985 # number of LoadLockedReq hits +system.cpu.dcache.replacements 158319 # number of replacements +system.cpu.dcache.tagsinuse 4069.477080 # Cycle average of tags in use +system.cpu.dcache.total_refs 44347755 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162415 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.052089 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 350225000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4069.477080 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.993525 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.993525 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26048553 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26048553 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266688 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266688 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15980 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15980 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44312365 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44312365 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44312365 # number of overall hits -system.cpu.dcache.overall_hits::total 44312365 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124675 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124675 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1582846 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1582846 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707521 # number of overall misses -system.cpu.dcache.overall_misses::total 1707521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4257063500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4257063500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98390759981 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98390759981 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 860000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 860000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102647823481 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102647823481 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102647823481 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102647823481 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26169985 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26169985 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44315241 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44315241 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44315241 # number of overall hits +system.cpu.dcache.overall_hits::total 44315241 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125407 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125407 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583213 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583213 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708620 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708620 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708620 # number of overall misses +system.cpu.dcache.overall_misses::total 1708620 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5134620500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5134620500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 123147327479 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 123147327479 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 951500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 951500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 128281947979 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 128281947979 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 128281947979 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 128281947979 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26173960 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26173960 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16024 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46019886 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46019886 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46019886 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46019886 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079741 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079741 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002621 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002621 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037104 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037104 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037104 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037104 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34145.285743 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34145.285743 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62160.665018 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62160.665018 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20476.190476 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20476.190476 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60115.116289 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60115.116289 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60115.116289 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60115.116289 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3743 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.572519 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46023861 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46023861 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46023861 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46023861 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004791 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004791 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002746 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002746 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037125 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037125 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037125 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037125 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40943.651471 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40943.651471 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77783.170981 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77783.170981 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21625 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21625 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75079.273319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75079.273319 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5184 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1288 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.751724 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 80.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129075 # number of writebacks -system.cpu.dcache.writebacks::total 129075 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69278 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69278 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475504 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475504 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544782 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544782 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544782 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544782 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55397 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55397 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107342 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107342 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162739 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162739 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162739 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162739 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878555500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878555500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6809217490 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6809217490 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8687772990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8687772990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8687772990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8687772990 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129077 # number of writebacks +system.cpu.dcache.writebacks::total 129077 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69998 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69998 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475881 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475881 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545879 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545879 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545879 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545879 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55409 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55409 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162741 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162741 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162741 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162741 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243387065 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243387065 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8465944990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8465944990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10709332055 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10709332055 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10709332055 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10709332055 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33910.780367 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33910.780367 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63434.792439 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63434.792439 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53384.701823 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53384.701823 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53384.701823 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53384.701823 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.773918 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.773918 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78876.243711 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78876.243711 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 0248ad642..9f4bab8c0 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932157000 # Number of ticks simulated final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1242714 # Simulator instruction rate (inst/s) -host_op_rate 1763527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 945130731 # Simulator tick rate (ticks/s) -host_mem_usage 286616 # Number of bytes of host memory used -host_seconds 57.06 # Real time elapsed on the host +host_inst_rate 2080365 # Simulator instruction rate (inst/s) +host_op_rate 2952231 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1582195312 # Simulator tick rate (ticks/s) +host_mem_usage 241268 # Number of bytes of host memory used +host_seconds 34.09 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 100632428 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1458502967 # Wr system.physmem.bw_total::cpu.inst 5795805126 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3434566060 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9230371187 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9230371187 # Throughput (bytes/s) +system.membus.data_through_bus 497813828 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index ddc9fbf9d..9c1dc992d 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu sim_ticks 132689045000 # Number of ticks simulated final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 652363 # Simulator instruction rate (inst/s) -host_op_rate 925068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1230026759 # Simulator tick rate (ticks/s) -host_mem_usage 295072 # Number of bytes of host memory used -host_seconds 107.88 # Real time elapsed on the host +host_inst_rate 438025 # Simulator instruction rate (inst/s) +host_op_rate 621131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 825892843 # Simulator tick rate (ticks/s) +host_mem_usage 249772 # Number of bytes of host memory used +host_seconds 160.66 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 40471887 # To system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 102119538 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 25532 # Transaction distribution +system.membus.trans_dist::ReadResp 25532 # Transaction distribution +system.membus.trans_dist::Writeback 83909 # Transaction distribution +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 339533 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13550144 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 148145463 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 37816 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 448235 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 486051 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1210112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18447168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 19657280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 4cce8cf2a..0c3e0f3fc 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu sim_ticks 68148672000 # Number of ticks simulated final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2091817 # Simulator instruction rate (inst/s) -host_op_rate 2118902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1060681468 # Simulator tick rate (ticks/s) -host_mem_usage 281256 # Number of bytes of host memory used -host_seconds 64.25 # Real time elapsed on the host +host_inst_rate 2813738 # Simulator instruction rate (inst/s) +host_op_rate 2850169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1426739476 # Simulator tick rate (ticks/s) +host_mem_usage 233072 # Number of bytes of host memory used +host_seconds 47.77 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory @@ -35,6 +35,9 @@ system.physmem.bw_write::total 1318924454 # Wr system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11383698247 # Throughput (bytes/s) +system.membus.data_through_bus 775783918 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 136297345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 97e5107ce..4b553d931 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.202242 # Nu sim_ticks 202242260000 # Number of ticks simulated final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1033030 # Simulator instruction rate (inst/s) -host_op_rate 1046406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1554493166 # Simulator tick rate (ticks/s) -host_mem_usage 289840 # Number of bytes of host memory used -host_seconds 130.10 # Real time elapsed on the host +host_inst_rate 840510 # Simulator instruction rate (inst/s) +host_op_rate 851393 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1264790801 # Simulator tick rate (ticks/s) +host_mem_usage 241580 # Number of bytes of host memory used +host_seconds 159.90 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 26223758 # To system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 67847660 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 30277 # Transaction distribution +system.membus.trans_dist::ReadResp 30277 # Transaction distribution +system.membus.trans_dist::Writeback 82868 # Transaction distribution +system.membus.trans_dist::ReadExReq 101256 # Transaction distribution +system.membus.trans_dist::ReadExResp 101256 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 345934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 345934 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13721664 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 404484520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -393,5 +409,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 146097102 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374048 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 425326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 799374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11969536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 17577472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 29547008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |