stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

4 files changed, 19 insertions, 55 deletions

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 7a3a9c70d..c69a77e9f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.059447                       # Nu
 sim_ticks                                 59447065000                       # Number of ticks simulated
 final_tick                                59447065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 412945                       # Simulator instruction rate (inst/s)
-host_op_rate                                   412945                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              277576735                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261724                       # Number of bytes of host memory used
-host_seconds                                   214.16                       # Real time elapsed on the host
+host_inst_rate                                 371878                       # Simulator instruction rate (inst/s)
+host_op_rate                                   371878                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              249972170                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261720                       # Number of bytes of host memory used
+host_seconds                                   237.81                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -442,8 +442,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       168424                       # number of writebacks
 system.cpu.dcache.writebacks::total            168424                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28112                       # number of ReadReq MSHR hits
@@ -486,7 +484,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            152872                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1932.382407                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            25430610                       # Total number of references to valid blocks.
@@ -547,8 +544,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       152872                       # number of writebacks
 system.cpu.icache.writebacks::total            152872                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154921                       # number of ReadReq MSHR misses
@@ -575,7 +570,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334
 system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           133382                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30429.048447                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             403995                       # Total number of references to valid blocks.
@@ -684,8 +678,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       114469                       # number of writebacks
 system.cpu.l2cache.writebacks::total           114469                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          115                       # number of CleanEvict MSHR misses
@@ -740,7 +732,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       713421                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       353638                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 8a6383ef9..41c072959 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.022275                       # Nu
 sim_ticks                                 22275010500                       # Number of ticks simulated
 final_tick                                22275010500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 279038                       # Simulator instruction rate (inst/s)
-host_op_rate                                   279038                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               78093188                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 259704                       # Simulator instruction rate (inst/s)
+host_op_rate                                   259704                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               72682241                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 263768                       # Number of bytes of host memory used
-host_seconds                                   285.24                       # Real time elapsed on the host
+host_seconds                                   306.47                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -694,8 +694,6 @@ system.cpu.dcache.blocked::no_mshrs             89218                       # nu
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.036921                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   137.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       168806                       # number of writebacks
 system.cpu.dcache.writebacks::total            168806                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207108                       # number of ReadReq MSHR hits
@@ -738,7 +736,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             90292                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1916.963164                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            13622372                       # Total number of references to valid blocks.
@@ -799,8 +796,6 @@ system.cpu.icache.blocked::no_mshrs                12                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    47.750000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        90292                       # number of writebacks
 system.cpu.icache.writebacks::total             90292                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12531                       # number of ReadReq MSHR hits
@@ -833,7 +828,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17004.672897
 system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           133082                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30595.837110                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             280630                       # Total number of references to valid blocks.
@@ -942,8 +936,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       114419                       # number of writebacks
 system.cpu.l2cache.writebacks::total           114419                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          111                       # number of CleanEvict MSHR misses
@@ -998,7 +990,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       589565                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       291710                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index ec22c8c38..c5d95ec77 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.056803                       # Nu
 sim_ticks                                 56802974500                       # Number of ticks simulated
 final_tick                                56802974500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 208655                       # Simulator instruction rate (inst/s)
-host_op_rate                                   266840                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              167132713                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280072                       # Number of bytes of host memory used
-host_seconds                                   339.87                       # Real time elapsed on the host
+host_inst_rate                                 222036                       # Simulator instruction rate (inst/s)
+host_op_rate                                   283951                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              177850276                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280068                       # Number of bytes of host memory used
+host_seconds                                   319.39                       # Real time elapsed on the host
 sim_insts                                    70915150                       # Number of instructions simulated
 sim_ops                                      90690106                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -542,8 +542,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       128389                       # number of writebacks
 system.cpu.dcache.writebacks::total            128389                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22138                       # number of ReadReq MSHR hits
@@ -594,7 +592,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             43497                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1852.676989                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            24844377                       # Total number of references to valid blocks.
@@ -654,8 +651,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        43497                       # number of writebacks
 system.cpu.icache.writebacks::total             43497                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        45540                       # number of ReadReq MSHR misses
@@ -682,7 +677,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144
 system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements            96391                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        29870.997301                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             163417                       # Total number of references to valid blocks.
@@ -791,8 +785,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        86215                       # number of writebacks
 system.cpu.l2cache.writebacks::total            86215                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
@@ -857,7 +849,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       406029                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       199980                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7832                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 5ae3909df..8db6a9814 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.033525                       # Nu
 sim_ticks                                 33524756000                       # Number of ticks simulated
 final_tick                                33524756000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 145211                       # Simulator instruction rate (inst/s)
-host_op_rate                                   185708                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               68655135                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 282260                       # Number of bytes of host memory used
-host_seconds                                   488.31                       # Real time elapsed on the host
+host_inst_rate                                 160372                       # Simulator instruction rate (inst/s)
+host_op_rate                                   205097                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               75822829                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282256                       # Number of bytes of host memory used
+host_seconds                                   442.15                       # Real time elapsed on the host
 sim_insts                                    70907652                       # Number of instructions simulated
 sim_ops                                      90682607                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -796,8 +796,6 @@ system.cpu.dcache.blocked::no_mshrs                 6                       # nu
 system.cpu.dcache.blocked::no_targets          131418                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs            8                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    22.123925                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       486293                       # number of writebacks
 system.cpu.dcache.writebacks::total            486293                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       267392                       # number of ReadReq MSHR hits
@@ -850,7 +848,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            325000                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.229072                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            22083387                       # Total number of references to valid blocks.
@@ -911,8 +908,6 @@ system.cpu.icache.blocked::no_mshrs             16495                       # nu
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    16.015580                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    24.500000                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       325000                       # number of writebacks
 system.cpu.icache.writebacks::total            325000                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         9178                       # number of ReadReq MSHR hits
@@ -945,7 +940,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037
 system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued       822902                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified       826054                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit         2760                       # number of redundant prefetches already in prefetch queue
@@ -1070,8 +1064,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.unused_prefetches              424                       # number of HardPF blocks evicted w/o reference
 system.cpu.l2cache.writebacks::writebacks        97140                       # number of writebacks
 system.cpu.l2cache.writebacks::total            97140                       # number of writebacks
@@ -1155,7 +1147,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1623643                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       811337                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        80260                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.