diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se/50.vortex/ref | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se/50.vortex/ref')
4 files changed, 2672 insertions, 2656 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 15844baba..e086bc978 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.059549 # Number of seconds simulated -sim_ticks 59549031000 # Number of ticks simulated -final_tick 59549031000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059474 # Number of seconds simulated +sim_ticks 59473862000 # Number of ticks simulated +final_tick 59473862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 320796 # Simulator instruction rate (inst/s) -host_op_rate 320796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216005540 # Simulator tick rate (ticks/s) -host_mem_usage 307628 # Number of bytes of host memory used -host_seconds 275.68 # Real time elapsed on the host +host_inst_rate 342067 # Simulator instruction rate (inst/s) +host_op_rate 342067 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 230037089 # Simulator tick rate (ticks/s) +host_mem_usage 307480 # Number of bytes of host memory used +host_seconds 258.54 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 500352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10147264 # Number of bytes read from this memory -system.physmem.bytes_read::total 10647616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 500352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 500352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7320640 # Number of bytes written to this memory -system.physmem.bytes_written::total 7320640 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7818 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158551 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166369 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114385 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114385 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8402353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 170401832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 178804186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8402353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8402353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122934662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122934662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122934662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8402353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 170401832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 301738848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166369 # Number of read requests accepted -system.physmem.writeReqs 114385 # Number of write requests accepted -system.physmem.readBursts 166369 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114385 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10647296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 7318592 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10647616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7320640 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 432448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10149376 # Number of bytes read from this memory +system.physmem.bytes_read::total 10581824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 432448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 432448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7325760 # Number of bytes written to this memory +system.physmem.bytes_written::total 7325760 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158584 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165341 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114465 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114465 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7271228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 170652715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 177923942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7271228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7271228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 123176127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 123176127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 123176127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7271228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 170652715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 301100070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165341 # Number of read requests accepted +system.physmem.writeReqs 114465 # Number of write requests accepted +system.physmem.readBursts 165341 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114465 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10581376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7323904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10581824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7325760 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10447 # Per bank write bursts -system.physmem.perBankRdBursts::1 10506 # Per bank write bursts -system.physmem.perBankRdBursts::2 10283 # Per bank write bursts -system.physmem.perBankRdBursts::3 10092 # Per bank write bursts -system.physmem.perBankRdBursts::4 10413 # Per bank write bursts -system.physmem.perBankRdBursts::5 10414 # Per bank write bursts -system.physmem.perBankRdBursts::6 9828 # Per bank write bursts -system.physmem.perBankRdBursts::7 10274 # Per bank write bursts -system.physmem.perBankRdBursts::8 10580 # Per bank write bursts -system.physmem.perBankRdBursts::9 10645 # Per bank write bursts -system.physmem.perBankRdBursts::10 10558 # Per bank write bursts -system.physmem.perBankRdBursts::11 10261 # Per bank write bursts -system.physmem.perBankRdBursts::12 10296 # Per bank write bursts -system.physmem.perBankRdBursts::13 10620 # Per bank write bursts -system.physmem.perBankRdBursts::14 10515 # Per bank write bursts -system.physmem.perBankRdBursts::15 10632 # Per bank write bursts -system.physmem.perBankWrBursts::0 7162 # Per bank write bursts -system.physmem.perBankWrBursts::1 7273 # Per bank write bursts -system.physmem.perBankWrBursts::2 7295 # Per bank write bursts -system.physmem.perBankWrBursts::3 7000 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 14983 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10312 # Per bank write bursts +system.physmem.perBankRdBursts::1 10359 # Per bank write bursts +system.physmem.perBankRdBursts::2 10206 # Per bank write bursts +system.physmem.perBankRdBursts::3 10057 # Per bank write bursts +system.physmem.perBankRdBursts::4 10348 # Per bank write bursts +system.physmem.perBankRdBursts::5 10339 # Per bank write bursts +system.physmem.perBankRdBursts::6 9776 # Per bank write bursts +system.physmem.perBankRdBursts::7 10207 # Per bank write bursts +system.physmem.perBankRdBursts::8 10534 # Per bank write bursts +system.physmem.perBankRdBursts::9 10607 # Per bank write bursts +system.physmem.perBankRdBursts::10 10498 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10274 # Per bank write bursts +system.physmem.perBankRdBursts::13 10561 # Per bank write bursts +system.physmem.perBankRdBursts::14 10464 # Per bank write bursts +system.physmem.perBankRdBursts::15 10564 # Per bank write bursts +system.physmem.perBankWrBursts::0 7163 # Per bank write bursts +system.physmem.perBankWrBursts::1 7274 # Per bank write bursts +system.physmem.perBankWrBursts::2 7296 # Per bank write bursts +system.physmem.perBankWrBursts::3 7002 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7181 # Per bank write bursts +system.physmem.perBankWrBursts::5 7187 # Per bank write bursts system.physmem.perBankWrBursts::6 6833 # Per bank write bursts -system.physmem.perBankWrBursts::7 7084 # Per bank write bursts -system.physmem.perBankWrBursts::8 7224 # Per bank write bursts -system.physmem.perBankWrBursts::9 6994 # Per bank write bursts -system.physmem.perBankWrBursts::10 7113 # Per bank write bursts -system.physmem.perBankWrBursts::11 6992 # Per bank write bursts -system.physmem.perBankWrBursts::12 6991 # Per bank write bursts -system.physmem.perBankWrBursts::13 7295 # Per bank write bursts -system.physmem.perBankWrBursts::14 7307 # Per bank write bursts +system.physmem.perBankWrBursts::7 7099 # Per bank write bursts +system.physmem.perBankWrBursts::8 7225 # Per bank write bursts +system.physmem.perBankWrBursts::9 7000 # Per bank write bursts +system.physmem.perBankWrBursts::10 7115 # Per bank write bursts +system.physmem.perBankWrBursts::11 7034 # Per bank write bursts +system.physmem.perBankWrBursts::12 6992 # Per bank write bursts +system.physmem.perBankWrBursts::13 7299 # Per bank write bursts +system.physmem.perBankWrBursts::14 7308 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 59549007000 # Total gap between requests +system.physmem.totGap 59473838000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166369 # Read request sizes (log2) +system.physmem.readPktSize::6 165341 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114385 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1588 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114465 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1560 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,122 +193,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54768 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.014023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.067660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.383666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19491 35.59% 35.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11850 21.64% 57.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5663 10.34% 67.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3680 6.72% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2902 5.30% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2048 3.74% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1635 2.99% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1469 2.68% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6030 11.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54768 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.634839 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.413145 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7035 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.237051 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.297949 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.344141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19597 35.82% 35.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11811 21.59% 57.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5572 10.18% 67.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3684 6.73% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2893 5.29% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2049 3.74% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1621 2.96% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1502 2.75% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5985 10.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54714 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7041 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.479761 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.363256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7038 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7038 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7038 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.247940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.232365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.745442 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6264 89.00% 89.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 17 0.24% 89.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 601 8.54% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 122 1.73% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 23 0.33% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 6 0.09% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7041 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7041 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.252805 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.237164 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.745060 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6251 88.78% 88.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 16 0.23% 89.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 606 8.61% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 134 1.90% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 28 0.40% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.06% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7038 # Writes before turning the bus around for reads -system.physmem.totQLat 2001235750 # Total ticks spent queuing -system.physmem.totMemAccLat 5120560750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831820000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12029.26 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7041 # Writes before turning the bus around for reads +system.physmem.totQLat 1980163000 # Total ticks spent queuing +system.physmem.totMemAccLat 5080175500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826670000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11976.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30779.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 178.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 178.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30726.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 177.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 123.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 177.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 123.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.36 # Data bus utilization in percentage -system.physmem.busUtilRead 1.40 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.35 # Data bus utilization in percentage +system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing -system.physmem.readRowHits 144462 # Number of row buffer hits during reads -system.physmem.writeRowHits 81475 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes -system.physmem.avgGap 212103.86 # Average gap between requests -system.physmem.pageHitRate 80.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199614240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108916500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 641355000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368899920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3888958320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12587581890 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24683289750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42478615620 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.426150 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40913813750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1988220000 # Time in different power states +system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing +system.physmem.readRowHits 143867 # Number of row buffer hits during reads +system.physmem.writeRowHits 81182 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.92 # Row buffer hit rate for writes +system.physmem.avgGap 212553.83 # Average gap between requests +system.physmem.pageHitRate 80.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199175760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108677250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 636448800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 369204480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3884381280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12421725570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24786732000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42406345140 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.051581 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 41087166750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1985880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16639693750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16398707250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214137000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116840625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 655777200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371764080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3888958320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13157757450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24183135750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42588370425 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.269477 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40075806250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1988220000 # Time in different power states +system.physmem_1.actEnergy 214341120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116952000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 652938000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 372237120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3884381280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13062187260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24224923500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42527960280 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.096508 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40147172500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1985880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17478332750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17338598750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14666095 # Number of BP lookups -system.cpu.branchPred.condPredicted 9488989 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386100 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9897774 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6385513 # Number of BTB hits +system.cpu.branchPred.lookups 14666171 # Number of BP lookups +system.cpu.branchPred.condPredicted 9489023 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386095 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9897790 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6385525 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.514637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1708089 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84886 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.514654 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1708105 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84877 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20569916 # DTB read hits -system.cpu.dtb.read_misses 97322 # DTB read misses +system.cpu.dtb.read_hits 20569903 # DTB read hits +system.cpu.dtb.read_misses 97320 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20667238 # DTB read accesses -system.cpu.dtb.write_hits 14665322 # DTB write hits +system.cpu.dtb.read_accesses 20667223 # DTB read accesses +system.cpu.dtb.write_hits 14665328 # DTB write hits system.cpu.dtb.write_misses 9407 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674729 # DTB write accesses -system.cpu.dtb.data_hits 35235238 # DTB hits -system.cpu.dtb.data_misses 106729 # DTB misses +system.cpu.dtb.write_accesses 14674735 # DTB write accesses +system.cpu.dtb.data_hits 35235231 # DTB hits +system.cpu.dtb.data_misses 106727 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35341967 # DTB accesses -system.cpu.itb.fetch_hits 25606453 # ITB hits -system.cpu.itb.fetch_misses 5227 # ITB misses +system.cpu.dtb.data_accesses 35341958 # DTB accesses +system.cpu.itb.fetch_hits 25606544 # ITB hits +system.cpu.itb.fetch_misses 5228 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25611680 # ITB accesses +system.cpu.itb.fetch_accesses 25611772 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -322,65 +320,65 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 119098062 # number of cpu cycles simulated +system.cpu.numCycles 118947724 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1106110 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1106117 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.346683 # CPI: cycles per instruction -system.cpu.ipc 0.742565 # IPC: instructions per cycle -system.cpu.tickCycles 91473495 # Number of cycles that the object actually ticked -system.cpu.idleCycles 27624567 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.344983 # CPI: cycles per instruction +system.cpu.ipc 0.743504 # IPC: instructions per cycle +system.cpu.tickCycles 91473408 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27474316 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 200766 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.715334 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616231 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.683377 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616213 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 204862 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.973411 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.973324 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 687575500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.715334 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993827 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993827 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.683377 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993819 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993819 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 686 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3360 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3361 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176386 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176386 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20282965 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20282965 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333266 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333266 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34616231 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616231 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34616231 # number of overall hits -system.cpu.dcache.overall_hits::total 34616231 # number of overall hits +system.cpu.dcache.tags.tag_accesses 70176360 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70176360 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20282952 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20282952 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333261 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333261 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34616213 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616213 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34616213 # number of overall hits +system.cpu.dcache.overall_hits::total 34616213 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 89420 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 89420 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280111 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280111 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369531 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369531 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369531 # number of overall misses -system.cpu.dcache.overall_misses::total 369531 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4765724000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4765724000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21723340000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21723340000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26489064000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26489064000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26489064000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26489064000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 280116 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280116 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369536 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369536 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369536 # number of overall misses +system.cpu.dcache.overall_misses::total 369536 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4768019500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4768019500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21708920500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21708920500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26476940000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26476940000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26476940000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26476940000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372372 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372372 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34985762 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34985762 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34985762 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34985762 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34985749 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34985749 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34985749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34985749 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses @@ -389,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.010562 system.cpu.dcache.demand_miss_rate::total 0.010562 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.010562 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.010562 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53295.951689 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53295.951689 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77552.613071 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77552.613071 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71682.927819 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71682.927819 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71682.927819 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71682.927819 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53321.622679 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53321.622679 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77499.751889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77499.751889 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71649.149203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71649.149203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71649.149203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71649.149203 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,16 +403,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168453 # number of writebacks -system.cpu.dcache.writebacks::total 168453 # number of writebacks +system.cpu.dcache.writebacks::writebacks 168423 # number of writebacks +system.cpu.dcache.writebacks::total 168423 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28115 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 28115 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136554 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136554 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164669 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164669 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164669 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164669 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136559 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136559 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164674 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164674 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164674 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164674 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61305 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61305 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143557 # number of WriteReq MSHR misses @@ -423,14 +421,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204862 system.cpu.dcache.demand_mshr_misses::total 204862 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204862 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204862 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2678183500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2678183500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10981560500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10981560500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13659744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13659744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13659744000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13659744000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2680071500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2680071500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10970928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10970928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13650999500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13650999500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13650999500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13650999500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -439,69 +437,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # 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average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43717.013294 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43717.013294 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76422.104112 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76422.104112 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66635.098261 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66635.098261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66635.098261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66635.098261 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 152851 # number of replacements -system.cpu.icache.tags.tagsinuse 1932.369225 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25451553 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 154899 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 164.310635 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42309465500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1932.369225 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943540 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943540 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 152856 # number of replacements +system.cpu.icache.tags.tagsinuse 1932.301021 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25451639 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 154904 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 164.305886 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42254913500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1932.301021 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943506 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1041 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51367805 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51367805 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25451553 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25451553 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25451553 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25451553 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25451553 # number of overall hits -system.cpu.icache.overall_hits::total 25451553 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 154900 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 154900 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 154900 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 154900 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 154900 # number of overall misses -system.cpu.icache.overall_misses::total 154900 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2550963000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2550963000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2550963000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2550963000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2550963000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2550963000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25606453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25606453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25606453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25606453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25606453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25606453 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 51367992 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51367992 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25451639 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25451639 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25451639 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25451639 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25451639 # number of overall hits +system.cpu.icache.overall_hits::total 25451639 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 154905 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 154905 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 154905 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 154905 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 154905 # number of overall misses +system.cpu.icache.overall_misses::total 154905 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2479923000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2479923000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2479923000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2479923000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2479923000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2479923000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25606544 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25606544 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25606544 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25606544 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25606544 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25606544 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006049 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.006049 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.006049 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.006049 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.006049 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.006049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16468.450613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16468.450613 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16468.450613 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16468.450613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16468.450613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16468.450613 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16009.315387 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16009.315387 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16009.315387 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16009.315387 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16009.315387 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16009.315387 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,129 +508,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154900 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 154900 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 154900 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 154900 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 154900 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 154900 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2396064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2396064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2396064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2396064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2396064000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2396064000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 152856 # number of writebacks +system.cpu.icache.writebacks::total 152856 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154905 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 154905 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 154905 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 154905 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 154905 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 154905 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325019000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2325019000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2325019000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2325019000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2325019000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2325019000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006049 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006049 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15468.457069 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15468.457069 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15468.457069 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15468.457069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15468.457069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15468.457069 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15009.321842 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15009.321842 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15009.321842 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15009.321842 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15009.321842 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15009.321842 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132445 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30425.579826 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 402950 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164521 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.449231 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 133370 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30430.165732 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 403981 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 165480 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.441268 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 25961.899693 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2481.819774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1981.860360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.792294 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075739 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.060482 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.928515 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 938 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11872 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19020 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 126 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 6015111 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 6015111 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1089 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11867 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18864 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 125 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979919 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 6016150 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 6016150 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 168423 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168423 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 152856 # 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number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 154905 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 154905 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61304 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 61304 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 154900 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 154905 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204862 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 359762 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 154900 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 359767 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 154905 # 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mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.050478 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.050478 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773941 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.462445 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.050478 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773941 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.462445 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71241.748292 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71241.748292 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69204.949482 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69204.949482 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70689.670751 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70689.670751 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69204.949482 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69204.949482 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911708 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911708 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043627 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451863 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451863 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459581 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774102 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459581 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71159.898535 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71159.898535 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69449.985203 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69449.985203 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70675.968377 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70675.968377 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69449.985203 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71075.366998 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71008.932999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69449.985203 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71075.366998 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71008.932999 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 713379 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 353617 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 713389 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 353622 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4036 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4036 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 216203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 282838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 203224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 216208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 282888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 152856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143558 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 154900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 154905 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 61304 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462650 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462665 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1073140 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9913536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23892160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33805696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132445 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 845824 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004759 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.068819 # Request fanout histogram +system.cpu.toL2Bus.pkt_count::total 1073155 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19696640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23890240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43586880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133370 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 493137 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008184 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.090096 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 841799 99.52% 99.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4025 0.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 489101 99.18% 99.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4036 0.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 845824 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 525142500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 232349997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 493137 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 677973500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 232357497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307296493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307299487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 35487 # Transaction distribution -system.membus.trans_dist::Writeback 114385 # Transaction distribution -system.membus.trans_dist::CleanEvict 16125 # Transaction distribution -system.membus.trans_dist::ReadExReq 130882 # Transaction distribution -system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35487 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 463248 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17968256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17968256 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 34458 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114465 # Transaction distribution +system.membus.trans_dist::CleanEvict 14983 # Transaction distribution +system.membus.trans_dist::ReadExReq 130883 # Transaction distribution +system.membus.trans_dist::ReadExResp 130883 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34458 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460130 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17907584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17907584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 296879 # Request fanout histogram +system.membus.snoop_fanout::samples 294789 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 296879 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294789 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 296879 # Request fanout histogram -system.membus.reqLayer0.occupancy 824874000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294789 # Request fanout histogram +system.membus.reqLayer0.occupancy 822943500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 878418750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 872924250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index bea1e6fc8..b43434371 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022357 # Number of seconds simulated -sim_ticks 22356634500 # Number of ticks simulated -final_tick 22356634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022297 # Number of seconds simulated +sim_ticks 22296591500 # Number of ticks simulated +final_tick 22296591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 213363 # Simulator instruction rate (inst/s) -host_op_rate 213363 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59931818 # Simulator tick rate (ticks/s) -host_mem_usage 308400 # Number of bytes of host memory used -host_seconds 373.03 # Real time elapsed on the host +host_inst_rate 221726 # Simulator instruction rate (inst/s) +host_op_rate 221726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62113736 # Simulator tick rate (ticks/s) +host_mem_usage 308500 # Number of bytes of host memory used +host_seconds 358.96 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 471552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10150720 # Number of bytes read from this memory -system.physmem.bytes_read::total 10622272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 471552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 471552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7318272 # Number of bytes written to this memory -system.physmem.bytes_written::total 7318272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158605 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165973 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114348 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114348 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21092262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 454036139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 475128401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21092262 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21092262 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 327342293 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 327342293 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 327342293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21092262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 454036139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 802470694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165973 # Number of read requests accepted -system.physmem.writeReqs 114348 # Number of write requests accepted -system.physmem.readBursts 165973 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114348 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10621952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 7316672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10622272 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7318272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory +system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 409984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 409984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7322432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7322432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158644 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165050 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114413 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114413 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18387743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455370768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 473758511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18387743 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18387743 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 328410376 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 328410376 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 328410376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18387743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455370768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 802168888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165050 # Number of read requests accepted +system.physmem.writeReqs 114413 # Number of write requests accepted +system.physmem.readBursts 165050 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114413 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10562816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7320896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10563200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7322432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10420 # Per bank write bursts -system.physmem.perBankRdBursts::1 10451 # Per bank write bursts -system.physmem.perBankRdBursts::2 10285 # Per bank write bursts -system.physmem.perBankRdBursts::3 10056 # Per bank write bursts -system.physmem.perBankRdBursts::4 10402 # Per bank write bursts -system.physmem.perBankRdBursts::5 10375 # Per bank write bursts -system.physmem.perBankRdBursts::6 9822 # Per bank write bursts -system.physmem.perBankRdBursts::7 10280 # Per bank write bursts -system.physmem.perBankRdBursts::8 10559 # Per bank write bursts -system.physmem.perBankRdBursts::9 10640 # Per bank write bursts -system.physmem.perBankRdBursts::10 10517 # Per bank write bursts -system.physmem.perBankRdBursts::11 10228 # Per bank write bursts -system.physmem.perBankRdBursts::12 10263 # Per bank write bursts -system.physmem.perBankRdBursts::13 10582 # Per bank write bursts -system.physmem.perBankRdBursts::14 10475 # Per bank write bursts -system.physmem.perBankRdBursts::15 10613 # Per bank write bursts -system.physmem.perBankWrBursts::0 7161 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 14730 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10292 # Per bank write bursts +system.physmem.perBankRdBursts::1 10329 # Per bank write bursts +system.physmem.perBankRdBursts::2 10209 # Per bank write bursts +system.physmem.perBankRdBursts::3 10020 # Per bank write bursts +system.physmem.perBankRdBursts::4 10344 # Per bank write bursts +system.physmem.perBankRdBursts::5 10314 # Per bank write bursts +system.physmem.perBankRdBursts::6 9779 # Per bank write bursts +system.physmem.perBankRdBursts::7 10195 # Per bank write bursts +system.physmem.perBankRdBursts::8 10531 # Per bank write bursts +system.physmem.perBankRdBursts::9 10599 # Per bank write bursts +system.physmem.perBankRdBursts::10 10453 # Per bank write bursts +system.physmem.perBankRdBursts::11 10204 # Per bank write bursts +system.physmem.perBankRdBursts::12 10247 # Per bank write bursts +system.physmem.perBankRdBursts::13 10532 # Per bank write bursts +system.physmem.perBankRdBursts::14 10447 # Per bank write bursts +system.physmem.perBankRdBursts::15 10549 # Per bank write bursts +system.physmem.perBankWrBursts::0 7163 # Per bank write bursts system.physmem.perBankWrBursts::1 7267 # Per bank write bursts system.physmem.perBankWrBursts::2 7294 # Per bank write bursts -system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::3 7000 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7171 # Per bank write bursts -system.physmem.perBankWrBursts::6 6835 # Per bank write bursts -system.physmem.perBankWrBursts::7 7095 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts -system.physmem.perBankWrBursts::9 6995 # Per bank write bursts -system.physmem.perBankWrBursts::10 7101 # Per bank write bursts -system.physmem.perBankWrBursts::11 6988 # Per bank write bursts -system.physmem.perBankWrBursts::12 6991 # Per bank write bursts -system.physmem.perBankWrBursts::13 7292 # Per bank write bursts +system.physmem.perBankWrBursts::5 7180 # Per bank write bursts +system.physmem.perBankWrBursts::6 6836 # Per bank write bursts +system.physmem.perBankWrBursts::7 7102 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::9 7001 # Per bank write bursts +system.physmem.perBankWrBursts::10 7100 # Per bank write bursts +system.physmem.perBankWrBursts::11 7020 # Per bank write bursts +system.physmem.perBankWrBursts::12 6992 # Per bank write bursts +system.physmem.perBankWrBursts::13 7297 # Per bank write bursts system.physmem.perBankWrBursts::14 7307 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22356603500 # Total gap between requests +system.physmem.totGap 22296560500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165973 # Read request sizes (log2) +system.physmem.readPktSize::6 165050 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114348 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 52267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32162 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114413 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32167 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,125 +193,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.051408 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.164629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.365120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18284 34.97% 34.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10551 20.18% 55.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5984 11.44% 66.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2964 5.67% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2982 5.70% 77.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1592 3.04% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1956 3.74% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 963 1.84% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7012 13.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52288 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.745743 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 338.273336 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6986 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.858612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.924906 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.625607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18434 35.24% 35.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10645 20.35% 55.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5863 11.21% 66.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2906 5.56% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2975 5.69% 78.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1493 2.85% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2022 3.87% 84.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 988 1.89% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6984 13.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52310 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.610300 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 338.218951 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6987 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6989 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6989 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.357562 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.328073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.050353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6097 87.24% 87.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.43% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 474 6.78% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 201 2.88% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 97 1.39% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 49 0.70% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 24 0.34% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 8 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6989 # Writes before turning the bus around for reads -system.physmem.totQLat 5746744750 # Total ticks spent queuing -system.physmem.totMemAccLat 8858644750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 829840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34625.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6990 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.364664 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.334270 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.064891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6098 87.24% 87.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 26 0.37% 87.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 456 6.52% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 208 2.98% 97.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 103 1.47% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 57 0.82% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.30% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.14% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.11% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6990 # Writes before turning the bus around for reads +system.physmem.totQLat 5731685000 # Total ticks spent queuing +system.physmem.totMemAccLat 8826260000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 825220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34728.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53375.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 475.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 327.27 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 475.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 327.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53478.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 473.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 328.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 473.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 328.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 6.27 # Data bus utilization in percentage -system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes +system.physmem.busUtilRead 3.70 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.57 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing -system.physmem.readRowHits 145973 # Number of row buffer hits during reads -system.physmem.writeRowHits 82020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.73 # Row buffer hit rate for writes -system.physmem.avgGap 79753.58 # Average gap between requests -system.physmem.pageHitRate 81.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190882440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 104152125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 640161600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368899920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1460075760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6647542920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7581572250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16993287015 # Total energy per rank (pJ) -system.physmem_0.averagePower 760.170138 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12528806000 # Time in different power states -system.physmem_0.memoryStateTime::REF 746460000 # Time in different power states +system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing +system.physmem.readRowHits 145441 # Number of row buffer hits during reads +system.physmem.writeRowHits 81669 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.38 # Row buffer hit rate for writes +system.physmem.avgGap 79783.59 # Average gap between requests +system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 190375920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 103875750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 635356800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 369036000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6553881090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7626357750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16934890590 # Total energy per rank (pJ) +system.physmem_0.averagePower 759.674656 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12601715000 # Time in different power states +system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9079331500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8946212500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204271200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111457500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654100200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371699280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1460075760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6857633520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7397282250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 17056519710 # Total energy per rank (pJ) -system.physmem_1.averagePower 762.998761 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12224344750 # Time in different power states -system.physmem_1.memoryStateTime::REF 746460000 # Time in different power states +system.physmem_1.actEnergy 204815520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111754500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 651565200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371893680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6747677955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7456388250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 17000102385 # Total energy per rank (pJ) +system.physmem_1.averagePower 762.598381 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12320846000 # Time in different power states +system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9383970250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9227273000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16500558 # Number of BP lookups -system.cpu.branchPred.condPredicted 10689411 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 329507 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9043813 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7288978 # Number of BTB hits +system.cpu.branchPred.lookups 16493971 # Number of BP lookups +system.cpu.branchPred.condPredicted 10685365 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 327092 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8977635 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7282355 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.596293 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1974529 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2931 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.116630 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1973286 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2952 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22520885 # DTB read hits -system.cpu.dtb.read_misses 225850 # DTB read misses -system.cpu.dtb.read_acv 12 # DTB read access violations -system.cpu.dtb.read_accesses 22746735 # DTB read accesses -system.cpu.dtb.write_hits 15825785 # DTB write hits -system.cpu.dtb.write_misses 44675 # DTB write misses -system.cpu.dtb.write_acv 5 # DTB write access violations -system.cpu.dtb.write_accesses 15870460 # DTB write accesses -system.cpu.dtb.data_hits 38346670 # DTB hits -system.cpu.dtb.data_misses 270525 # DTB misses -system.cpu.dtb.data_acv 17 # DTB access violations -system.cpu.dtb.data_accesses 38617195 # DTB accesses -system.cpu.itb.fetch_hits 13761847 # ITB hits -system.cpu.itb.fetch_misses 29330 # ITB misses +system.cpu.dtb.read_hits 22518673 # DTB read hits +system.cpu.dtb.read_misses 225961 # DTB read misses +system.cpu.dtb.read_acv 15 # DTB read access violations +system.cpu.dtb.read_accesses 22744634 # DTB read accesses +system.cpu.dtb.write_hits 15824450 # DTB write hits +system.cpu.dtb.write_misses 44763 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15869213 # DTB write accesses +system.cpu.dtb.data_hits 38343123 # DTB hits +system.cpu.dtb.data_misses 270724 # DTB misses +system.cpu.dtb.data_acv 19 # DTB access violations +system.cpu.dtb.data_accesses 38613847 # DTB accesses +system.cpu.itb.fetch_hits 13750650 # ITB hits +system.cpu.itb.fetch_misses 29320 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13791177 # ITB accesses +system.cpu.itb.fetch_accesses 13779970 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -325,141 +324,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44713274 # number of cpu cycles simulated +system.cpu.numCycles 44593188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15584768 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105191572 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16500558 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9263507 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27593237 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 896542 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 162 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4764 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 325871 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13761847 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 191924 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15564341 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105145283 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16493971 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9255641 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27572822 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 891924 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 262 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 325760 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13750650 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 190232 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43957183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.393046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.127676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43914039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.394343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.128103 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24416716 55.55% 55.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1522401 3.46% 59.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1379227 3.14% 62.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1505485 3.42% 65.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4199085 9.55% 75.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1828470 4.16% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 669319 1.52% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1052182 2.39% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7384298 16.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24384273 55.53% 55.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1520929 3.46% 58.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1376099 3.13% 62.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1504413 3.43% 65.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4198532 9.56% 75.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1828676 4.16% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 668520 1.52% 80.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050487 2.39% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7382110 16.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43957183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369030 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.352580 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14931500 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9767964 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18310970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 595597 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 351152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3708003 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98860 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103215952 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 311866 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 351152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15279451 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4431592 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 96231 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18542963 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5255794 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102192828 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5698 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 95463 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 341437 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4753642 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61435412 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123253139 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122935807 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 317331 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43914039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369876 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.357878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14911775 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9756593 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18301996 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 594945 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 348730 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3706760 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98994 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103174683 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312811 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 348730 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15258388 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4434115 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 96788 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18534618 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5241400 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102158813 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5649 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94745 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 345515 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4735615 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61411273 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123213365 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122896091 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 317273 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8888531 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5692 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5745 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2361848 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23156457 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16385404 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1258348 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 502815 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90834629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5552 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88691609 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70456 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11248424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4497706 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 969 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43957183 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.017682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.245665 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8864392 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5712 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5765 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2362727 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23149705 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16384887 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1256801 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 494099 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90814957 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5561 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88678954 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 70817 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11228761 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4483589 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 978 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43914039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.019376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.246135 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17476881 39.76% 39.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5730177 13.04% 52.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5107740 11.62% 64.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4380373 9.97% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4328154 9.85% 84.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2635103 5.99% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1947598 4.43% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1378142 3.14% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 973015 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17441953 39.72% 39.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5726957 13.04% 52.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5104887 11.62% 64.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4381256 9.98% 74.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4320313 9.84% 84.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2639459 6.01% 90.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1947949 4.44% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1377906 3.14% 97.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 973359 2.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43957183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43914039 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243362 9.64% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1165216 46.16% 55.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1115524 44.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 242855 9.63% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1163309 46.14% 55.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1115010 44.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49430492 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43978 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49423838 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43986 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121147 0.14% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120628 0.14% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39084 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121174 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120676 0.14% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39089 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -481,84 +480,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22917985 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16018139 18.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22912706 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16017331 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88691609 # Type of FU issued -system.cpu.iq.rate 1.983563 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2524102 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223325364 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101690449 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86898361 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 609595 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 418176 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299341 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90910760 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 304951 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1670602 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88678954 # Type of FU issued +system.cpu.iq.rate 1.988621 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2521174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028430 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223254204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101651163 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86893480 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 609734 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 418232 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299390 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90895107 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305021 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1671418 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2879819 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5660 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20258 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1772027 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2873067 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5610 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20361 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1771510 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3047 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 205936 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3045 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 204833 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 351152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1286887 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2706445 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100341607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125884 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23156457 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16385404 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5552 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3769 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2705021 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20258 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 121859 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 151192 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 273051 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87981340 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22747403 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 710269 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 348730 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1277507 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2721681 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100319642 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 124919 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23149705 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16384887 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5561 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3725 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2720217 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20361 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 118662 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 150973 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 269635 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87973235 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22745315 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 705719 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9501426 # number of nop insts executed -system.cpu.iew.exec_refs 38618193 # number of memory reference insts executed -system.cpu.iew.exec_branches 15127263 # Number of branches executed -system.cpu.iew.exec_stores 15870790 # Number of stores executed -system.cpu.iew.exec_rate 1.967678 # Inst execution rate -system.cpu.iew.wb_sent 87600358 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87197702 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33849535 # num instructions producing a value -system.cpu.iew.wb_consumers 44277575 # num instructions consuming a value +system.cpu.iew.exec_nop 9499124 # number of nop insts executed +system.cpu.iew.exec_refs 38614853 # number of memory reference insts executed +system.cpu.iew.exec_branches 15126858 # Number of branches executed +system.cpu.iew.exec_stores 15869538 # Number of stores executed +system.cpu.iew.exec_rate 1.972795 # Inst execution rate +system.cpu.iew.wb_sent 87594856 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87192870 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33852684 # num instructions producing a value +system.cpu.iew.wb_consumers 44279326 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.950152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764485 # average fanout of values written-back +system.cpu.iew.wb_rate 1.955296 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764526 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8791000 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8765402 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 232388 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42666920 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.070472 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.884283 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 229860 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42628268 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.072350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.885151 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21190783 49.67% 49.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6285871 14.73% 64.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2905995 6.81% 71.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1744112 4.09% 75.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1680276 3.94% 79.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1128586 2.65% 81.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1203447 2.82% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 797041 1.87% 86.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5730809 13.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21157300 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6282680 14.74% 64.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2903206 6.81% 71.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1743375 4.09% 75.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1680050 3.94% 79.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1128930 2.65% 81.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1204133 2.82% 84.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 796945 1.87% 86.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5731649 13.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42666920 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42628268 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -604,333 +603,339 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5730809 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132750441 # The number of ROB reads -system.cpu.rob.rob_writes 195556891 # The number of ROB writes -system.cpu.timesIdled 46372 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 756091 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5731649 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 132685351 # The number of ROB reads +system.cpu.rob.rob_writes 195501271 # The number of ROB writes +system.cpu.timesIdled 46319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 679149 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.561783 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561783 # CPI: Total CPI of All Threads -system.cpu.ipc 1.780048 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.780048 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116466074 # number of integer regfile reads -system.cpu.int_regfile_writes 57713698 # number of integer regfile writes -system.cpu.fp_regfile_reads 255059 # number of floating regfile reads -system.cpu.fp_regfile_writes 240376 # number of floating regfile writes -system.cpu.misc_regfile_reads 38265 # number of misc regfile reads +system.cpu.cpi 0.560274 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.560274 # CPI: Total CPI of All Threads +system.cpu.ipc 1.784841 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.784841 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116453986 # number of integer regfile reads +system.cpu.int_regfile_writes 57709287 # number of integer regfile writes +system.cpu.fp_regfile_reads 255067 # number of floating regfile reads +system.cpu.fp_regfile_writes 240450 # number of floating regfile writes +system.cpu.misc_regfile_reads 38270 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 201297 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.745765 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33997888 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205393 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.526031 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 229746500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.745765 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993834 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993834 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201399 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.676822 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33995451 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205495 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.432011 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 229821500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.676822 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993818 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993818 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2788 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1232 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2778 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70843209 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70843209 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20436554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20436554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561278 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561278 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33997832 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33997832 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33997832 # number of overall hits -system.cpu.dcache.overall_hits::total 33997832 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268921 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268921 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052099 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052099 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321020 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321020 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321020 # number of overall misses -system.cpu.dcache.overall_misses::total 1321020 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17355062000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17355062000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89131929604 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89131929604 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106486991604 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106486991604 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106486991604 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106486991604 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20705475 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20705475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70838999 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70838999 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20434147 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20434147 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561246 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561246 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 58 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 58 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33995393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33995393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33995393 # number of overall hits +system.cpu.dcache.overall_hits::total 33995393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269170 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052131 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052131 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1321301 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321301 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321301 # number of overall misses +system.cpu.dcache.overall_misses::total 1321301 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17282869000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17282869000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89120990413 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89120990413 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106403859413 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106403859413 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106403859413 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106403859413 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20703317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20703317 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35318852 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35318852 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35318852 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35318852 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012988 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012988 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071996 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071996 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037403 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037403 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037403 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037403 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64535.912034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64535.912034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84718.196295 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84718.196295 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80609.674043 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80609.674043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80609.674043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80609.674043 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6869550 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35316694 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35316694 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35316694 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35316694 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071998 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071998 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037413 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037413 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037413 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037413 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64208.006093 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64208.006093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84705.222461 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84705.222461 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80529.613928 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80529.613928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80529.613928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80529.613928 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6870751 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 88969 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 89149 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.212849 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.070421 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168788 # number of writebacks -system.cpu.dcache.writebacks::total 168788 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206925 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 206925 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908702 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908702 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115627 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115627 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115627 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115627 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61996 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61996 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143397 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143397 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205393 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205393 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205393 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205393 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3212836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3212836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14233206202 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14233206202 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17446042702 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17446042702 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17446042702 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17446042702 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005815 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005815 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005815 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005815 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51823.286986 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51823.286986 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99257.349889 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99257.349889 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84939.811493 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84939.811493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84939.811493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84939.811493 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168802 # number of writebacks +system.cpu.dcache.writebacks::total 168802 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207068 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207068 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908738 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 908738 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115806 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115806 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115806 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115806 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143393 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143393 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205495 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205495 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205495 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205495 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3198491500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3198491500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14240616218 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14240616218 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17439107718 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17439107718 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17439107718 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17439107718 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005819 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005819 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51503.840456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51503.840456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99311.794983 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99311.794983 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84863.902859 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84863.902859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84863.902859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84863.902859 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 91498 # number of replacements -system.cpu.icache.tags.tagsinuse 1915.935564 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13655300 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93546 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 145.974173 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18815415500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1915.935564 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.935515 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.935515 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 91476 # number of replacements +system.cpu.icache.tags.tagsinuse 1915.700741 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13644579 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93524 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 145.893878 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18771424500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1915.700741 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935401 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935401 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1476 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1477 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 380 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27617236 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27617236 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13655300 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13655300 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13655300 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13655300 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13655300 # number of overall hits -system.cpu.icache.overall_hits::total 13655300 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106545 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106545 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106545 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106545 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106545 # number of overall misses -system.cpu.icache.overall_misses::total 106545 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2015171999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2015171999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2015171999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2015171999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2015171999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2015171999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13761845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13761845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13761845 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13761845 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13761845 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13761845 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007742 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007742 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007742 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007742 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007742 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007742 # 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number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13644579 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13644579 # number of overall hits +system.cpu.icache.overall_hits::total 13644579 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106069 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106069 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106069 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106069 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106069 # number of overall misses +system.cpu.icache.overall_misses::total 106069 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1942429499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1942429499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1942429499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1942429499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1942429499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1942429499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13750648 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13750648 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13750648 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13750648 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13750648 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13750648 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007714 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007714 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007714 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1645041500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1645041500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1645041500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006798 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006798 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006798 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006798 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006798 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006798 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17585.187125 # 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Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 133079 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30599.466713 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 282960 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 165171 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.713134 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26451.406117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2221.195572 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1924.780395 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.807233 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.067786 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 529244000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 16629791500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17159035500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 168802 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168802 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 91476 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 91476 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143394 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143394 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 93525 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 93525 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62101 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 62101 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 93525 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205495 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 299020 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 93525 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205495 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 299020 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912060 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912060 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.068506 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.068506 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.448624 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.448624 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.068506 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.772009 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.551973 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.068506 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.772009 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.551973 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106197.631209 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106197.631209 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82604.026846 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82604.026846 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98379.055994 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98379.055994 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82604.026846 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104824.585235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 103962.020830 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82604.026846 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104824.585235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 103962.020830 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -939,122 +944,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114348 # number of writebacks -system.cpu.l2cache.writebacks::total 114348 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2056 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 2056 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130783 # 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number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12573700500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12573700500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 525566500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 525566500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2477938500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2477938500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 525566500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15051639000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15577205500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 525566500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15051639000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15577205500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 114413 # number of writebacks +system.cpu.l2cache.writebacks::total 114413 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 112 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 112 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130784 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130784 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6407 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6407 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27860 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27860 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6407 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158644 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165051 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6407 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158644 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165051 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12581111000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12581111000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 465184000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 465184000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2462240500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2462240500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 465184000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15043351500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15508535500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 465184000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15043351500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15508535500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912022 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912022 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078773 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448785 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448785 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.555208 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772203 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.555208 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96141.704197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96141.704197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71321.278328 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71321.278328 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89063.996118 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89063.996118 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71321.278328 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71321.278328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.068506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448624 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448624 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772009 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.551973 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772009 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.551973 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96197.631209 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96197.631209 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72605.587639 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72605.587639 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88379.055994 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88379.055994 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72605.587639 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94824.585235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93962.081417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72605.587639 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94824.585235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93962.081417 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 591735 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 292795 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 591895 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 292875 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4047 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4047 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 155540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 283136 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 141723 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 93547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61994 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 278591 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612083 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 890674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5986944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23947584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29934528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132064 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 723799 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005561 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.074364 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 155625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283215 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 91476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 93525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 278525 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612389 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 890914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11840000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23955008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35795008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133079 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 432099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009366 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.096323 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 719774 99.44% 99.44% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4025 0.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 428052 99.06% 99.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4047 0.94% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 723799 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 464655500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 140327982 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432099 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 556225500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 140299972 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308097983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308258967 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 35190 # Transaction distribution -system.membus.trans_dist::Writeback 114348 # Transaction distribution -system.membus.trans_dist::CleanEvict 15746 # Transaction distribution -system.membus.trans_dist::ReadExReq 130783 # Transaction distribution -system.membus.trans_dist::ReadExResp 130783 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35190 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462040 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 34266 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114413 # Transaction distribution +system.membus.trans_dist::CleanEvict 14730 # Transaction distribution +system.membus.trans_dist::ReadExReq 130784 # Transaction distribution +system.membus.trans_dist::ReadExResp 130784 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34266 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 459243 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 459243 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17885632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17885632 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 296067 # Request fanout histogram +system.membus.snoop_fanout::samples 294193 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 296067 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294193 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 296067 # Request fanout histogram -system.membus.reqLayer0.occupancy 778875000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294193 # Request fanout histogram +system.membus.reqLayer0.occupancy 777045500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 857731250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 852834000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 67f744153..c1732fe78 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.056991 # Number of seconds simulated -sim_ticks 56991022500 # Number of ticks simulated -final_tick 56991022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056961 # Number of seconds simulated +sim_ticks 56960656500 # Number of ticks simulated +final_tick 56960656500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186679 # Simulator instruction rate (inst/s) -host_op_rate 238735 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 150024942 # Simulator tick rate (ticks/s) -host_mem_usage 325676 # Number of bytes of host memory used -host_seconds 379.88 # Real time elapsed on the host +host_inst_rate 199606 # Simulator instruction rate (inst/s) +host_op_rate 255266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 160327771 # Simulator tick rate (ticks/s) +host_mem_usage 325784 # Number of bytes of host memory used +host_seconds 355.28 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 318720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923904 # Number of bytes read from this memory -system.physmem.bytes_read::total 8242624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 318720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 318720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5514048 # Number of bytes written to this memory -system.physmem.bytes_written::total 5514048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123811 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86157 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86157 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5592460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 139037758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 144630218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5592460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5592460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96752923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96752923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96752923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5592460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 139037758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 241383141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128791 # Number of read requests accepted -system.physmem.writeReqs 86157 # Number of write requests accepted -system.physmem.readBursts 128791 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 86157 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8242176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5512640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8242624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5514048 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 285184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924608 # Number of bytes read from this memory +system.physmem.bytes_read::total 8209792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 285184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 285184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5517504 # Number of bytes written to this memory +system.physmem.bytes_written::total 5517504 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123822 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128278 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86211 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86211 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5006684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139124239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144130923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5006684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5006684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96865176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96865176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96865176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5006684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139124239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 240996099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128278 # Number of read requests accepted +system.physmem.writeReqs 86211 # Number of write requests accepted +system.physmem.readBursts 128278 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86211 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8209408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 5515712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8209792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8144 # Per bank write bursts -system.physmem.perBankRdBursts::1 8370 # Per bank write bursts -system.physmem.perBankRdBursts::2 8248 # Per bank write bursts -system.physmem.perBankRdBursts::3 8170 # Per bank write bursts -system.physmem.perBankRdBursts::4 8315 # Per bank write bursts -system.physmem.perBankRdBursts::5 8436 # Per bank write bursts -system.physmem.perBankRdBursts::6 8084 # Per bank write bursts -system.physmem.perBankRdBursts::7 7955 # Per bank write bursts -system.physmem.perBankRdBursts::8 8060 # Per bank write bursts -system.physmem.perBankRdBursts::9 7629 # Per bank write bursts -system.physmem.perBankRdBursts::10 7815 # Per bank write bursts -system.physmem.perBankRdBursts::11 7829 # Per bank write bursts -system.physmem.perBankRdBursts::12 7881 # Per bank write bursts -system.physmem.perBankRdBursts::13 7878 # Per bank write bursts -system.physmem.perBankRdBursts::14 7975 # Per bank write bursts -system.physmem.perBankRdBursts::15 7995 # Per bank write bursts -system.physmem.perBankWrBursts::0 5393 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6908 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8061 # Per bank write bursts +system.physmem.perBankRdBursts::1 8314 # Per bank write bursts +system.physmem.perBankRdBursts::2 8233 # Per bank write bursts +system.physmem.perBankRdBursts::3 8140 # Per bank write bursts +system.physmem.perBankRdBursts::4 8284 # Per bank write bursts +system.physmem.perBankRdBursts::5 8402 # Per bank write bursts +system.physmem.perBankRdBursts::6 8056 # Per bank write bursts +system.physmem.perBankRdBursts::7 7915 # Per bank write bursts +system.physmem.perBankRdBursts::8 8035 # Per bank write bursts +system.physmem.perBankRdBursts::9 7586 # Per bank write bursts +system.physmem.perBankRdBursts::10 7763 # Per bank write bursts +system.physmem.perBankRdBursts::11 7815 # Per bank write bursts +system.physmem.perBankRdBursts::12 7871 # Per bank write bursts +system.physmem.perBankRdBursts::13 7867 # Per bank write bursts +system.physmem.perBankRdBursts::14 7968 # Per bank write bursts +system.physmem.perBankRdBursts::15 7962 # Per bank write bursts +system.physmem.perBankWrBursts::0 5394 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts -system.physmem.perBankWrBursts::2 5464 # Per bank write bursts -system.physmem.perBankWrBursts::3 5326 # Per bank write bursts -system.physmem.perBankWrBursts::4 5352 # Per bank write bursts -system.physmem.perBankWrBursts::5 5547 # Per bank write bursts -system.physmem.perBankWrBursts::6 5252 # Per bank write bursts -system.physmem.perBankWrBursts::7 5180 # Per bank write bursts +system.physmem.perBankWrBursts::2 5465 # Per bank write bursts +system.physmem.perBankWrBursts::3 5335 # Per bank write bursts +system.physmem.perBankWrBursts::4 5367 # Per bank write bursts +system.physmem.perBankWrBursts::5 5560 # Per bank write bursts +system.physmem.perBankWrBursts::6 5259 # Per bank write bursts +system.physmem.perBankWrBursts::7 5181 # Per bank write bursts system.physmem.perBankWrBursts::8 5155 # Per bank write bursts system.physmem.perBankWrBursts::9 5101 # Per bank write bursts system.physmem.perBankWrBursts::10 5292 # Per bank write bursts @@ -79,27 +79,27 @@ system.physmem.perBankWrBursts::11 5270 # Pe system.physmem.perBankWrBursts::12 5531 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts system.physmem.perBankWrBursts::14 5703 # Per bank write bursts -system.physmem.perBankWrBursts::15 5431 # Per bank write bursts +system.physmem.perBankWrBursts::15 5432 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56990990500 # Total gap between requests +system.physmem.totGap 56960630500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128791 # Read request sizes (log2) +system.physmem.readPktSize::6 128278 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 86157 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86211 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116041 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5463 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,98 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38662 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 355.683203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.343519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.125731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12148 31.42% 31.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8177 21.15% 52.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4090 10.58% 63.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2852 7.38% 70.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2693 6.97% 77.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1623 4.20% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1296 3.35% 85.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1161 3.00% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4622 11.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38662 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 38843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.305769 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 214.370646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.820424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12327 31.74% 31.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8308 21.39% 53.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4009 10.32% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2908 7.49% 70.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2579 6.64% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1645 4.23% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1295 3.33% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1183 3.05% 88.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4589 11.81% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38843 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.322124 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.056892 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.231438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 352.038332 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.273380 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.256688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.768255 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4654 87.93% 87.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 4 0.08% 88.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 500 9.45% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 109 2.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 18 0.34% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.282449 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.265601 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.771117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4623 87.34% 87.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.11% 87.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 534 10.09% 97.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 111 2.10% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 13 0.25% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads -system.physmem.totQLat 1683428000 # Total ticks spent queuing -system.physmem.totMemAccLat 4098128000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13071.72 # Average queueing delay per DRAM burst +system.physmem.totQLat 1678352000 # Total ticks spent queuing +system.physmem.totMemAccLat 4083452000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 641360000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13084.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31821.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 144.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 144.63 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31834.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.12 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 96.83 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.13 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.89 # Data bus utilization in percentage +system.physmem.busUtil 1.88 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing -system.physmem.readRowHits 112096 # Number of row buffer hits during reads -system.physmem.writeRowHits 64153 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.46 # Row buffer hit rate for writes -system.physmem.avgGap 265138.50 # Average gap between requests -system.physmem.pageHitRate 82.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 151963560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82916625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512397600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 278957520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11726025750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 23906742000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40381153695 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.591931 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39643767750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1902940000 # Time in different power states +system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing +system.physmem.readRowHits 111810 # Number of row buffer hits during reads +system.physmem.writeRowHits 63793 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes +system.physmem.avgGap 265564.34 # Average gap between requests +system.physmem.pageHitRate 81.87 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 153158040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 83568375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 509862600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11565367830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24028947750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40340244195 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.261877 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39847901500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1901900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15441187500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15206891000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140313600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76560000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 491751000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 140419440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76617750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 490214400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11059172775 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24491665500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40260752475 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.479908 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40617302250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1902940000 # Time in different power states +system.physmem_1.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10938128715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24579157500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40223793165 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.217322 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40763292250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1901900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14467595250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14291603250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14800541 # Number of BP lookups -system.cpu.branchPred.condPredicted 9905717 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 381681 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9438549 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6732145 # Number of BTB hits +system.cpu.branchPred.lookups 14800638 # Number of BP lookups +system.cpu.branchPred.condPredicted 9905777 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 381686 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9438449 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6732187 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.326059 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1714124 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 71.327259 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1714133 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,67 +404,67 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 113982045 # number of cpu cycles simulated +system.cpu.numCycles 113921313 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1144890 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1144928 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.607302 # CPI: cycles per instruction -system.cpu.ipc 0.622161 # IPC: instructions per cycle -system.cpu.tickCycles 95587829 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18394216 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156435 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.142814 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42624094 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160531 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.519395 # Average number of references to valid blocks. +system.cpu.cpi 1.606446 # CPI: cycles per instruction +system.cpu.ipc 0.622492 # IPC: instructions per cycle +system.cpu.tickCycles 95595424 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18325889 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156436 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.127430 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42624259 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.518769 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.142814 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127430 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1110 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2947 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86016729 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86016729 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22866654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22866654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642187 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642187 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83415 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83415 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86016734 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86016734 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22866824 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22866824 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83418 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83418 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42508841 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42508841 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42592256 # number of overall hits -system.cpu.dcache.overall_hits::total 42592256 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51701 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51701 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207714 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207714 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259415 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259415 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 304005 # number of overall misses -system.cpu.dcache.overall_misses::total 304005 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1492164500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1492164500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16804934500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16804934500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18297099000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18297099000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18297099000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18297099000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22918355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22918355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42509003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42509003 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42592421 # number of overall hits +system.cpu.dcache.overall_hits::total 42592421 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44587 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44587 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303842 # number of overall misses +system.cpu.dcache.overall_misses::total 303842 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489955500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1489955500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16807631000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16807631000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18297586500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18297586500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18297586500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18297586500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) @@ -473,28 +473,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42768256 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42768256 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42896261 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42896261 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002256 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002256 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348346 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348346 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28861.424344 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28861.424344 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80904.197599 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80904.197599 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70532.155041 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70532.155041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60186.835743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60186.835743 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348322 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.348322 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28912.648206 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28912.648206 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80914.063027 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80914.063027 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70577.564560 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70577.564560 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60220.728207 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60220.728207 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,36 +503,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128400 # number of writebacks -system.cpu.dcache.writebacks::total 128400 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100686 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100686 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122869 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122869 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122869 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122869 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29518 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29518 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 128377 # number of writebacks +system.cpu.dcache.writebacks::total 128377 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22014 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22014 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100694 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100694 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122708 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122708 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122708 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122708 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29519 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29519 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136546 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136546 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160531 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160531 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 578376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8484284000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8484284000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1716349500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1716349500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9062660000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9062660000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779009500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10779009500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 136547 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136547 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 577658500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 577658500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488450500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488450500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1712416500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1712416500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9066109000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9066109000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10778525500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10778525500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -543,70 +543,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19594.010434 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19594.010434 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79271.629854 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79271.629854 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71559.287054 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71559.287054 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66370.746855 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66370.746855 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67145.968691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67145.968691 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19569.040279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19569.040279 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79310.558919 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79310.558919 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71395.309568 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71395.309568 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66395.519491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66395.519491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67142.535445 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67142.535445 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42866 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.547846 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24941084 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 555.381758 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42868 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.481887 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24941232 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44910 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 555.360321 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.547846 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904564 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904564 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.481887 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904532 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904532 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50016894 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50016894 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24941084 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24941084 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24941084 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24941084 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24941084 # number of overall hits -system.cpu.icache.overall_hits::total 24941084 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44909 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44909 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44909 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44909 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44909 # number of overall misses -system.cpu.icache.overall_misses::total 44909 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 929470000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 929470000 # 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number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 896725000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 896725000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 896725000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 896725000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 896725000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 896725000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24986143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24986143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24986143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24986143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24986143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24986143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20696.742301 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20696.742301 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20696.742301 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20696.742301 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19966.711941 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19966.711941 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19966.711941 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19966.711941 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,129 +615,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44909 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44909 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44909 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44909 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44909 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44909 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 884562000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 884562000 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95654 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29860.905704 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 161645 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126772 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.275084 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 96386 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.911283 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1809 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12704 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15880 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 604 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3409216 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3409216 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 128400 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128400 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1851 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12724 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15788 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 593 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3410031 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3410031 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 128377 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 128377 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 39288 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 39288 # 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miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403716 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403716 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111136 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.627273 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111136 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.627273 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80896.808635 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80896.808635 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79002.304147 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81839.440142 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,132 +752,133 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 86157 # number of writebacks -system.cpu.l2cache.writebacks::total 86157 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 10 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 10 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 65 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 65 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits +system.cpu.l2cache.writebacks::writebacks 86211 # number of writebacks +system.cpu.l2cache.writebacks::total 86211 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1374 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1374 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102276 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102276 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4981 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4981 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21535 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21535 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4981 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123811 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128792 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123811 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128792 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7251042000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7251042000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 343845500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 343845500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1655136500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1655136500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 343845500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8906178500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9250024000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 343845500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8906178500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9250024000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102277 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102277 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4457 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4457 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21545 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21545 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4457 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123822 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128279 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4457 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123822 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128279 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7255203500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7255203500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310493500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310493500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649955000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649955000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310493500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8905158500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9215652000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310493500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8905158500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9215652000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110913 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402501 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402501 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.626908 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.626908 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70896.808635 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70896.808635 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69031.419394 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69031.419394 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76857.975389 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76857.975389 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955610 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955610 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099241 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.624402 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.624402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70936.803974 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70936.803974 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69664.236033 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69664.236033 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76581.805523 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76581.805523 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 404741 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 199337 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 404747 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 199340 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3362 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 98411 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 214557 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 72584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 39288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34000 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 44909 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129104 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 602366 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21365696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 95654 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 500395 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.038076 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.191682 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 44911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53504 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473266 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 602375 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5388672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 23878848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 96386 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 301829 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037243 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.189864 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 481371 96.20% 96.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18995 3.80% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 290617 96.29% 96.29% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11183 3.71% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 500395 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 330770500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 67369485 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 301829 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 373618500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 67384461 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240829933 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240832431 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 26515 # Transaction distribution -system.membus.trans_dist::Writeback 86157 # Transaction distribution -system.membus.trans_dist::CleanEvict 7510 # Transaction distribution -system.membus.trans_dist::ReadExReq 102276 # Transaction distribution -system.membus.trans_dist::ReadExResp 102276 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26515 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 351249 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 351249 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13756672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13756672 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 26001 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86211 # Transaction distribution +system.membus.trans_dist::CleanEvict 6908 # Transaction distribution +system.membus.trans_dist::ReadExReq 102277 # Transaction distribution +system.membus.trans_dist::ReadExResp 102277 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26001 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349675 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 349675 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13727296 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 222458 # Request fanout histogram +system.membus.snoop_fanout::samples 221397 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222458 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 221397 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222458 # Request fanout histogram -system.membus.reqLayer0.occupancy 591531500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 221397 # Request fanout histogram +system.membus.reqLayer0.occupancy 590585500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 679686000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 676907000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 4fc60452d..6b580b547 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033346 # Number of seconds simulated -sim_ticks 33346420000 # Number of ticks simulated -final_tick 33346420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033788 # Number of seconds simulated +sim_ticks 33787619000 # Number of ticks simulated +final_tick 33787619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116263 # Simulator instruction rate (inst/s) -host_op_rate 148687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54676178 # Simulator tick rate (ticks/s) -host_mem_usage 326572 # Number of bytes of host memory used -host_seconds 609.89 # Real time elapsed on the host +host_inst_rate 117892 # Simulator instruction rate (inst/s) +host_op_rate 150770 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56175899 # Simulator tick rate (ticks/s) +host_mem_usage 326928 # Number of bytes of host memory used +host_seconds 601.46 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 581760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2519040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6191552 # Number of bytes read from this memory -system.physmem.bytes_read::total 9292352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 581760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 581760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6257152 # Number of bytes written to this memory -system.physmem.bytes_written::total 6257152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96743 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145193 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97768 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97768 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17445951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75541542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 185673665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 278661158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17445951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17445951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 187640892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 187640892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 187640892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17445951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75541542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 185673665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 466302050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145193 # Number of read requests accepted -system.physmem.writeReqs 97768 # Number of write requests accepted -system.physmem.readBursts 145193 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97768 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9285376 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 6255360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9292352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6257152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9137 # Per bank write bursts -system.physmem.perBankRdBursts::1 9395 # Per bank write bursts -system.physmem.perBankRdBursts::2 9161 # Per bank write bursts -system.physmem.perBankRdBursts::3 9548 # Per bank write bursts -system.physmem.perBankRdBursts::4 9715 # Per bank write bursts -system.physmem.perBankRdBursts::5 9765 # Per bank write bursts -system.physmem.perBankRdBursts::6 9098 # Per bank write bursts -system.physmem.perBankRdBursts::7 9032 # Per bank write bursts -system.physmem.perBankRdBursts::8 9205 # Per bank write bursts -system.physmem.perBankRdBursts::9 8593 # Per bank write bursts -system.physmem.perBankRdBursts::10 8826 # Per bank write bursts -system.physmem.perBankRdBursts::11 8653 # Per bank write bursts -system.physmem.perBankRdBursts::12 8623 # Per bank write bursts -system.physmem.perBankRdBursts::13 8667 # Per bank write bursts -system.physmem.perBankRdBursts::14 8699 # Per bank write bursts -system.physmem.perBankRdBursts::15 8967 # Per bank write bursts -system.physmem.perBankWrBursts::0 5976 # Per bank write bursts -system.physmem.perBankWrBursts::1 6230 # Per bank write bursts -system.physmem.perBankWrBursts::2 6094 # Per bank write bursts -system.physmem.perBankWrBursts::3 6205 # Per bank write bursts -system.physmem.perBankWrBursts::4 6124 # Per bank write bursts -system.physmem.perBankWrBursts::5 6340 # Per bank write bursts -system.physmem.perBankWrBursts::6 6054 # Per bank write bursts -system.physmem.perBankWrBursts::7 6041 # Per bank write bursts -system.physmem.perBankWrBursts::8 6001 # Per bank write bursts -system.physmem.perBankWrBursts::9 6103 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 736896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2854400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6176576 # Number of bytes read from this memory +system.physmem.bytes_read::total 9767872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 736896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 736896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6229632 # Number of bytes written to this memory +system.physmem.bytes_written::total 6229632 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 11514 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 44600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96509 # Number of read requests responded to by this memory +system.physmem.num_reads::total 152623 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97338 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97338 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21809646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 84480650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 182805897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 289096192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21809646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21809646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 184376176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 184376176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 184376176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21809646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 84480650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 182805897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 473472369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 152624 # Number of read requests accepted +system.physmem.writeReqs 97338 # Number of write requests accepted +system.physmem.readBursts 152624 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97338 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9758080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6227712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9767936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6229632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 27837 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9027 # Per bank write bursts +system.physmem.perBankRdBursts::1 9355 # Per bank write bursts +system.physmem.perBankRdBursts::2 9548 # Per bank write bursts +system.physmem.perBankRdBursts::3 12185 # Per bank write bursts +system.physmem.perBankRdBursts::4 10599 # Per bank write bursts +system.physmem.perBankRdBursts::5 10432 # Per bank write bursts +system.physmem.perBankRdBursts::6 9787 # Per bank write bursts +system.physmem.perBankRdBursts::7 9285 # Per bank write bursts +system.physmem.perBankRdBursts::8 9499 # Per bank write bursts +system.physmem.perBankRdBursts::9 9569 # Per bank write bursts +system.physmem.perBankRdBursts::10 9134 # Per bank write bursts +system.physmem.perBankRdBursts::11 8776 # Per bank write bursts +system.physmem.perBankRdBursts::12 8706 # Per bank write bursts +system.physmem.perBankRdBursts::13 8772 # Per bank write bursts +system.physmem.perBankRdBursts::14 8686 # Per bank write bursts +system.physmem.perBankRdBursts::15 9110 # Per bank write bursts +system.physmem.perBankWrBursts::0 5979 # Per bank write bursts +system.physmem.perBankWrBursts::1 6226 # Per bank write bursts +system.physmem.perBankWrBursts::2 6146 # Per bank write bursts +system.physmem.perBankWrBursts::3 6158 # Per bank write bursts +system.physmem.perBankWrBursts::4 6081 # Per bank write bursts +system.physmem.perBankWrBursts::5 6325 # Per bank write bursts +system.physmem.perBankWrBursts::6 6021 # Per bank write bursts +system.physmem.perBankWrBursts::7 5966 # Per bank write bursts +system.physmem.perBankWrBursts::8 5954 # Per bank write bursts +system.physmem.perBankWrBursts::9 6102 # Per bank write bursts system.physmem.perBankWrBursts::10 6248 # Per bank write bursts -system.physmem.perBankWrBursts::11 5916 # Per bank write bursts -system.physmem.perBankWrBursts::12 6074 # Per bank write bursts -system.physmem.perBankWrBursts::13 6102 # Per bank write bursts -system.physmem.perBankWrBursts::14 6204 # Per bank write bursts -system.physmem.perBankWrBursts::15 6028 # Per bank write bursts +system.physmem.perBankWrBursts::11 5872 # Per bank write bursts +system.physmem.perBankWrBursts::12 6030 # Per bank write bursts +system.physmem.perBankWrBursts::13 6061 # Per bank write bursts +system.physmem.perBankWrBursts::14 6151 # Per bank write bursts +system.physmem.perBankWrBursts::15 5988 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33346162500 # Total gap between requests +system.physmem.totGap 33787609500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145193 # Read request sizes (log2) +system.physmem.readPktSize::6 152624 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97768 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 41267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97338 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 49823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -197,102 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.437436 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.610569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.212794 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52129 58.86% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22374 25.26% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4601 5.19% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1696 1.91% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1069 1.21% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 812 0.92% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 692 0.78% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 790 0.89% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4403 4.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88566 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5908 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.550271 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.061813 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 186.955752 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5907 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5908 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5908 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.543670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.503041 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.228970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4711 79.74% 79.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.59% 80.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 768 13.00% 93.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 163 2.76% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 108 1.83% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 61 1.03% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 38 0.64% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.17% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.17% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5908 # Writes before turning the bus around for reads -system.physmem.totQLat 7011292666 # Total ticks spent queuing -system.physmem.totMemAccLat 9731617666 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 725420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 48325.75 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 95484 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 167.396422 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 105.401782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 235.895158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59753 62.58% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22097 23.14% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4150 4.35% 90.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1579 1.65% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 956 1.00% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 842 0.88% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 589 0.62% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 882 0.92% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4636 4.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 95484 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5850 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.058462 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 198.495488 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5849 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5850 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5850 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.633846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.583273 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.382653 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4554 77.85% 77.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 25 0.43% 78.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 781 13.35% 91.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 204 3.49% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 105 1.79% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 84 1.44% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 47 0.80% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 32 0.55% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.14% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5850 # Writes before turning the bus around for reads +system.physmem.totQLat 6712073801 # Total ticks spent queuing +system.physmem.totMemAccLat 9570886301 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 762350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44022.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 67075.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 278.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 187.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 278.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 187.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 62772.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 288.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 184.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 289.10 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 184.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.64 # Data bus utilization in percentage -system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.62 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.60 # Average write queue length when enqueuing -system.physmem.readRowHits 118088 # Number of row buffer hits during reads -system.physmem.writeRowHits 36158 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.98 # Row buffer hit rate for writes -system.physmem.avgGap 137249.03 # Average gap between requests -system.physmem.pageHitRate 63.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 342241200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186738750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 583385400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 317818080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2177653920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11790659475 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9661917750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25060414575 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.639504 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15978647517 # Time in different power states -system.physmem_0.memoryStateTime::REF 1113320000 # Time in different power states +system.physmem.busUtil 3.70 # Data bus utilization in percentage +system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 121004 # Number of row buffer hits during reads +system.physmem.writeRowHits 33280 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.19 # Row buffer hit rate for writes +system.physmem.avgGap 135170.98 # Average gap between requests +system.physmem.pageHitRate 61.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 375641280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204963000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 625404000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 316826640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15342350850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6812703000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25884530610 # Total energy per rank (pJ) +system.physmem_0.averagePower 766.158096 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11227638574 # Time in different power states +system.physmem_0.memoryStateTime::REF 1128140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16249048233 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21429077176 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 326909520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178373250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 547528800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315329760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2177653920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11234568330 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 10149705000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24930068580 # Total energy per rank (pJ) -system.physmem_1.averagePower 747.730472 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16793127980 # Time in different power states -system.physmem_1.memoryStateTime::REF 1113320000 # Time in different power states +system.physmem_1.actEnergy 346043880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 188813625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 563401800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313625520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13705423425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 8248614750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25572564840 # Total energy per rank (pJ) +system.physmem_1.averagePower 756.923807 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 13625050098 # Time in different power states +system.physmem_1.memoryStateTime::REF 1128140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15434548270 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19031683152 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17208509 # Number of BP lookups -system.cpu.branchPred.condPredicted 11519539 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648302 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9342884 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7675123 # Number of BTB hits +system.cpu.branchPred.lookups 17216173 # Number of BP lookups +system.cpu.branchPred.condPredicted 11524251 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 650211 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9349330 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7678783 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.149398 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872388 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.131907 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872954 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101563 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,95 +412,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66692841 # number of cpu cycles simulated +system.cpu.numCycles 67575239 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5046776 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88195647 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17208509 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9547511 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60140641 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322595 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6428 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13633 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22763338 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69414 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65868800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.694437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296898 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5134859 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88248834 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17216173 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9551737 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60707500 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1326839 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12635 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22778595 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 70008 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66523790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.678669 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300955 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20089005 30.50% 30.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8265359 12.55% 43.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9198123 13.96% 57.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28316313 42.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20715769 31.14% 31.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8270385 12.43% 43.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9211836 13.85% 57.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28325800 42.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65868800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258026 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.322416 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8616725 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19555814 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31576285 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5627882 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492094 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3179727 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171045 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101400911 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3043244 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492094 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13372904 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5353130 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 801467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32232883 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13616322 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99196979 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 981006 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3848899 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 63135 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4311075 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5311261 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103921430 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457681852 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115406862 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 66523790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.305934 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8696241 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 20116868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31576119 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5641245 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 493317 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3182236 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172097 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101426011 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3049995 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 493317 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13462916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5983097 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 839028 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32232549 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13512883 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99220100 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 979828 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3816376 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 66808 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4343458 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5148151 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103925700 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457807646 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115438955 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 552 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10292204 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18650 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12699652 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24320213 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21993792 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1400092 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2341142 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98161647 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34523 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94891012 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 695609 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7513585 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20245943 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 737 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65868800 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.440606 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.149928 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10296474 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18669 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12740509 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24326602 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22004719 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1418947 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2350394 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98183255 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94912265 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694103 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7535192 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20267739 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66523790 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.426742 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.152135 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17598833 26.72% 26.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17429188 26.46% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17113322 25.98% 79.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11675618 17.73% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2050869 3.11% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 970 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18209770 27.37% 27.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17473699 26.27% 53.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17129113 25.75% 79.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11665460 17.54% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2044780 3.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 968 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65868800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66523790 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6712111 22.40% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6707680 22.40% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 41 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available @@ -527,13 +528,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11183885 37.33% 59.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12062879 40.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11186120 37.35% 59.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12052780 40.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49494737 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89878 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49503200 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89866 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -554,91 +555,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24064392 25.36% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21241967 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24070106 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21249051 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94891012 # Type of FU issued -system.cpu.iq.rate 1.422807 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29958914 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315719 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286305140 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105721004 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93462242 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124849808 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1363438 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94912265 # Type of FU issued +system.cpu.iq.rate 1.404542 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29946621 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315519 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286988829 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105764420 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93479370 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124858764 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1365617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1453951 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2082 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1438054 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1460340 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2088 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11950 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1448981 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 138729 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 184462 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 137954 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185768 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492094 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 624554 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 468032 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98206039 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 493317 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 628934 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 513918 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98227667 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24320213 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21993792 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18603 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1634 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 463552 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302690 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221650 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524340 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93974044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23757485 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 916968 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24326602 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22004719 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1669 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 509191 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11950 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303594 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221648 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 525242 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93991933 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23762441 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 920332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9869 # number of nop insts executed -system.cpu.iew.exec_refs 44742217 # number of memory reference insts executed -system.cpu.iew.exec_branches 14251815 # Number of branches executed -system.cpu.iew.exec_stores 20984732 # Number of stores executed -system.cpu.iew.exec_rate 1.409057 # Inst execution rate -system.cpu.iew.wb_sent 93584291 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93462299 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44972986 # num instructions producing a value -system.cpu.iew.wb_consumers 76550519 # num instructions consuming a value +system.cpu.iew.exec_nop 9890 # number of nop insts executed +system.cpu.iew.exec_refs 44753885 # number of memory reference insts executed +system.cpu.iew.exec_branches 14253415 # Number of branches executed +system.cpu.iew.exec_stores 20991444 # Number of stores executed +system.cpu.iew.exec_rate 1.390923 # Inst execution rate +system.cpu.iew.wb_sent 93601796 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93479432 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44975266 # num instructions producing a value +system.cpu.iew.wb_consumers 76559860 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.401384 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587494 # average fanout of values written-back +system.cpu.iew.wb_rate 1.383339 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587452 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6533064 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6553334 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479099 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64811353 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.399263 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.164401 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 480109 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 65462437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.385346 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.157754 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31214732 48.16% 48.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16807105 25.93% 74.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4339311 6.70% 80.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4161583 6.42% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1937068 2.99% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1261836 1.95% 92.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 738743 1.14% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 580049 0.89% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3770926 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31857215 48.66% 48.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16813031 25.68% 74.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4347273 6.64% 80.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4157866 6.35% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1935310 2.96% 90.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1259510 1.92% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 744006 1.14% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 581672 0.89% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3766554 5.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64811353 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 65462437 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,386 +685,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3770926 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158236329 # The number of ROB reads -system.cpu.rob.rob_writes 195501562 # The number of ROB writes -system.cpu.timesIdled 24613 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 824041 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3766554 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158912055 # The number of ROB reads +system.cpu.rob.rob_writes 195546008 # The number of ROB writes +system.cpu.timesIdled 28044 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1051449 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.940559 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.940559 # CPI: Total CPI of All Threads -system.cpu.ipc 1.063197 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.063197 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102271310 # number of integer regfile reads -system.cpu.int_regfile_writes 56791274 # number of integer regfile writes -system.cpu.fp_regfile_reads 36 # number of floating regfile reads -system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346086877 # number of cc regfile reads -system.cpu.cc_regfile_writes 38805113 # number of cc regfile writes -system.cpu.misc_regfile_reads 44208470 # number of misc regfile reads +system.cpu.cpi 0.953004 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.953004 # CPI: Total CPI of All Threads +system.cpu.ipc 1.049314 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.049314 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102290506 # number of integer regfile reads +system.cpu.int_regfile_writes 56802248 # number of integer regfile writes +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.fp_regfile_writes 24 # number of floating regfile writes +system.cpu.cc_regfile_reads 346154538 # number of cc regfile reads +system.cpu.cc_regfile_writes 38804906 # number of cc regfile writes +system.cpu.misc_regfile_reads 44219892 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485016 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.742621 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40419295 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.248124 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 152905500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.742621 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997544 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997544 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485017 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.752563 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40412566 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485529 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.234093 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.752563 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997564 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84611982 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84611982 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21497006 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21497006 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830802 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830802 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60196 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60196 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15349 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15349 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84615901 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84615901 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21489624 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21489624 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831353 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831353 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60282 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60282 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15348 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15348 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40327808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40327808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40388004 # number of overall hits -system.cpu.dcache.overall_hits::total 40388004 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 555640 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 555640 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019099 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019099 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68639 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68639 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 40320977 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40320977 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40381259 # number of overall hits +system.cpu.dcache.overall_hits::total 40381259 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 564963 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 564963 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018548 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018548 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68572 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68572 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 577 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 577 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1574739 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1574739 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1643378 # number of overall misses -system.cpu.dcache.overall_misses::total 1643378 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9002363000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9002363000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14580629410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14580629410 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5329000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5329000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23582992410 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23582992410 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23582992410 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23582992410 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22052646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22052646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1583511 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1583511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1652083 # number of overall misses +system.cpu.dcache.overall_misses::total 1652083 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9256149500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9256149500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14245975429 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14245975429 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5465000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5465000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23502124929 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23502124929 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23502124929 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23502124929 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054587 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054587 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128835 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128835 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128854 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128854 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15925 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41902547 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41902547 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42031382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42031382 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025196 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025196 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051340 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051340 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532767 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532767 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036230 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036230 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037581 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037581 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039099 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039099 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16201.790728 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16201.790728 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14307.372895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14307.372895 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9235.701906 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9235.701906 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14975.810220 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14975.810220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14350.315271 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14350.315271 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3096615 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 130248 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.833333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.774760 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41904488 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904488 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42033342 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42033342 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025617 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025617 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051312 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051312 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532168 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532168 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037789 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037789 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039304 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039304 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16383.638398 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16383.638398 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13986.552847 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13986.552847 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9471.403813 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9471.403813 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14841.781919 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14841.781919 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14225.753143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14225.753143 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2896869 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131288 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.466667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.064995 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 253749 # number of writebacks -system.cpu.dcache.writebacks::total 253749 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 256216 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 256216 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870580 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870580 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 485017 # number of writebacks +system.cpu.dcache.writebacks::total 485017 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265550 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 265550 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870019 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870019 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 577 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 577 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1126796 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1126796 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1126796 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1126796 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299424 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299424 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148519 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148519 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37595 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37595 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447943 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447943 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485538 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485538 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3220458500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3220458500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2349684961 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2349684961 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2014368500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2014368500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5570143461 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5570143461 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7584511961 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7584511961 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013578 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013578 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291807 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1135569 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135569 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135569 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135569 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299413 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299413 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148529 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148529 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447942 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447942 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485539 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485539 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3625766000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3625766000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2305447971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2305447971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1884857000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1884857000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5931213971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5931213971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816070971 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7816070971 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291780 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291780 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10755.512250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10755.512250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.770144 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.770144 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53580.755420 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53580.755420 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12434.938064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12434.938064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15620.841131 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15620.841131 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011551 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011551 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12109.581080 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12109.581080 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15521.870954 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15521.870954 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50133.175519 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50133.175519 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13241.031140 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13241.031140 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16097.720206 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16097.720206 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 322602 # number of replacements -system.cpu.icache.tags.tagsinuse 510.289801 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22429330 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323114 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.416150 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1108313500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.289801 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996660 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996660 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 323105 # number of replacements +system.cpu.icache.tags.tagsinuse 510.281102 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22444187 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323617 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.354166 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.281102 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996643 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996643 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 350 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 341 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45849556 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45849556 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22429330 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22429330 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22429330 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22429330 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22429330 # number of overall hits -system.cpu.icache.overall_hits::total 22429330 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 333886 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 333886 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 333886 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 333886 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 333886 # number of overall misses -system.cpu.icache.overall_misses::total 333886 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3387462898 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3387462898 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3387462898 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3387462898 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3387462898 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3387462898 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22763216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22763216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22763216 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22763216 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22763216 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22763216 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014668 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014668 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014668 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10145.567343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10145.567343 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10145.567343 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10145.567343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10145.567343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10145.567343 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 275055 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45880575 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45880575 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22444187 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22444187 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22444187 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22444187 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22444187 # number of overall hits +system.cpu.icache.overall_hits::total 22444187 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 334287 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 334287 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 334287 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 334287 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 334287 # number of overall misses +system.cpu.icache.overall_misses::total 334287 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3550514898 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3550514898 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3550514898 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3550514898 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3550514898 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3550514898 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22778474 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22778474 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22778474 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22778474 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22778474 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22778474 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014676 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014676 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014676 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10621.157562 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10621.157562 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10621.157562 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10621.157562 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 261417 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16465 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16440 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.705436 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.901277 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10762 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 10762 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 10762 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 10762 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 10762 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 10762 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323124 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323124 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323124 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323124 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323124 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323124 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3106237439 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3106237439 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3106237439 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3106237439 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3106237439 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3106237439 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014195 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014195 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014195 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014195 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014195 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014195 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9613.143682 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9613.143682 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9613.143682 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9613.143682 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9613.143682 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9613.143682 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 323105 # number of writebacks +system.cpu.icache.writebacks::total 323105 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10659 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 10659 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 10659 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 10659 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 10659 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 10659 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323628 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 323628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 323628 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 323628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 323628 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 323628 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3274041434 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 3274041434 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3274041434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 3274041434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3274041434 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 3274041434 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014208 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014208 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014208 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10116.681604 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10116.681604 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10116.681604 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10116.681604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10116.681604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10116.681604 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 824554 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 825997 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 1265 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 822385 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 826178 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3328 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78883 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 129320 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16077.798328 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1332136 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 145605 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.148972 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78886 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 128056 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15991.461548 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1186413 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 144416 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.215246 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 12580.729391 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1435.218060 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1954.277207 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.573670 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.767867 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087599 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.119280 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006566 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.981311 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 27 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16258 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2698 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11935 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 582 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 887 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001648 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.992310 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 24877336 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 24877336 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 253749 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 253749 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 137176 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 137176 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 313988 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 313988 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 305816 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 305816 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 313988 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 442992 # 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number of writebacks +system.cpu.l2cache.writebacks::total 97338 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3200 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3200 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 27 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 27 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 107 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 107 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3307 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3334 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 3307 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3334 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112837 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 112837 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8287 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8287 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 11515 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 11515 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 36313 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 36313 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 11515 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 44600 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 56115 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 11515 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 44600 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112837 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168952 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10338050198 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10338050198 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 173000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 173000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 653811000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 653811000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 801316000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 801316000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2775072500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2775072500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 801316000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3428883500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4230199500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 801316000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3428883500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10338050198 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14568249698 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056032 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056032 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028133 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.092103 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.092103 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.081066 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059915 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.081066 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055781 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055781 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.035582 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.107764 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.107764 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069351 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.198976 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94466.292379 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17333.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17333.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80754.565113 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80754.565113 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71826.512651 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71826.512651 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80537.939812 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80537.939812 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71826.512651 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80583.752541 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78940.753354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71826.512651 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80583.752541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89791.262138 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.208803 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91619.328749 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78895.981658 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78895.981658 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69588.884064 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69588.884064 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76420.909867 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76420.909867 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75384.469393 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86227.151487 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1616280 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 807659 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 20376 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 20194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 182 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 660093 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 351517 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 505600 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 141126 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 1617289 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 808162 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79873 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 67046 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10433 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 660594 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 350764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 474834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 78545 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 142478 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323124 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336969 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938319 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2345110 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20679232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47313728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 67992960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 270457 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1886726 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.095537 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.294284 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148562 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148562 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336967 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 939793 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2346582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39434560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 58959360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 98393920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318372 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1127528 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.139590 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.372305 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1706655 90.46% 90.46% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 179889 9.53% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 182 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 980569 86.97% 86.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 136526 12.11% 99.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 10433 0.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1886726 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1061889000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485111148 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728499095 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1127528 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1616766500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 485882115 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 728582930 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 136869 # Transaction distribution -system.membus.trans_dist::Writeback 97768 # Transaction distribution -system.membus.trans_dist::CleanEvict 30364 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8324 # Transaction distribution -system.membus.trans_dist::ReadExResp 8324 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 136869 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 418530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 418530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15549504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15549504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 144336 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97338 # Transaction distribution +system.membus.trans_dist::CleanEvict 27827 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10 # Transaction distribution +system.membus.trans_dist::ReadExReq 8287 # Transaction distribution +system.membus.trans_dist::ReadExResp 8287 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 144337 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 430432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 430432 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15997504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15997504 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 273331 # Request fanout histogram +system.membus.snoop_fanout::samples 277799 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 273331 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 277799 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 273331 # Request fanout histogram -system.membus.reqLayer0.occupancy 739892708 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 277799 # Request fanout histogram +system.membus.reqLayer0.occupancy 747949896 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 756443702 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 797228853 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |