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authorGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:45 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:45 -0800
commit57e07ac2d2daaa7469241372510395e43ebe14c0 (patch)
treedc338f4fbe8b26f7d7d3532ea0abe324846ca33d /tests/long/se/50.vortex/ref
parentec20ee2f7cdaff22e63a5ae492f925d0d4839849 (diff)
downloadgem5-57e07ac2d2daaa7469241372510395e43ebe14c0.tar.xz
SE/FS: Make both SE and FS tests available all the time.
--HG-- rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => 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tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr rename : 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tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => 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tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simout => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout rename : tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr => 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tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simout => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout rename : tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/power/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/power/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/power/linux/o3-timing/simout => tests/quick/se/00.hello/ref/power/linux/o3-timing/simout rename : tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt rename : tests/quick/00.hello/test.py => tests/quick/se/00.hello/test.py rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simout => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py
Diffstat (limited to 'tests/long/se/50.vortex/ref')
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini240
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr6
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout11
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg158
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out258
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt315
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini535
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr6
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout11
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg158
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out258
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt517
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini102
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr6
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout11
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg158
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out258
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt77
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini205
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr6
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout11
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg158
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out258
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt266
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini535
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr2
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/o3-timing/simout11
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out258
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt544
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini102
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr2
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout11
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out258
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt87
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini205
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr2
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/simple-timing/simout11
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out258
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt280
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini102
-rwxr-xr-xtests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr563
-rwxr-xr-xtests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout11
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg158
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out258
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt45
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini205
-rwxr-xr-xtests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr563
-rwxr-xr-xtests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout11
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg158
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out258
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt244
51 files changed, 9131 insertions, 0 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
new file mode 100644
index 000000000..1b963b10c
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -0,0 +1,240 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+dataMemPort=dcache_port
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchBuffSize=4
+fetchMemPort=icache_port
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+stageTracing=false
+stageWidth=4
+system=system
+threadModel=SMT
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
new file mode 100755
index 000000000..0aab67a06
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:28:56
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 46914279500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg
new file mode 100644
index 000000000..472b08431
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg
@@ -0,0 +1,158 @@
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 4005c800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
new file mode 100644
index 000000000..32a07ce20
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -0,0 +1,315 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.046914 # Number of seconds simulated
+sim_ticks 46914279500 # Number of ticks simulated
+final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 107347 # Simulator instruction rate (inst/s)
+host_tick_rate 57007816 # Simulator tick rate (ticks/s)
+host_mem_usage 216192 # Number of bytes of host memory used
+host_seconds 822.94 # Real time elapsed on the host
+sim_insts 88340673 # Number of instructions simulated
+system.physmem.bytes_read 11164096 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7712960 # Number of bytes written to this memory
+system.physmem.num_reads 174439 # Number of read requests responded to by this memory
+system.physmem.num_writes 120515 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 237967973 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 12774277 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 164405381 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 402373354 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 20277222 # DTB read hits
+system.cpu.dtb.read_misses 90148 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 20367370 # DTB read accesses
+system.cpu.dtb.write_hits 14736811 # DTB write hits
+system.cpu.dtb.write_misses 7252 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 14744063 # DTB write accesses
+system.cpu.dtb.data_hits 35014033 # DTB hits
+system.cpu.dtb.data_misses 97400 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 35111433 # DTB accesses
+system.cpu.itb.fetch_hits 12380499 # ITB hits
+system.cpu.itb.fetch_misses 10576 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 12391075 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4583 # Number of system calls
+system.cpu.numCycles 93828560 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.contextSwitches 1 # Number of context switches
+system.cpu.threadCycles 77431415 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled 305691 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 24228941 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 69599619 # Number of cycles cpu stages are processed.
+system.cpu.activity 74.177435 # Percentage of cycles cpu is active
+system.cpu.comLoads 20276638 # Number of Load instructions committed
+system.cpu.comStores 14613377 # Number of Store instructions committed
+system.cpu.comBranches 13754477 # Number of Branches instructions committed
+system.cpu.comNops 8748916 # Number of Nop instructions committed
+system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
+system.cpu.comInts 30791227 # Number of Integer instructions committed
+system.cpu.comFloats 151453 # Number of Floating Point instructions committed
+system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
+system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
+system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.941512 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
+system.cpu.ipc_total 0.941512 # IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups 18761151 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 12342012 # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 4785453 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 15763185 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 4708455 # Number of BTB hits
+system.cpu.branch_predictor.usedRAS 1660959 # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct 29.869947 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 8112975 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 10648176 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 74148043 # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 126467293 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads 65874 # Number of Reads from FP Register File
+system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
+system.cpu.regfile_manager.floatRegFileAccesses 293504 # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards 14179622 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 35053135 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 4496417 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 178536 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 4674953 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 9097544 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 33.944121 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 44764178 # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
+system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
+system.cpu.stage0.idleCycles 41142190 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 52686370 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 56.151741 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 51376338 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 42452222 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 45.244456 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 50789796 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 43038764 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 45.869577 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 71702339 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 22126221 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 23.581542 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 47784207 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 46044353 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 49.072855 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements 83610 # number of replacements
+system.cpu.icache.tagsinuse 1886.858130 # Cycle average of tags in use
+system.cpu.icache.total_refs 12263478 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1886.858130 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.921317 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 12263478 # number of ReadReq hits
+system.cpu.icache.demand_hits 12263478 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 12263478 # number of overall hits
+system.cpu.icache.ReadReq_misses 116984 # number of ReadReq misses
+system.cpu.icache.demand_misses 116984 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 116984 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 2068004000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 2068004000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 2068004000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 12380462 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 12380462 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 12380462 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.009449 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.009449 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.009449 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 17677.665322 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 17677.665322 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 17677.665322 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 1596000 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 172 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 9279.069767 # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits 31328 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 31328 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 31328 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 85656 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 85656 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 85656 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 1345401500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 1345401500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 1345401500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.006919 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.006919 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.006919 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15707.031615 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 200251 # number of replacements
+system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use
+system.cpu.dcache.total_refs 34126014 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 167.000318 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4073.105766 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.994411 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 20180445 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 13945569 # number of WriteReq hits
+system.cpu.dcache.demand_hits 34126014 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 34126014 # number of overall hits
+system.cpu.dcache.ReadReq_misses 96193 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 667808 # number of WriteReq misses
+system.cpu.dcache.demand_misses 764001 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 764001 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 4158649000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 35332073000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 39490722000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 39490722000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.004744 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.045698 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.021897 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.021897 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 43232.345389 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 52907.531806 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 51689.359045 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 51689.359045 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 6330522500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 124112 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 161216 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 35426 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 524228 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 559654 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 559654 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 60767 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 143580 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 204347 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 204347 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2088724500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 7254420000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 9343144500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 9343144500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34372.677605 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.282073 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 148060 # number of replacements
+system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 131331 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 3005.792321 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15657.764606 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.091730 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.477837 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 103294 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 161216 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 12270 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 115564 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 115564 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 42939 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 131500 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 174439 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 174439 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 2242306500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 6854385000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 9096691500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 9096691500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 146233 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 161216 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 143770 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 290003 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 290003 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.293634 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.914655 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.601508 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.601508 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52220.743380 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52124.600760 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52148.266729 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52148.266729 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 120515 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 42939 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 131500 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 174439 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 174439 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1718628500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262711000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 6981339500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 6981339500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293634 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.914655 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.601508 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.601508 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.884138 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40020.615970 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644
index 000000000..ea038d4da
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
new file mode 100755
index 000000000..9e435cc97
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:35:02
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 21259532000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
new file mode 100644
index 000000000..472b08431
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
@@ -0,0 +1,158 @@
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 4005c800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
new file mode 100644
index 000000000..9c4b77b7d
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -0,0 +1,517 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.021260 # Number of seconds simulated
+sim_ticks 21259532000 # Number of ticks simulated
+final_tick 21259532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 187781 # Simulator instruction rate (inst/s)
+host_tick_rate 50157547 # Simulator tick rate (ticks/s)
+host_mem_usage 217440 # Number of bytes of host memory used
+host_seconds 423.86 # Real time elapsed on the host
+sim_insts 79591756 # Number of instructions simulated
+system.physmem.bytes_read 11229312 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 642688 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7713344 # Number of bytes written to this memory
+system.physmem.num_reads 175458 # Number of read requests responded to by this memory
+system.physmem.num_writes 120521 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 528201279 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 30230581 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 362818147 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 891019426 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 22309038 # DTB read hits
+system.cpu.dtb.read_misses 216523 # DTB read misses
+system.cpu.dtb.read_acv 41 # DTB read access violations
+system.cpu.dtb.read_accesses 22525561 # DTB read accesses
+system.cpu.dtb.write_hits 15629688 # DTB write hits
+system.cpu.dtb.write_misses 39366 # DTB write misses
+system.cpu.dtb.write_acv 9 # DTB write access violations
+system.cpu.dtb.write_accesses 15669054 # DTB write accesses
+system.cpu.dtb.data_hits 37938726 # DTB hits
+system.cpu.dtb.data_misses 255889 # DTB misses
+system.cpu.dtb.data_acv 50 # DTB access violations
+system.cpu.dtb.data_accesses 38194615 # DTB accesses
+system.cpu.itb.fetch_hits 13877051 # ITB hits
+system.cpu.itb.fetch_misses 28133 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 13905184 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4583 # Number of system calls
+system.cpu.numCycles 42519067 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.BPredUnit.lookups 16615602 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 10784809 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 464390 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 14543138 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8570194 # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS 1986002 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 35485 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 14905140 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 105779121 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16615602 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 10556196 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20616414 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2026173 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 4867777 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 5763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 282637 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 13877051 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 219292 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 42124503 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.511107 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.106328 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 21508089 51.06% 51.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2128231 5.05% 56.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1654689 3.93% 60.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2031982 4.82% 64.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 3913911 9.29% 74.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1970832 4.68% 78.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 733979 1.74% 80.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1130432 2.68% 83.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 7052358 16.74% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 42124503 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.390780 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.487804 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 15964361 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 4443062 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19692488 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 675645 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1348947 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3728678 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 99733 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 103933078 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 280329 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1348947 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 16452599 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2364451 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 84031 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19835916 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2038559 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102562493 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 192 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2676 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1925408 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 61709040 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 123636906 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 123159992 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 476914 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 9162159 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 5463 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 5460 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 4149992 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 23138107 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16243401 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1017520 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 376699 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 90712605 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 5415 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 88293060 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 101013 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10834162 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 4923026 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 832 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 42124503 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.096002 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.077334 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 13300851 31.58% 31.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 7326403 17.39% 48.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5817137 13.81% 62.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 4863957 11.55% 74.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4880067 11.58% 85.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2467879 5.86% 91.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1850711 4.39% 96.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1163401 2.76% 98.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 454097 1.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 42124503 # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 99927 5.41% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 1 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 762620 41.31% 46.72% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 983690 53.28% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49334128 55.88% 55.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 44107 0.05% 55.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 126794 0.14% 56.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 90 0.00% 56.07% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 127284 0.14% 56.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 38913 0.04% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 22763265 25.78% 82.04% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 15858425 17.96% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total 88293060 # Type of FU issued
+system.cpu.iq.rate 2.076552 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1846238 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.020910 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 220034609 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 101108296 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86316001 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 623265 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 459484 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 302223 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 89827554 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 311744 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1421900 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads 2861469 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 4255 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 15998 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1630024 # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads 1270 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles 1348947 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1395228 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 60292 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100209488 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 330917 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 23138107 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16243401 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 5415 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 42613 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 717 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 15998 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 305754 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 116766 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 422520 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 87324044 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 22528336 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 969016 # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp 0 # number of swp insts executed
+system.cpu.iew.exec_nop 9491468 # number of nop insts executed
+system.cpu.iew.exec_refs 38197877 # number of memory reference insts executed
+system.cpu.iew.exec_branches 15069707 # Number of branches executed
+system.cpu.iew.exec_stores 15669541 # Number of stores executed
+system.cpu.iew.exec_rate 2.053762 # Inst execution rate
+system.cpu.iew.wb_sent 87015038 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 86618224 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 32981280 # num instructions producing a value
+system.cpu.iew.wb_consumers 42978824 # num instructions consuming a value
+system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate 2.037162 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.767384 # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 8835054 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 366565 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 40775556 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.166511 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.804904 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 17645835 43.28% 43.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 7080138 17.36% 60.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3592753 8.81% 69.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2169640 5.32% 74.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2013725 4.94% 79.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1230420 3.02% 82.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1128970 2.77% 85.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 727312 1.78% 87.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5186763 12.72% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 40775556 # Number of insts commited each cycle
+system.cpu.commit.count 88340672 # Number of instructions committed
+system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.refs 34890015 # Number of memory references committed
+system.cpu.commit.loads 20276638 # Number of loads committed
+system.cpu.commit.membars 0 # Number of memory barriers committed
+system.cpu.commit.branches 13754477 # Number of branches committed
+system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1661057 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 5186763 # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads 131447177 # The number of ROB reads
+system.cpu.rob.rob_writes 195703293 # The number of ROB writes
+system.cpu.timesIdled 15923 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 394564 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 79591756 # Number of Instructions Simulated
+system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
+system.cpu.cpi 0.534214 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.534214 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.871907 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.871907 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 115518864 # number of integer regfile reads
+system.cpu.int_regfile_writes 57354047 # number of integer regfile writes
+system.cpu.fp_regfile_reads 252314 # number of floating regfile reads
+system.cpu.fp_regfile_writes 251108 # number of floating regfile writes
+system.cpu.misc_regfile_reads 38108 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.icache.replacements 88378 # number of replacements
+system.cpu.icache.tagsinuse 1927.638696 # Cycle average of tags in use
+system.cpu.icache.total_refs 13782143 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 90426 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 152.413498 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 17839872000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1927.638696 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.941230 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 13782143 # number of ReadReq hits
+system.cpu.icache.demand_hits 13782143 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 13782143 # number of overall hits
+system.cpu.icache.ReadReq_misses 94908 # number of ReadReq misses
+system.cpu.icache.demand_misses 94908 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 94908 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 914028500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 914028500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 914028500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 13877051 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 13877051 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 13877051 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.006839 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.006839 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.006839 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 9630.679184 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 9630.679184 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 9630.679184 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
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+system.cpu.icache.ReadReq_mshr_hits 4481 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 4481 # number of demand (read+write) MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses 90427 # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_misses 90427 # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency 542589500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 542589500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 542589500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.006516 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.006516 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.006516 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 6000.304113 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 6000.304113 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 6000.304113 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 201340 # number of replacements
+system.cpu.dcache.tagsinuse 4076.154176 # Cycle average of tags in use
+system.cpu.dcache.total_refs 34207250 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 205436 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 166.510495 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 157430000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4076.154176 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.995155 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 20628725 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 13578476 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 49 # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits 34207201 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 34207201 # number of overall hits
+system.cpu.dcache.ReadReq_misses 257071 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 1034901 # number of WriteReq misses
+system.cpu.dcache.demand_misses 1291972 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 1291972 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 8273144500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 33900181500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 42173326000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 42173326000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 20885796 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 49 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 35499173 # number of demand (read+write) accesses
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+system.cpu.dcache.ReadReq_miss_rate 0.012308 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.070819 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.036394 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.036394 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 32182.332896 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 32756.931822 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 32642.600614 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 32642.600614 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 53500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2675 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
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+system.cpu.dcache.writebacks 161613 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 195029 # number of ReadReq MSHR hits
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+system.cpu.dcache.overall_mshr_hits 1086536 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 62042 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 143394 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 205436 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 205436 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 1278233000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 4733826000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 6012059000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 6012059000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002971 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009813 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.005787 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.005787 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20602.704619 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33012.720197 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 29264.875679 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 29264.875679 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 149119 # number of replacements
+system.cpu.l2cache.tagsinuse 18923.797261 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 136861 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 174485 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.784371 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 3200.297768 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15723.499493 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.097665 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.479843 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 108391 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 161613 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 12014 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 120405 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 120405 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 44050 # number of ReadReq misses
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+system.cpu.l2cache.demand_misses 175458 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 175458 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 1516062500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 4525488500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 6041551000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 6041551000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 152441 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 161613 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 143422 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 295863 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 295863 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.288964 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.916233 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.593038 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.593038 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34416.855846 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34438.455041 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34433.032407 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34433.032407 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 120521 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 44050 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 131408 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 175458 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 175458 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1367587500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4118168500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 5485756000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 5485756000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.288964 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.916233 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.593038 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.593038 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31046.254257 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31338.795964 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31265.351252 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31265.351252 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644
index 000000000..d8535707b
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
new file mode 100755
index 000000000..160c80ddb
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:17
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 44221003000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
new file mode 100644
index 000000000..472b08431
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
@@ -0,0 +1,158 @@
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 4005c800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
new file mode 100644
index 000000000..4fc91e266
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -0,0 +1,77 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.044221 # Number of seconds simulated
+sim_ticks 44221003000 # Number of ticks simulated
+final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3998504 # Simulator instruction rate (inst/s)
+host_tick_rate 2001543652 # Simulator tick rate (ticks/s)
+host_mem_usage 206876 # Number of bytes of host memory used
+host_seconds 22.09 # Real time elapsed on the host
+sim_insts 88340673 # Number of instructions simulated
+system.physmem.bytes_read 480454939 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 353752292 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 91652896 # Number of bytes written to this memory
+system.physmem.num_reads 108714711 # Number of read requests responded to by this memory
+system.physmem.num_writes 14613377 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 10864858470 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999644241 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2072610067 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 12937468537 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 20276638 # DTB read hits
+system.cpu.dtb.read_misses 90148 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 20366786 # DTB read accesses
+system.cpu.dtb.write_hits 14613377 # DTB write hits
+system.cpu.dtb.write_misses 7252 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 14620629 # DTB write accesses
+system.cpu.dtb.data_hits 34890015 # DTB hits
+system.cpu.dtb.data_misses 97400 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 34987415 # DTB accesses
+system.cpu.itb.fetch_hits 88438073 # ITB hits
+system.cpu.itb.fetch_misses 3934 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 88442007 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4583 # Number of system calls
+system.cpu.numCycles 88442007 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 88340673 # Number of instructions executed
+system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
+system.cpu.num_func_calls 3321606 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
+system.cpu.num_int_insts 78039444 # number of integer instructions
+system.cpu.num_fp_insts 267757 # number of float instructions
+system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
+system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
+system.cpu.num_mem_refs 34987415 # number of memory refs
+system.cpu.num_load_insts 20366786 # Number of load instructions
+system.cpu.num_store_insts 14620629 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 88442007 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644
index 000000000..f99b5fb55
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
new file mode 100755
index 000000000..1b49765a7
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
@@ -0,0 +1,6 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
new file mode 100755
index 000000000..e74b48d2a
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:42:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 134276988000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
new file mode 100644
index 000000000..472b08431
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
@@ -0,0 +1,158 @@
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 4005c800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
new file mode 100644
index 000000000..59b869a9f
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -0,0 +1,266 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.134277 # Number of seconds simulated
+sim_ticks 134276988000 # Number of ticks simulated
+final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1801981 # Simulator instruction rate (inst/s)
+host_tick_rate 2738992827 # Simulator tick rate (ticks/s)
+host_mem_usage 215584 # Number of bytes of host memory used
+host_seconds 49.02 # Real time elapsed on the host
+sim_insts 88340673 # Number of instructions simulated
+system.physmem.bytes_read 11121920 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 558272 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 7712384 # Number of bytes written to this memory
+system.physmem.num_reads 173780 # Number of read requests responded to by this memory
+system.physmem.num_writes 120506 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 82828191 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 4157615 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 57436379 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 140264570 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 20276638 # DTB read hits
+system.cpu.dtb.read_misses 90148 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 20366786 # DTB read accesses
+system.cpu.dtb.write_hits 14613377 # DTB write hits
+system.cpu.dtb.write_misses 7252 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 14620629 # DTB write accesses
+system.cpu.dtb.data_hits 34890015 # DTB hits
+system.cpu.dtb.data_misses 97400 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 34987415 # DTB accesses
+system.cpu.itb.fetch_hits 88438074 # ITB hits
+system.cpu.itb.fetch_misses 3934 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 88442008 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4583 # Number of system calls
+system.cpu.numCycles 268553976 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 88340673 # Number of instructions executed
+system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
+system.cpu.num_func_calls 3321606 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
+system.cpu.num_int_insts 78039444 # number of integer instructions
+system.cpu.num_fp_insts 267757 # number of float instructions
+system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
+system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
+system.cpu.num_mem_refs 34987415 # number of memory refs
+system.cpu.num_load_insts 20366786 # Number of load instructions
+system.cpu.num_store_insts 14620629 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 268553976 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 74391 # number of replacements
+system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use
+system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.913772 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
+system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 88361638 # number of overall hits
+system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
+system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 76436 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 1436470000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 1436470000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 1436470000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 18793.107960 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 18793.107960 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 18793.107960 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 1207162000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 1207162000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 1207162000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 200248 # number of replacements
+system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use
+system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4078.858373 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.995815 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
+system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 34685671 # number of overall hits
+system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
+system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 204344 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 2261000000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 7532210000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 9793210000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 9793210000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 47925.116470 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 47925.116470 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 161222 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2078702000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 7101476000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 9180178000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 9180178000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34208.307277 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49460.753040 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 147405 # number of replacements
+system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.085649 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.482430 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 94901 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 161222 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 107000 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 107000 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 42301 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 173780 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 173780 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 2199652000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 6836908000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 9036560000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 9036560000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 161222 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.308312 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.618919 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.618919 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 120506 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 42301 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 173780 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 173780 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1692040000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259160000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 6951200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 6951200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.308312 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.618919 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.618919 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..1feff9641
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..41153b9d0
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:34:51
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 31183407000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..858b9d08f
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,544 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.031183 # Number of seconds simulated
+sim_ticks 31183407000 # Number of ticks simulated
+final_tick 31183407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 157932 # Simulator instruction rate (inst/s)
+host_tick_rate 48938242 # Simulator tick rate (ticks/s)
+host_mem_usage 229072 # Number of bytes of host memory used
+host_seconds 637.20 # Real time elapsed on the host
+sim_insts 100634165 # Number of instructions simulated
+system.physmem.bytes_read 8651648 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 350016 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5661184 # Number of bytes written to this memory
+system.physmem.num_reads 135182 # Number of read requests responded to by this memory
+system.physmem.num_writes 88456 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 277443962 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 11224431 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 181544756 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 458988718 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 62366815 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.BPredUnit.lookups 17631068 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11525225 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 822451 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 15041021 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 9743390 # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS 1887340 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 176888 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 12968459 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 88523933 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 17631068 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11630730 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22984896 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2898005 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 23107334 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 525 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 12208408 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 230644 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 61059715 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.021356 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.077680 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 38090584 62.38% 62.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2437224 3.99% 66.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2605062 4.27% 70.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2470326 4.05% 74.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1717744 2.81% 77.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1704134 2.79% 80.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1004081 1.64% 81.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1295541 2.12% 84.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9735019 15.94% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 61059715 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.282700 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.419408 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 14872380 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 21838408 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 21376813 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1070090 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1902024 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3467429 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 98061 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 120316029 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 332599 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1902024 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 16801594 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2005674 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 15516104 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 20489827 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4344492 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 117017437 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 3607 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 2996198 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 60 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 118959985 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 538237718 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 538236225 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1493 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 99144333 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 19815652 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 778147 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 778546 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12135199 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29749057 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 22305499 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2463618 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 3436887 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 111737256 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 774255 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 107616850 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 306406 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 11658627 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 29328565 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 71223 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 61059715 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.762485 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.902924 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 22160160 36.29% 36.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 11614525 19.02% 55.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8577298 14.05% 69.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7396039 12.11% 81.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4782616 7.83% 89.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3521695 5.77% 95.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1664317 2.73% 97.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 809749 1.33% 99.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 533316 0.87% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 61059715 # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 88066 3.33% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1488278 56.33% 59.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 1065734 40.34% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57002654 52.97% 52.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 87399 0.08% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 39 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 28992824 26.94% 79.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21533927 20.01% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total 107616850 # Type of FU issued
+system.cpu.iq.rate 1.725547 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2642078 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.024551 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 279241693 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 124185257 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 105412682 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 206 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 204 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 110258821 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 107 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1870348 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads 2440492 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 3482 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 15956 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1748305 # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads 52 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles 1902024 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 953128 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 28578 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 112587966 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 618611 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 29749057 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 22305499 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 756996 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1135 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1192 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 15956 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 682416 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 198748 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 881164 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 106274273 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 28622040 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1342577 # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp 0 # number of swp insts executed
+system.cpu.iew.exec_nop 76455 # number of nop insts executed
+system.cpu.iew.exec_refs 49853649 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14601408 # Number of branches executed
+system.cpu.iew.exec_stores 21231609 # Number of stores executed
+system.cpu.iew.exec_rate 1.704020 # Inst execution rate
+system.cpu.iew.wb_sent 105725224 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 105412758 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 52507879 # num instructions producing a value
+system.cpu.iew.wb_consumers 101154765 # num instructions consuming a value
+system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate 1.690206 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.519085 # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts 100639717 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 11948697 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 703032 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 788200 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 59157692 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.701211 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.430896 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 26246617 44.37% 44.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 14635662 24.74% 69.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4223894 7.14% 76.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 3641491 6.16% 82.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2268632 3.83% 86.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1889350 3.19% 89.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 703853 1.19% 90.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 498146 0.84% 91.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5050047 8.54% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 59157692 # Number of insts commited each cycle
+system.cpu.commit.count 100639717 # Number of instructions committed
+system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.refs 47865759 # Number of memory references committed
+system.cpu.commit.loads 27308565 # Number of loads committed
+system.cpu.commit.membars 15920 # Number of memory barriers committed
+system.cpu.commit.branches 13670084 # Number of branches committed
+system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 91478611 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1679850 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 5050047 # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads 166670760 # The number of ROB reads
+system.cpu.rob.rob_writes 227084538 # The number of ROB writes
+system.cpu.timesIdled 61622 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 1307100 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 100634165 # Number of Instructions Simulated
+system.cpu.committedInsts_total 100634165 # Number of Instructions Simulated
+system.cpu.cpi 0.619738 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.619738 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.613585 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.613585 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 511657086 # number of integer regfile reads
+system.cpu.int_regfile_writes 103892124 # number of integer regfile writes
+system.cpu.fp_regfile_reads 166 # number of floating regfile reads
+system.cpu.fp_regfile_writes 126 # number of floating regfile writes
+system.cpu.misc_regfile_reads 146210782 # number of misc regfile reads
+system.cpu.misc_regfile_writes 34752 # number of misc regfile writes
+system.cpu.icache.replacements 26083 # number of replacements
+system.cpu.icache.tagsinuse 1805.405384 # Cycle average of tags in use
+system.cpu.icache.total_refs 12179175 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 28115 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 433.191357 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1805.405384 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.881546 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 12179178 # number of ReadReq hits
+system.cpu.icache.demand_hits 12179178 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 12179178 # number of overall hits
+system.cpu.icache.ReadReq_misses 29230 # number of ReadReq misses
+system.cpu.icache.demand_misses 29230 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 29230 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 357885000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 357885000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 357885000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 12208408 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 12208408 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 12208408 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.002394 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.002394 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.002394 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 12243.756415 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 12243.756415 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 12243.756415 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 1 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits 1069 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 1069 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 1069 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 28161 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 28161 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 28161 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 246973000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 246973000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 246973000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.002307 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.002307 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.002307 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 8770.036575 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 157879 # number of replacements
+system.cpu.dcache.tagsinuse 4072.329363 # Cycle average of tags in use
+system.cpu.dcache.total_refs 44742203 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 161975 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 276.229066 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 306596000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4072.329363 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.994221 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 26395464 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 18310275 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 18919 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits 17375 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 44705739 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 44705739 # number of overall hits
+system.cpu.dcache.ReadReq_misses 108834 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 1539626 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses 1648460 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 1648460 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 2418698500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 52283649500 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency 386000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency 54702348000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 54702348000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 26504298 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 18946 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 17375 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 46354199 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 46354199 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.004106 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate 0.001425 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate 0.035562 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.035562 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 22223.739824 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33958.668859 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 14296.296296 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 33183.909831 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 33183.909831 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 123472 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 53734 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 1432703 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 1486437 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 1486437 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 55100 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 106923 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 162023 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 162023 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 1035726000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 3662471000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 4698197000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 4698197000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002079 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.005387 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.003495 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.003495 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18797.205082 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34253.350542 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 114920 # number of replacements
+system.cpu.l2cache.tagsinuse 18304.700184 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 72415 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.541323 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 2370.650310 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15934.049874 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.072347 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.486269 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 50510 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 123473 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits 16 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits 4309 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 54819 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 54819 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 32664 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses 31 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 135262 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 135262 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 1118309000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 3526121000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 4644430000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 4644430000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 83174 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 123473 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses 47 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 106907 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 190081 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 190081 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.392719 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate 0.659574 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.959694 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.711602 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.711602 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34236.743816 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.321020 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34336.546850 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34336.546850 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 88456 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 80 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 32584 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 135182 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 135182 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1012754000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 962000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197891500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 4210645500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 4210645500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.391757 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.659574 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959694 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.711181 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.711181 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.328259 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31032.258065 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.140724 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..321a621c1
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..cba7edc9e
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:35:25
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 53932162000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..550377594
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.053932 # Number of seconds simulated
+sim_ticks 53932162000 # Number of ticks simulated
+final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3016681 # Simulator instruction rate (inst/s)
+host_tick_rate 1616735818 # Simulator tick rate (ticks/s)
+host_mem_usage 217624 # Number of bytes of host memory used
+host_seconds 33.36 # Real time elapsed on the host
+sim_insts 100632437 # Number of instructions simulated
+system.physmem.bytes_read 419153654 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 312580308 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 78660211 # Number of bytes written to this memory
+system.physmem.num_reads 105301330 # Number of read requests responded to by this memory
+system.physmem.num_writes 19865820 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 7771868185 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 5795805256 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1458502832 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9230371017 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 107864325 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 100632437 # Number of instructions executed
+system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
+system.cpu.num_func_calls 3287514 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
+system.cpu.num_int_insts 91472788 # number of integer instructions
+system.cpu.num_fp_insts 56 # number of float instructions
+system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read
+system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
+system.cpu.num_mem_refs 47862848 # number of memory refs
+system.cpu.num_load_insts 27307109 # Number of load instructions
+system.cpu.num_store_insts 20555739 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 107864325 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..62eb4cdbf
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..4fb750502
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:36:06
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 133117442000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..2fff6cef5
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,280 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.133117 # Number of seconds simulated
+sim_ticks 133117442000 # Number of ticks simulated
+final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1410680 # Simulator instruction rate (inst/s)
+host_tick_rate 1881780580 # Simulator tick rate (ticks/s)
+host_mem_usage 226592 # Number of bytes of host memory used
+host_seconds 70.74 # Real time elapsed on the host
+sim_insts 99791663 # Number of instructions simulated
+system.physmem.bytes_read 8570688 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 294208 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5660736 # Number of bytes written to this memory
+system.physmem.num_reads 133917 # Number of read requests responded to by this memory
+system.physmem.num_writes 88449 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 64384410 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 2210139 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 42524375 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 106908785 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 266234884 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 99791663 # Number of instructions executed
+system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
+system.cpu.num_func_calls 3287514 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8920660 # number of instructions that are conditional controls
+system.cpu.num_int_insts 91472788 # number of integer instructions
+system.cpu.num_fp_insts 56 # number of float instructions
+system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read
+system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
+system.cpu.num_mem_refs 47862848 # number of memory refs
+system.cpu.num_load_insts 27307109 # Number of load instructions
+system.cpu.num_store_insts 20555739 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 266234884 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 16890 # number of replacements
+system.cpu.icache.tagsinuse 1736.182852 # Cycle average of tags in use
+system.cpu.icache.total_refs 78126170 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1736.182852 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.847746 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 78126170 # number of ReadReq hits
+system.cpu.icache.demand_hits 78126170 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 78126170 # number of overall hits
+system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses
+system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 18908 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 457786000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 457786000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 457786000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 78145078 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 78145078 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 78145078 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000242 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 24211.233340 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 24211.233340 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 24211.233340 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 401062000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 401062000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 401062000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000242 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 155902 # number of replacements
+system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use
+system.cpu.dcache.total_refs 46862075 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4076.934010 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.995345 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 27087368 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 19742869 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 15919 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits 15919 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 46830237 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 46830237 # number of overall hits
+system.cpu.dcache.ReadReq_misses 52966 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 107032 # number of WriteReq misses
+system.cpu.dcache.demand_misses 159998 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 159998 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 1862630000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 5808782000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 7671412000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 7671412000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 27140334 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 15919 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 15919 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 46990235 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 46990235 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.005392 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.003405 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.003405 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 47946.924337 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 47946.924337 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 122808 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 52966 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 107032 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 159998 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 159998 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 1703732000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 5487686000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 7191418000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 7191418000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.005392 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.003405 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.003405 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 113660 # number of replacements
+system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 61800 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.466454 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 2165.921088 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 16025.699940 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.066099 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.489066 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 40584 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 122808 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 4405 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 44989 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 44989 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 31290 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 102627 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 133917 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 133917 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 1627080000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 5336604000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 6963684000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 6963684000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 71874 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 122808 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 107032 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 178906 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 178906 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.435345 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.958844 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.748533 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.748533 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 88449 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 31290 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 102627 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 133917 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 133917 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1251600000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4105080000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 5356680000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 5356680000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.435345 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.958844 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.748533 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.748533 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..2df6b792d
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex bendian.raw
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
new file mode 100755
index 000000000..bb51748c6
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
@@ -0,0 +1,563 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: ignoring syscall time(4026528248, 4026527848, ...)
+warn: ignoring syscall time(1375098, 4026527400, ...)
+warn: ignoring syscall time(1, 4026527312, ...)
+warn: ignoring syscall time(413, 4026527048, ...)
+warn: ignoring syscall time(414, 4026527048, ...)
+warn: ignoring syscall time(4026527688, 4026527288, ...)
+warn: ignoring syscall time(1375098, 4026526840, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526960, ...)
+warn: ignoring syscall time(409, 4026527040, ...)
+warn: ignoring syscall time(409, 4026527000, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(19045, 4026526312, ...)
+warn: ignoring syscall time(409, 4026526832, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526840, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526936, ...)
+warn: ignoring syscall time(4026527408, 4026527008, ...)
+warn: ignoring syscall time(1375098, 4026526560, ...)
+warn: ignoring syscall time(18732, 4026527184, ...)
+warn: ignoring syscall time(409, 4026526632, ...)
+warn: ignoring syscall time(0, 4026526736, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(225, 4026527744, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(4026527496, 4026527096, ...)
+warn: ignoring syscall time(1375098, 4026526648, ...)
+warn: ignoring syscall time(0, 4026526824, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(1879089152, 4026527184, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall time(1595768, 4026527472, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(20500, 4026525968, ...)
+warn: ignoring syscall time(4026526436, 4026525968, ...)
+warn: ignoring syscall time(7004192, 4026526056, ...)
+warn: ignoring syscall time(4, 4026527512, ...)
+warn: ignoring syscall time(0, 4026525760, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
new file mode 100755
index 000000000..542479326
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:24:20
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 68148678500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
new file mode 100644
index 000000000..0ac2d9980
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
@@ -0,0 +1,158 @@
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := False
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 4
+ sizeof(longaddr ) = 4
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 4
+ sizeof(char * ) = 4
+ ALLOC CORE_1 :: 8
+ BHOOLE NATH
+
+ OPEN File ./input/bendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 1b4750
+
+ OPEN File ./input/bendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..dc6c31998
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.068149 # Number of seconds simulated
+sim_ticks 68148678500 # Number of ticks simulated
+final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3420916 # Simulator instruction rate (inst/s)
+host_tick_rate 1712444497 # Simulator tick rate (ticks/s)
+host_mem_usage 214012 # Number of bytes of host memory used
+host_seconds 39.80 # Real time elapsed on the host
+sim_insts 136139203 # Number of instructions simulated
+system.physmem.bytes_read 685773693 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 538214332 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 89882950 # Number of bytes written to this memory
+system.physmem.num_reads 171784884 # Number of read requests responded to by this memory
+system.physmem.num_writes 20864304 # Number of write requests responded to by this memory
+system.physmem.num_other 15916 # Number of other requests responded to by this memory
+system.physmem.bw_read 10062905226 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7897648844 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1318924328 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11381829554 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 136297358 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 136139203 # Number of instructions executed
+system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
+system.cpu.num_func_calls 1709332 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8898970 # number of instructions that are conditional controls
+system.cpu.num_int_insts 115187758 # number of integer instructions
+system.cpu.num_fp_insts 2326977 # number of float instructions
+system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read
+system.cpu.num_int_register_writes 113147747 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
+system.cpu.num_mem_refs 58160249 # number of memory refs
+system.cpu.num_load_insts 37275868 # Number of load instructions
+system.cpu.num_store_insts 20884381 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 136297358 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
new file mode 100644
index 000000000..5e34ae7a1
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex bendian.raw
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
new file mode 100755
index 000000000..bb51748c6
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
@@ -0,0 +1,563 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: ignoring syscall time(4026528248, 4026527848, ...)
+warn: ignoring syscall time(1375098, 4026527400, ...)
+warn: ignoring syscall time(1, 4026527312, ...)
+warn: ignoring syscall time(413, 4026527048, ...)
+warn: ignoring syscall time(414, 4026527048, ...)
+warn: ignoring syscall time(4026527688, 4026527288, ...)
+warn: ignoring syscall time(1375098, 4026526840, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526960, ...)
+warn: ignoring syscall time(409, 4026527040, ...)
+warn: ignoring syscall time(409, 4026527000, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(19045, 4026526312, ...)
+warn: ignoring syscall time(409, 4026526832, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526840, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526936, ...)
+warn: ignoring syscall time(4026527408, 4026527008, ...)
+warn: ignoring syscall time(1375098, 4026526560, ...)
+warn: ignoring syscall time(18732, 4026527184, ...)
+warn: ignoring syscall time(409, 4026526632, ...)
+warn: ignoring syscall time(0, 4026526736, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(225, 4026527744, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(4026527496, 4026527096, ...)
+warn: ignoring syscall time(1375098, 4026526648, ...)
+warn: ignoring syscall time(0, 4026526824, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(1879089152, 4026527184, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall time(1595768, 4026527472, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(20500, 4026525968, ...)
+warn: ignoring syscall time(4026526436, 4026525968, ...)
+warn: ignoring syscall time(7004192, 4026526056, ...)
+warn: ignoring syscall time(4, 4026527512, ...)
+warn: ignoring syscall time(0, 4026525760, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
new file mode 100755
index 000000000..787eaa97a
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:24:48
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 202941992000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg
new file mode 100644
index 000000000..0ac2d9980
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg
@@ -0,0 +1,158 @@
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := False
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 4
+ sizeof(longaddr ) = 4
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 4
+ sizeof(char * ) = 4
+ ALLOC CORE_1 :: 8
+ BHOOLE NATH
+
+ OPEN File ./input/bendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 1b4750
+
+ OPEN File ./input/bendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..168a8eefa
--- /dev/null
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -0,0 +1,244 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.202942 # Number of seconds simulated
+sim_ticks 202941992000 # Number of ticks simulated
+final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1608666 # Simulator instruction rate (inst/s)
+host_tick_rate 2398029397 # Simulator tick rate (ticks/s)
+host_mem_usage 222724 # Number of bytes of host memory used
+host_seconds 84.63 # Real time elapsed on the host
+sim_insts 136139203 # Number of instructions simulated
+system.physmem.bytes_read 8970304 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 835264 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 5584960 # Number of bytes written to this memory
+system.physmem.num_reads 140161 # Number of read requests responded to by this memory
+system.physmem.num_writes 87265 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 44201320 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 4115777 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 27519982 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 71721303 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 405883984 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 136139203 # Number of instructions executed
+system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
+system.cpu.num_func_calls 1709332 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8898970 # number of instructions that are conditional controls
+system.cpu.num_int_insts 115187758 # number of integer instructions
+system.cpu.num_fp_insts 2326977 # number of float instructions
+system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read
+system.cpu.num_int_register_writes 113147746 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
+system.cpu.num_mem_refs 58160249 # number of memory refs
+system.cpu.num_load_insts 37275868 # Number of load instructions
+system.cpu.num_store_insts 20884381 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 405883984 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 184976 # number of replacements
+system.cpu.icache.tagsinuse 2004.721102 # Cycle average of tags in use
+system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 144544557000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 2004.721102 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.978868 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits
+system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 134366560 # number of overall hits
+system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
+system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 187024 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 3166478000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 3166478000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 3166478000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 16930.864488 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 16930.864488 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 16930.864488 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 2605406000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 2605406000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 2605406000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 13930.864488 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 13930.864488 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 146582 # number of replacements
+system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use
+system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 776708000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4087.617150 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.997953 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 20759140 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits
+system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 57944942 # number of overall hits
+system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 105164 # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses
+system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 150663 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 1709246000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 5738404000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency 462000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency 7447650000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 7447650000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.005040 # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 37566.671795 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 54566.239398 # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 30800 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 49432.508313 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 49432.508313 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 118818 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 105164 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 1572749000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 5422912000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency 417000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 6995661000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 6995661000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.005040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34566.671795 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51566.239398 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 27800 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 46432.508313 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 120138 # number of replacements
+system.cpu.l2cache.tagsinuse 19734.031622 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 212003 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 139002 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.525179 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 3965.924560 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15768.107062 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.121030 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.481204 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 193942 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 118818 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 3599 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 197541 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 197541 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 38581 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 101580 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 140161 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 140161 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 2006212000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 5282160000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 7288372000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 7288372000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 118818 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.165923 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.965782 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.415043 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.415043 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 87265 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 38581 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 101580 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 140161 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 140161 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1543240000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4063200000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 5606440000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 5606440000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165923 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.965782 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.415043 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.415043 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------