diff options
| author | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-07-23 16:09:05 -0500 |
|---|---|---|
| committer | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-07-23 16:09:05 -0500 |
| commit | 5d0b25ba3f82b6d563b3fabd3de71f3ceabb140d (patch) | |
| tree | 0b8cdef424988f3486a9f2cebbb49f76b74ae8f9 /tests/long/se/50.vortex/ref | |
| parent | 0e8a90f06bd3db00f700891a33458353478cce76 (diff) | |
| download | gem5-5d0b25ba3f82b6d563b3fabd3de71f3ceabb140d.tar.xz | |
cpu: Minor CPU add regression tests for ARM and ALPHA
This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
Diffstat (limited to 'tests/long/se/50.vortex/ref')
8 files changed, 2956 insertions, 0 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini new file mode 100644 index 000000000..608f400a3 --- /dev/null +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini @@ -0,0 +1,718 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=vortex lendian.raw +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/alpha/tru64/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr new file mode 100644 index 000000000..506aa6e28 --- /dev/null +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr @@ -0,0 +1,5 @@ +warn: Sockets disabled, not accepting gdb connections +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout new file mode 100644 index 000000000..bfc5e794b --- /dev/null +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout @@ -0,0 +1,13 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:41:53 +gem5 started May 7 2014 11:01:25 +gem5 executing on cz3212c2d7 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 58222132000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt new file mode 100644 index 000000000..8796e7316 --- /dev/null +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,660 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 58437370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 298644 # Simulator instruction rate (inst/s) +host_mem_usage 257212 # Number of bytes of host memory used +host_op_rate 298644 # Simulator op (including micro ops) rate (op/s) +host_seconds 296.13 # Real time elapsed on the host +host_tick_rate 197335322 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 88438073 # Number of instructions simulated +sim_ops 88438073 # Number of ops (including micro ops) simulated +sim_seconds 0.058437 # Number of seconds simulated +sim_ticks 58437370000 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 63.309910 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 6368851 # Number of BTB hits +system.cpu.branchPred.BTBLookups 10059801 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 72966 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 375118 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 9451361 # Number of conditional branches predicted +system.cpu.branchPred.lookups 14600308 # Number of BP lookups +system.cpu.branchPred.usedRAS 1701571 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 88438073 # Number of instructions committed +system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed +system.cpu.cpi 1.321543 # CPI: cycles per instruction +system.cpu.dcache.ReadReq_accesses::cpu.inst 20357517 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20357517 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49316.405682 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49316.405682 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39545.722557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39545.722557 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 20268112 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20268112 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4409133250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4409133250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004392 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004392 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 89405 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89405 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28095 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28095 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2424548250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2424548250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61310 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61310 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70753.026587 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70753.026587 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69179.575454 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69179.575454 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 14333276 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333276 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 19817993500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19817993500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019167 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019167 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 280101 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280101 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136536 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136536 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9931765750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9931765750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143565 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143565 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 34970894 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34970894 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 65566.260764 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65566.260764 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60311.477730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60311.477730 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 34601388 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34601388 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 24227126750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24227126750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.010566 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010566 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 369506 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369506 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 164631 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164631 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12356314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12356314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005858 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005858 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 204875 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204875 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 34970894 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34970894 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 65566.260764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65566.260764 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60311.477730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60311.477730 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 34601388 # number of overall hits +system.cpu.dcache.overall_hits::total 34601388 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 24227126750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24227126750 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.010566 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010566 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 369506 # number of overall misses +system.cpu.dcache.overall_misses::total 369506 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 164631 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164631 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12356314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12356314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005858 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005858 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 204875 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204875 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 730 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3314 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 168.890240 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 70146663 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.465989 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.994010 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994010 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 200779 # number of replacements +system.cpu.dcache.tags.sampled_refs 204875 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 70146663 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 4071.465989 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34601388 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 644810250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 168548 # number of writebacks +system.cpu.dcache.writebacks::total 168548 # number of writebacks +system.cpu.discardedOps 1195680 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dtb.data_accesses 35330623 # DTB accesses +system.cpu.dtb.data_acv 9 # DTB access violations +system.cpu.dtb.data_hits 35224185 # DTB hits +system.cpu.dtb.data_misses 106438 # DTB misses +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.read_accesses 20656247 # DTB read accesses +system.cpu.dtb.read_acv 9 # DTB read access violations +system.cpu.dtb.read_hits 20558934 # DTB read hits +system.cpu.dtb.read_misses 97313 # DTB read misses +system.cpu.dtb.write_accesses 14674376 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 14665251 # DTB write hits +system.cpu.dtb.write_misses 9125 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 25515682 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25515682 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16238.011767 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16238.011767 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14217.821664 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14217.821664 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 25361176 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25361176 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2508870246 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2508870246 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006055 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006055 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 154506 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 154506 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2196738754 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2196738754 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006055 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154506 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 154506 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 25515682 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25515682 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16238.011767 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16238.011767 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14217.821664 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14217.821664 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 25361176 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25361176 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 2508870246 # number of demand (read+write) miss cycles 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+system.cpu.icache.overall_mshr_misses::total 154506 # number of overall MSHR misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 164.144694 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 51185869 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1934.490309 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.944575 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.944575 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 152457 # number of replacements +system.cpu.icache.tags.sampled_refs 154505 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 51185869 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 1934.490309 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25361176 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 41486335250 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 25710116 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.756691 # IPC: instructions per cycle +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.fetch_accesses 25520848 # ITB accesses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_hits 25515682 # ITB hits +system.cpu.itb.fetch_misses 5166 # ITB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143566 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143566 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73817.546091 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73817.546091 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60944.031219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60944.031219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 12685 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12685 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9661314250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9661314250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911643 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911643 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 130881 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130881 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7976415750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7976415750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911643 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911643 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 130881 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 215815 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 215815 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72877.172362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72877.172362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60213.094339 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60213.094339 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 180082 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 180082 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2604120000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2604120000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.165572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 35733 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35733 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2151594500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2151594500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35733 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35733 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 168548 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168548 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 168548 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168548 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 359381 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 359381 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73615.868114 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73615.868114 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60787.270277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60787.270277 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 192767 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 192767 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 12265434250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12265434250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463614 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.463614 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 166614 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166614 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10128010250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10128010250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463614 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.463614 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 166614 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166614 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 359381 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 359381 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73615.868114 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73615.868114 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60787.270277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60787.270277 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 192767 # number of overall hits +system.cpu.l2cache.overall_hits::total 192767 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 12265434250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12265434250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463614 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.463614 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 166614 # number of overall misses +system.cpu.l2cache.overall_misses::total 166614 # number of overall misses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10128010250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10128010250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463614 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.463614 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 166614 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166614 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 993 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12007 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18840 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 113 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 1.331233 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 4531761 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 26227.699402 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4243.729621 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.800406 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129508 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.929914 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 132687 # number of replacements +system.cpu.l2cache.tags.sampled_refs 164763 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 4531761 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 30471.429023 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 219338 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 114047 # number of writebacks +system.cpu.l2cache.writebacks::total 114047 # number of writebacks +system.cpu.numCycles 116874740 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 91164624 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 33787392 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 309011 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887309 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 432512500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 233318246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 343226000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 578181256 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9888320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 33787392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 215815 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 215814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168548 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143566 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143566 # Transaction distribution +system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 17962240 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447273 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 1301422000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1600112750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 307375914 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962240 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17962240 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 35732 # Transaction distribution +system.membus.trans_dist::ReadResp 35732 # Transaction distribution +system.membus.trans_dist::Writeback 114047 # Transaction distribution +system.membus.trans_dist::ReadExReq 130881 # Transaction distribution +system.membus.trans_dist::ReadExResp 130881 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 208214.01 # Average gap between requests +system.physmem.avgMemAccLat 30471.23 # Average memory access latency per DRAM burst +system.physmem.avgQLat 11721.23 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 182.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 182.47 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrBW 124.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 124.90 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 24.17 # Average write queue length when enqueuing +system.physmem.busUtil 2.40 # Data bus utilization in percentage +system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 8825038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8825038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 182472825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 182472825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 124903089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 182472825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 307375914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 124903089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 124903089 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 54430 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.948631 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.734417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.314792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19369 35.59% 35.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11718 21.53% 57.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5622 10.33% 67.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3646 6.70% 74.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2769 5.09% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2059 3.78% 83.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1651 3.03% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1489 2.74% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6107 11.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54430 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 10662720 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 10663232 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7296960 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 7299008 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 515712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 515712 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 10663232 # Number of bytes read from this memory +system.physmem.bytes_read::total 10663232 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 7299008 # Number of bytes written to this memory +system.physmem.bytes_written::total 7299008 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 31940805250 # Time in different power states +system.physmem.memoryStateTime::REF 1951300000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 24543978500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 166613 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166613 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114047 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114047 # Number of write requests responded to by this memory +system.physmem.pageHitRate 80.59 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 10468 # Per bank write bursts +system.physmem.perBankRdBursts::1 10509 # Per bank write bursts +system.physmem.perBankRdBursts::2 10311 # Per bank write bursts +system.physmem.perBankRdBursts::3 10091 # Per bank write bursts +system.physmem.perBankRdBursts::4 10432 # Per bank write bursts +system.physmem.perBankRdBursts::5 10432 # Per bank write bursts +system.physmem.perBankRdBursts::6 9848 # Per bank write bursts +system.physmem.perBankRdBursts::7 10303 # Per bank write bursts +system.physmem.perBankRdBursts::8 10590 # Per bank write bursts +system.physmem.perBankRdBursts::9 10643 # Per bank write bursts +system.physmem.perBankRdBursts::10 10591 # Per bank write bursts +system.physmem.perBankRdBursts::11 10256 # Per bank write bursts +system.physmem.perBankRdBursts::12 10303 # Per bank write bursts +system.physmem.perBankRdBursts::13 10654 # Per bank write bursts +system.physmem.perBankRdBursts::14 10527 # Per bank write bursts +system.physmem.perBankRdBursts::15 10647 # Per bank write bursts +system.physmem.perBankWrBursts::0 7087 # Per bank write bursts +system.physmem.perBankWrBursts::1 7261 # Per bank write bursts +system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::4 7126 # Per bank write bursts +system.physmem.perBankWrBursts::5 7180 # Per bank write bursts +system.physmem.perBankWrBursts::6 6771 # Per bank write bursts +system.physmem.perBankWrBursts::7 7085 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::9 6938 # Per bank write bursts +system.physmem.perBankWrBursts::10 7096 # Per bank write bursts +system.physmem.perBankWrBursts::11 6991 # Per bank write bursts +system.physmem.perBankWrBursts::12 6965 # Per bank write bursts +system.physmem.perBankWrBursts::13 7289 # Per bank write bursts +system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 7018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.736820 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.923098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7017 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7018 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 164979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 166613 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 166613 # Read request sizes (log2) +system.physmem.readReqs 166613 # Number of read requests accepted +system.physmem.readRowHitRate 86.96 # Row buffer hit rate for reads +system.physmem.readRowHits 144887 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 833025000 # Total ticks spent in databus transfers +system.physmem.totGap 58437343500 # Total gap between requests +system.physmem.totMemAccLat 5076659000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1952815250 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 7018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.246082 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.230651 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.740530 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6255 89.13% 89.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.20% 89.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 591 8.42% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 122 1.74% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 26 0.37% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7018 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7074 # What write queue length does an incoming req see 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Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 114047 # Write request sizes (log2) +system.physmem.writeReqs 114047 # Number of write requests accepted +system.physmem.writeRowHitRate 71.29 # Row buffer hit rate for writes +system.physmem.writeRowHits 81299 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini new file mode 100644 index 000000000..4cb5c8ea2 --- /dev/null +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini @@ -0,0 +1,816 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 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+[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 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+eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=vortex lendian.raw +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/vortex +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr new file mode 100644 index 000000000..1a4f96712 --- /dev/null +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr @@ -0,0 +1 @@ +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout new file mode 100644 index 000000000..0b495a4c8 --- /dev/null +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout @@ -0,0 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 17:09:29 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0xcee8df0 +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Exiting @ tick 64581408500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt new file mode 100644 index 000000000..ce74a2918 --- /dev/null +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,729 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 64366581500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 178791 # Simulator instruction rate (inst/s) +host_mem_usage 302756 # Number of bytes of host memory used +host_op_rate 253719 # Simulator op (including micro ops) rate (op/s) +host_seconds 396.64 # Real time elapsed on the host +host_tick_rate 162280857 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 70915127 # Number of instructions simulated +sim_ops 100634375 # Number of ops (including micro ops) simulated +sim_seconds 0.064367 # Number of seconds simulated +sim_ticks 64366581500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 66.765050 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 7446252 # Number of BTB hits +system.cpu.branchPred.BTBLookups 11152919 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 511 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 417499 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 12871662 # Number of conditional branches predicted +system.cpu.branchPred.lookups 16883830 # Number of BP lookups +system.cpu.branchPred.usedRAS 1514690 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 70915127 # Number of instructions committed +system.cpu.committedOps 100634375 # Number of ops (including micro ops) committed +system.cpu.cpi 1.815313 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses::cpu.inst 27634745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27634745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38199.338598 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38199.338598 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.609683 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.609683 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 27577955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27577955 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2169340439 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2169340439 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002055 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002055 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 56790 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56790 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2862 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2862 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2001786311 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2001786311 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.001951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53928 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53928 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73771.399808 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73771.399808 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.202050 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.202050 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 19642294 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642294 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15315459000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15315459000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 207607 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207607 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 100574 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100574 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7591658250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7591658250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107033 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107033 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 47484646 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47484646 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.854128 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66130.854128 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59601.049701 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59601.049701 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 47220249 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47220249 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 17484799439 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17484799439 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.005568 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005568 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 264397 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 264397 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 103436 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 103436 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593444561 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9593444561 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003390 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 160961 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 160961 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 47484646 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47484646 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.854128 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66130.854128 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59601.049701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59601.049701 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 47220249 # number of overall hits +system.cpu.dcache.overall_hits::total 47220249 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 17484799439 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17484799439 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.005568 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005568 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 264397 # number of overall misses +system.cpu.dcache.overall_misses::total 264397 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 103436 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 103436 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593444561 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9593444561 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003390 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 160961 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160961 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 711 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3335 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 293.562335 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 95193929 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 4070.633737 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993807 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993807 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 156865 # number of replacements +system.cpu.dcache.tags.sampled_refs 160961 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 95193929 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 4070.633737 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 47252087 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 802561250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 128565 # number of writebacks +system.cpu.dcache.writebacks::total 128565 # number of writebacks +system.cpu.discardedOps 2952330 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 27472867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27472867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19971.672117 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19971.672117 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17929.897070 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17929.897070 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 27427302 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27427302 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 910009240 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 910009240 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001659 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001659 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 45565 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 45565 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 816975760 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 816975760 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001659 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45565 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 45565 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 27472867 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27472867 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19971.672117 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19971.672117 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17929.897070 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17929.897070 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 27427302 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27427302 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 910009240 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 910009240 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::cpu.inst 0.001659 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001659 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 45565 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 45565 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 816975760 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 816975760 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001659 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::cpu.inst 45565 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 45565 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses::cpu.inst 27472867 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27472867 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19971.672117 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19971.672117 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17929.897070 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17929.897070 # average overall mshr miss latency +system.cpu.icache.overall_hits::cpu.inst 27427302 # number of overall hits +system.cpu.icache.overall_hits::total 27427302 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 910009240 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 910009240 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.001659 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001659 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 45565 # number of overall misses +system.cpu.icache.overall_misses::total 45565 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 816975760 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 816975760 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001659 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::cpu.inst 45565 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 45565 # number of overall MSHR misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 727 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1194 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 601.951146 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 54991298 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1864.297147 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 43522 # number of replacements +system.cpu.icache.tags.sampled_refs 45564 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 54991298 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 1864.297147 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27427302 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 19565206 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.550869 # IPC: instructions per cycle +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107033 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107033 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.821477 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.821477 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.466837 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.466837 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 4766 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4766 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7436940250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7436940250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955472 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955472 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 102267 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102267 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6118068750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6118068750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955472 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955472 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102267 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102267 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 99493 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 99493 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74187.493019 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74187.493019 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61477.049578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61477.049578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 72636 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 72636 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1992453500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1992453500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269939 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.269939 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 26857 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26857 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1646724250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1646724250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269225 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269225 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26786 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26786 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 128565 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128565 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 128565 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128565 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 206526 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 206526 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73025.880162 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73025.880162 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60167.473829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60167.473829 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 77402 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 77402 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 9429393750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9429393750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.625219 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.625219 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 129124 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 129124 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7764793000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7764793000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.624875 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 129053 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 129053 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 206526 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 206526 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73025.880162 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73025.880162 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60167.473829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60167.473829 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 77402 # number of overall hits +system.cpu.l2cache.overall_hits::total 77402 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 9429393750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9429393750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.625219 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.625219 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 129124 # number of overall misses +system.cpu.l2cache.overall_misses::total 129124 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7764793000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7764793000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.624875 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 129053 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 129053 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1012 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9483 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19900 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 597 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 0.794453 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 2914793 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 26739.141291 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3288.835051 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.816014 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.100367 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.916381 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31121 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 95911 # number of replacements +system.cpu.l2cache.tags.sampled_refs 127032 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 2914793 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 30027.976342 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 100921 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 83957 # number of writebacks +system.cpu.l2cache.writebacks::total 83957 # number of writebacks +system.cpu.numCycles 128733163 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 109167957 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 21445760 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91129 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 450487 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 541616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 296110500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 69298740 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 269478939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 333181591 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2916096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18529664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 21445760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 99493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 99492 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 13632576 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 975516000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1243562500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 211795868 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13632576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13632576 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 26785 # Transaction distribution +system.membus.trans_dist::ReadResp 26785 # Transaction distribution +system.membus.trans_dist::Writeback 83957 # Transaction distribution +system.membus.trans_dist::ReadExReq 102267 # Transaction distribution +system.membus.trans_dist::ReadExResp 102267 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 302177.61 # Average gap between requests +system.physmem.avgMemAccLat 30050.93 # Average memory access latency per DRAM burst +system.physmem.avgQLat 11300.93 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 128.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 128.32 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrBW 83.45 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 83.48 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 23.63 # Average write queue length when enqueuing +system.physmem.busUtil 1.65 # Data bus utilization in percentage +system.physmem.busUtilRead 1.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.65 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 5060017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5060017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 128317021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 128317021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 83478847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 128317021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 211795868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 83478847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 83478847 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 38820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.055332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 212.915649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.657943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12445 32.06% 32.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8253 21.26% 53.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4125 10.63% 63.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2766 7.13% 71.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2568 6.62% 77.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1673 4.31% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1314 3.38% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1198 3.09% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4478 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38820 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 8258880 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 8259328 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371584 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 5373248 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 325696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 325696 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 8259328 # Number of bytes read from this memory +system.physmem.bytes_read::total 8259328 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 5373248 # Number of bytes written to this memory +system.physmem.bytes_written::total 5373248 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 37439884750 # Time in different power states +system.physmem.memoryStateTime::REF 2149160000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 24772371500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 129052 # Number of read requests responded to by this memory +system.physmem.num_reads::total 129052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83957 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83957 # Number of write requests responded to by this memory +system.physmem.pageHitRate 81.76 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 8196 # Per bank write bursts +system.physmem.perBankRdBursts::1 8381 # Per bank write bursts +system.physmem.perBankRdBursts::2 8249 # Per bank write bursts +system.physmem.perBankRdBursts::3 8185 # Per bank write bursts +system.physmem.perBankRdBursts::4 8327 # Per bank write bursts +system.physmem.perBankRdBursts::5 8459 # Per bank write bursts +system.physmem.perBankRdBursts::6 8094 # Per bank write bursts +system.physmem.perBankRdBursts::7 7981 # Per bank write bursts +system.physmem.perBankRdBursts::8 8076 # Per bank write bursts +system.physmem.perBankRdBursts::9 7644 # Per bank write bursts +system.physmem.perBankRdBursts::10 7831 # Per bank write bursts +system.physmem.perBankRdBursts::11 7843 # Per bank write bursts +system.physmem.perBankRdBursts::12 7891 # Per bank write bursts +system.physmem.perBankRdBursts::13 7884 # Per bank write bursts +system.physmem.perBankRdBursts::14 7977 # Per bank write bursts +system.physmem.perBankRdBursts::15 8027 # Per bank write bursts +system.physmem.perBankWrBursts::0 5181 # Per bank write bursts +system.physmem.perBankWrBursts::1 5375 # Per bank write bursts +system.physmem.perBankWrBursts::2 5284 # Per bank write bursts +system.physmem.perBankWrBursts::3 5155 # Per bank write bursts +system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::5 5517 # Per bank write bursts +system.physmem.perBankWrBursts::6 5201 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts +system.physmem.perBankWrBursts::8 5034 # Per bank write bursts +system.physmem.perBankWrBursts::9 5087 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::11 5146 # Per bank write bursts +system.physmem.perBankWrBursts::12 5344 # Per bank write bursts +system.physmem.perBankWrBursts::13 5363 # Per bank write bursts +system.physmem.perBankWrBursts::14 5451 # Per bank write bursts +system.physmem.perBankWrBursts::15 5227 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.028123 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 359.400532 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 128466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 129052 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 129052 # Read request sizes (log2) +system.physmem.readReqs 129052 # Number of read requests accepted +system.physmem.readRowHitRate 86.89 # Row buffer hit rate for reads +system.physmem.readRowHits 112129 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 645225000 # Total ticks spent in databus transfers +system.physmem.totGap 64366550000 # Total gap between requests +system.physmem.totMemAccLat 3877921750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1458328000 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 5155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.280116 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.263015 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.779231 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4514 87.57% 87.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.14% 87.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 501 9.72% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 114 2.21% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 12 0.23% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5155 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 83957 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 83957 # Write request sizes (log2) +system.physmem.writeReqs 83957 # Number of write requests accepted +system.physmem.writeRowHitRate 73.87 # Row buffer hit rate for writes +system.physmem.writeRowHits 62016 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- |