diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
| commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
| tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/long/se/50.vortex/ref | |
| parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
| download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz | |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/long/se/50.vortex/ref')
4 files changed, 2784 insertions, 2704 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 2126b1202..7a3a9c70d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.059474 # Number of seconds simulated -sim_ticks 59473862000 # Number of ticks simulated -final_tick 59473862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059447 # Number of seconds simulated +sim_ticks 59447065000 # Number of ticks simulated +final_tick 59447065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 330532 # Simulator instruction rate (inst/s) -host_op_rate 330532 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 222279677 # Simulator tick rate (ticks/s) -host_mem_usage 308876 # Number of bytes of host memory used -host_seconds 267.56 # Real time elapsed on the host +host_inst_rate 412945 # Simulator instruction rate (inst/s) +host_op_rate 412945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 277576735 # Simulator tick rate (ticks/s) +host_mem_usage 261724 # Number of bytes of host memory used +host_seconds 214.16 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 432448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10149376 # Number of bytes read from this memory -system.physmem.bytes_read::total 10581824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 432448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 432448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7325760 # Number of bytes written to this memory -system.physmem.bytes_written::total 7325760 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6757 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158584 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165341 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114465 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114465 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7271228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 170652715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 177923942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7271228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7271228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 123176127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 123176127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 123176127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7271228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 170652715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 301100070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165341 # Number of read requests accepted -system.physmem.writeReqs 114465 # Number of write requests accepted -system.physmem.readBursts 165341 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114465 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10581376 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 432832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10149568 # Number of bytes read from this memory +system.physmem.bytes_read::total 10582400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 432832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 432832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7326016 # Number of bytes written to this memory +system.physmem.bytes_written::total 7326016 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6763 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158587 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165350 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114469 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114469 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7280965 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 170732870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 178013835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7280965 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7280965 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 123235958 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 123235958 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 123235958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7280965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 170732870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 301249793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165350 # Number of read requests accepted +system.physmem.writeReqs 114469 # Number of write requests accepted +system.physmem.readBursts 165350 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114469 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10581952 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7323904 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10581824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7325760 # Total written bytes from the system interface side +system.physmem.bytesWritten 7323968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10582400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7326016 # Total written bytes from the system interface side system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10312 # Per bank write bursts -system.physmem.perBankRdBursts::1 10359 # Per bank write bursts +system.physmem.perBankRdBursts::0 10315 # Per bank write bursts +system.physmem.perBankRdBursts::1 10360 # Per bank write bursts system.physmem.perBankRdBursts::2 10206 # Per bank write bursts system.physmem.perBankRdBursts::3 10057 # Per bank write bursts system.physmem.perBankRdBursts::4 10348 # Per bank write bursts -system.physmem.perBankRdBursts::5 10339 # Per bank write bursts -system.physmem.perBankRdBursts::6 9776 # Per bank write bursts +system.physmem.perBankRdBursts::5 10343 # Per bank write bursts +system.physmem.perBankRdBursts::6 9775 # Per bank write bursts system.physmem.perBankRdBursts::7 10207 # Per bank write bursts -system.physmem.perBankRdBursts::8 10534 # Per bank write bursts -system.physmem.perBankRdBursts::9 10607 # Per bank write bursts -system.physmem.perBankRdBursts::10 10498 # Per bank write bursts +system.physmem.perBankRdBursts::8 10536 # Per bank write bursts +system.physmem.perBankRdBursts::9 10606 # Per bank write bursts +system.physmem.perBankRdBursts::10 10500 # Per bank write bursts system.physmem.perBankRdBursts::11 10228 # Per bank write bursts -system.physmem.perBankRdBursts::12 10274 # Per bank write bursts -system.physmem.perBankRdBursts::13 10561 # Per bank write bursts -system.physmem.perBankRdBursts::14 10464 # Per bank write bursts -system.physmem.perBankRdBursts::15 10564 # Per bank write bursts +system.physmem.perBankRdBursts::12 10273 # Per bank write bursts +system.physmem.perBankRdBursts::13 10559 # Per bank write bursts +system.physmem.perBankRdBursts::14 10465 # Per bank write bursts +system.physmem.perBankRdBursts::15 10565 # Per bank write bursts system.physmem.perBankWrBursts::0 7163 # Per bank write bursts system.physmem.perBankWrBursts::1 7274 # Per bank write bursts system.physmem.perBankWrBursts::2 7296 # Per bank write bursts system.physmem.perBankWrBursts::3 7002 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7187 # Per bank write bursts +system.physmem.perBankWrBursts::5 7186 # Per bank write bursts system.physmem.perBankWrBursts::6 6833 # Per bank write bursts system.physmem.perBankWrBursts::7 7099 # Per bank write bursts -system.physmem.perBankWrBursts::8 7225 # Per bank write bursts -system.physmem.perBankWrBursts::9 7000 # Per bank write bursts -system.physmem.perBankWrBursts::10 7115 # Per bank write bursts +system.physmem.perBankWrBursts::8 7226 # Per bank write bursts +system.physmem.perBankWrBursts::9 6999 # Per bank write bursts +system.physmem.perBankWrBursts::10 7117 # Per bank write bursts system.physmem.perBankWrBursts::11 7034 # Per bank write bursts system.physmem.perBankWrBursts::12 6992 # Per bank write bursts system.physmem.perBankWrBursts::13 7299 # Per bank write bursts -system.physmem.perBankWrBursts::14 7308 # Per bank write bursts -system.physmem.perBankWrBursts::15 7482 # Per bank write bursts +system.physmem.perBankWrBursts::14 7307 # Per bank write bursts +system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 59473838000 # Total gap between requests +system.physmem.totGap 59447041000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165341 # Read request sizes (log2) +system.physmem.readPktSize::6 165350 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114465 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163748 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114469 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,120 +193,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.237051 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.297949 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.344141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19597 35.82% 35.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11811 21.59% 57.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5572 10.18% 67.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3684 6.73% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2893 5.29% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2049 3.74% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1621 2.96% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1502 2.75% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5985 10.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54714 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7041 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.479761 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.363256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7038 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.365172 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.328231 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.549756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19615 35.86% 35.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11787 21.55% 57.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5586 10.21% 67.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3666 6.70% 74.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2860 5.23% 79.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2087 3.82% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1603 2.93% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1458 2.67% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6030 11.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54692 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.476853 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.379045 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7039 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7041 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7041 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.252805 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.237164 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.745060 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6251 88.78% 88.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 16 0.23% 89.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 606 8.61% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 134 1.90% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 28 0.40% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7041 # Writes before turning the bus around for reads -system.physmem.totQLat 1980163000 # Total ticks spent queuing -system.physmem.totMemAccLat 5080175500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826670000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11976.74 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.250639 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.234557 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.758479 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6275 89.11% 89.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 11 0.16% 89.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 574 8.15% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 150 2.13% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 18 0.26% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 9 0.13% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads +system.physmem.totQLat 1988923000 # Total ticks spent queuing +system.physmem.totMemAccLat 5089104250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826715000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12029.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30726.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 177.92 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 123.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 177.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 123.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30779.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 178.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 123.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 178.01 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 123.24 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.35 # Data bus utilization in percentage system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing -system.physmem.readRowHits 143867 # Number of row buffer hits during reads -system.physmem.writeRowHits 81182 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.92 # Row buffer hit rate for writes -system.physmem.avgGap 212553.83 # Average gap between requests -system.physmem.pageHitRate 80.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199175760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108677250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 636448800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 369204480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3884381280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12421725570 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24786732000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42406345140 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.051581 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41087166750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1985880000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.77 # Average write queue length when enqueuing +system.physmem.readRowHits 143858 # Number of row buffer hits during reads +system.physmem.writeRowHits 81218 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.95 # Row buffer hit rate for writes +system.physmem.avgGap 212448.19 # Average gap between requests +system.physmem.pageHitRate 80.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199274040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108730875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 636347400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 369068400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3882347040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12411408285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24777095250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42384271290 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.053838 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 41070575000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1984840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16398707250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16385091250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214341120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116952000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 652938000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 372237120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3884381280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13062187260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24224923500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42527960280 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.096508 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40147172500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1985880000 # Time in different power states +system.physmem_1.actEnergy 213940440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116733375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 652860000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 372152880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3882347040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13085746785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24185582250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42509362770 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.158080 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40083292000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1984840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17338598750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17372590500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14666171 # Number of BP lookups -system.cpu.branchPred.condPredicted 9489023 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386095 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9897790 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6385525 # Number of BTB hits +system.cpu.branchPred.lookups 14660042 # Number of BP lookups +system.cpu.branchPred.condPredicted 9484785 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 381684 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9866507 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6346497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.514654 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1708105 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84877 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.323646 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1708762 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84355 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37443 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31778 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5665 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 7605 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20569903 # DTB read hits -system.cpu.dtb.read_misses 97320 # DTB read misses -system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20667223 # DTB read accesses -system.cpu.dtb.write_hits 14665328 # DTB write hits -system.cpu.dtb.write_misses 9407 # DTB write misses +system.cpu.dtb.read_hits 20565775 # DTB read hits +system.cpu.dtb.read_misses 97355 # DTB read misses +system.cpu.dtb.read_acv 8 # DTB read access violations +system.cpu.dtb.read_accesses 20663130 # DTB read accesses +system.cpu.dtb.write_hits 14665271 # DTB write hits +system.cpu.dtb.write_misses 9409 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674735 # DTB write accesses -system.cpu.dtb.data_hits 35235231 # DTB hits -system.cpu.dtb.data_misses 106727 # DTB misses -system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35341958 # DTB accesses -system.cpu.itb.fetch_hits 25606544 # ITB hits -system.cpu.itb.fetch_misses 5228 # ITB misses +system.cpu.dtb.write_accesses 14674680 # DTB write accesses +system.cpu.dtb.data_hits 35231046 # DTB hits +system.cpu.dtb.data_misses 106764 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 35337810 # DTB accesses +system.cpu.itb.fetch_hits 25585531 # ITB hits +system.cpu.itb.fetch_misses 5208 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25611772 # ITB accesses +system.cpu.itb.fetch_accesses 25590739 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -320,81 +326,116 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 118947724 # number of cpu cycles simulated +system.cpu.numCycles 118894130 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1106117 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1097381 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.344983 # CPI: cycles per instruction -system.cpu.ipc 0.743504 # IPC: instructions per cycle -system.cpu.tickCycles 91473408 # Number of cycles that the object actually ticked -system.cpu.idleCycles 27474316 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.344377 # CPI: cycles per instruction +system.cpu.ipc 0.743839 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction +system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction +system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 60.14% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction +system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::MemRead 20366786 23.03% 83.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 88438073 # Class of committed instruction +system.cpu.tickCycles 91425505 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27468625 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 200766 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.683377 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616213 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.673886 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34612040 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 204862 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.973324 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 687575500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.683377 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993819 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993819 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 168.952954 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 687650500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.673886 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993817 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993817 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3361 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3360 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176360 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176360 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20282952 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20282952 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333261 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333261 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34616213 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616213 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34616213 # number of overall hits -system.cpu.dcache.overall_hits::total 34616213 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89420 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89420 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280116 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280116 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369536 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369536 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369536 # number of overall misses -system.cpu.dcache.overall_misses::total 369536 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4768019500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4768019500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21708920500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21708920500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26476940000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26476940000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26476940000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26476940000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372372 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372372 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70168000 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70168000 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20278781 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20278781 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333259 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333259 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34612040 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34612040 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34612040 # number of overall hits +system.cpu.dcache.overall_hits::total 34612040 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89411 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89411 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280118 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280118 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369529 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369529 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369529 # number of overall misses +system.cpu.dcache.overall_misses::total 369529 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4770299000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4770299000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21700228000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21700228000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26470527000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26470527000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26470527000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26470527000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20368192 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20368192 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34985749 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34985749 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34985749 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34985749 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010562 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010562 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010562 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010562 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53321.622679 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53321.622679 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77499.751889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77499.751889 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71649.149203 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71649.149203 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71649.149203 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71649.149203 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 34981569 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34981569 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34981569 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34981569 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019169 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019169 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010564 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010564 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010564 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010564 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53352.484594 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53352.484594 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77468.166987 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77468.166987 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71633.151931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71633.151931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71633.151931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71633.151931 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,103 +444,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168423 # number of writebacks -system.cpu.dcache.writebacks::total 168423 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28115 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28115 # 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number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 204862 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 204862 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204862 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204862 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2680071500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2680071500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10970928000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10970928000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13650999500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13650999500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13650999500 # 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Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1932.301021 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943506 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943506 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 152872 # number of replacements +system.cpu.icache.tags.tagsinuse 1932.382407 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25430610 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 154920 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 164.153176 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42235793500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1932.382407 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943546 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943546 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15009.321842 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15009.321842 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 152872 # number of writebacks +system.cpu.icache.writebacks::total 152872 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154921 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 154921 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 154921 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 154921 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 154921 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 154921 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2328819000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2328819000 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81061.194066 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,123 +686,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114465 # number of writebacks -system.cpu.l2cache.writebacks::total 114465 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 114469 # number of writebacks +system.cpu.l2cache.writebacks::total 114469 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 115 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 115 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130883 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130883 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6758 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6758 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27701 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27701 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6758 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158584 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165342 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6758 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158584 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165342 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9313621000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9313621000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 469343000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 469343000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1957795000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1957795000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 469343000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11271416000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11740759000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 469343000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11271416000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11740759000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6764 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6764 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27704 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27704 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158587 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165351 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158587 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165351 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9318048000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9318048000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 472956000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 472956000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1959045500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1959045500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472956000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11277093500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11750049500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472956000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11277093500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11750049500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911708 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911708 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043627 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451863 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451863 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.459581 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.459581 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71159.898535 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71159.898535 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69449.985203 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69449.985203 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70675.968377 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70675.968377 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69449.985203 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71075.366998 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71008.932999 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69449.985203 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71075.366998 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71008.932999 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911670 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911670 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043661 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451956 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451956 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774116 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459585 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774116 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459585 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71193.722638 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71193.722638 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69922.531047 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69922.531047 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70713.452931 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70713.452931 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 713389 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 353622 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 713421 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 353638 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4036 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4036 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4037 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4037 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 216208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 282888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 152856 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 154905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61304 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462665 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 216218 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 282893 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 152872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51255 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143564 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143564 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 154921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61298 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462713 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1073155 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19696640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23890240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43586880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133370 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 493137 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008184 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.090096 # Request fanout histogram +system.cpu.toL2Bus.pkt_count::total 1073203 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19698688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23890304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43588992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133382 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 493165 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.090105 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 489101 99.18% 99.18% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4036 0.82% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 489128 99.18% 99.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4037 0.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 493137 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 677973500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 493165 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 678006500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 232357497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 232381497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307299487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307297491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 34458 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114465 # Transaction distribution -system.membus.trans_dist::CleanEvict 14983 # Transaction distribution +system.membus.trans_dist::ReadResp 34467 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114469 # Transaction distribution +system.membus.trans_dist::CleanEvict 14990 # Transaction distribution system.membus.trans_dist::ReadExReq 130883 # Transaction distribution system.membus.trans_dist::ReadExResp 130883 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34458 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460130 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17907584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17907584 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 34467 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460159 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460159 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17908416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17908416 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 294789 # Request fanout histogram +system.membus.snoop_fanout::samples 294809 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294789 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294809 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294789 # Request fanout histogram -system.membus.reqLayer0.occupancy 822943500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294809 # Request fanout histogram +system.membus.reqLayer0.occupancy 822950500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 872924250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 872961750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 5beee1623..8a6383ef9 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022297 # Number of seconds simulated -sim_ticks 22296591500 # Number of ticks simulated -final_tick 22296591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022275 # Number of seconds simulated +sim_ticks 22275010500 # Number of ticks simulated +final_tick 22275010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210659 # Simulator instruction rate (inst/s) -host_op_rate 210659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59013272 # Simulator tick rate (ticks/s) -host_mem_usage 309644 # Number of bytes of host memory used -host_seconds 377.82 # Real time elapsed on the host +host_inst_rate 279038 # Simulator instruction rate (inst/s) +host_op_rate 279038 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78093188 # Simulator tick rate (ticks/s) +host_mem_usage 263768 # Number of bytes of host memory used +host_seconds 285.24 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -18,71 +18,71 @@ system.physmem.bytes_read::cpu.data 10153216 # Nu system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 409984 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 409984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7322432 # Number of bytes written to this memory -system.physmem.bytes_written::total 7322432 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7322816 # Number of bytes written to this memory +system.physmem.bytes_written::total 7322816 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 6406 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158644 # Number of read requests responded to by this memory system.physmem.num_reads::total 165050 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114413 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114413 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18387743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455370768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 473758511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18387743 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18387743 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 328410376 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 328410376 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 328410376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18387743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455370768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 802168888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 114419 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114419 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18405558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455811951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 474217509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18405558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18405558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 328745793 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 328745793 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 328745793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18405558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455811951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 802963303 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165050 # Number of read requests accepted -system.physmem.writeReqs 114413 # Number of write requests accepted +system.physmem.writeReqs 114419 # Number of write requests accepted system.physmem.readBursts 165050 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114413 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 114419 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 10562816 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7320896 # Total number of bytes written to DRAM +system.physmem.bytesWritten 7320960 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10563200 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7322432 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 7322816 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10292 # Per bank write bursts -system.physmem.perBankRdBursts::1 10329 # Per bank write bursts -system.physmem.perBankRdBursts::2 10209 # Per bank write bursts -system.physmem.perBankRdBursts::3 10020 # Per bank write bursts -system.physmem.perBankRdBursts::4 10344 # Per bank write bursts -system.physmem.perBankRdBursts::5 10314 # Per bank write bursts -system.physmem.perBankRdBursts::6 9779 # Per bank write bursts -system.physmem.perBankRdBursts::7 10195 # Per bank write bursts -system.physmem.perBankRdBursts::8 10531 # Per bank write bursts +system.physmem.perBankRdBursts::0 10290 # Per bank write bursts +system.physmem.perBankRdBursts::1 10331 # Per bank write bursts +system.physmem.perBankRdBursts::2 10206 # Per bank write bursts +system.physmem.perBankRdBursts::3 10021 # Per bank write bursts +system.physmem.perBankRdBursts::4 10343 # Per bank write bursts +system.physmem.perBankRdBursts::5 10313 # Per bank write bursts +system.physmem.perBankRdBursts::6 9783 # Per bank write bursts +system.physmem.perBankRdBursts::7 10190 # Per bank write bursts +system.physmem.perBankRdBursts::8 10528 # Per bank write bursts system.physmem.perBankRdBursts::9 10599 # Per bank write bursts -system.physmem.perBankRdBursts::10 10453 # Per bank write bursts -system.physmem.perBankRdBursts::11 10204 # Per bank write bursts +system.physmem.perBankRdBursts::10 10456 # Per bank write bursts +system.physmem.perBankRdBursts::11 10208 # Per bank write bursts system.physmem.perBankRdBursts::12 10247 # Per bank write bursts -system.physmem.perBankRdBursts::13 10532 # Per bank write bursts -system.physmem.perBankRdBursts::14 10447 # Per bank write bursts -system.physmem.perBankRdBursts::15 10549 # Per bank write bursts +system.physmem.perBankRdBursts::13 10535 # Per bank write bursts +system.physmem.perBankRdBursts::14 10446 # Per bank write bursts +system.physmem.perBankRdBursts::15 10548 # Per bank write bursts system.physmem.perBankWrBursts::0 7163 # Per bank write bursts -system.physmem.perBankWrBursts::1 7267 # Per bank write bursts +system.physmem.perBankWrBursts::1 7268 # Per bank write bursts system.physmem.perBankWrBursts::2 7294 # Per bank write bursts -system.physmem.perBankWrBursts::3 7000 # Per bank write bursts +system.physmem.perBankWrBursts::3 7001 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7180 # Per bank write bursts +system.physmem.perBankWrBursts::5 7177 # Per bank write bursts system.physmem.perBankWrBursts::6 6836 # Per bank write bursts -system.physmem.perBankWrBursts::7 7102 # Per bank write bursts +system.physmem.perBankWrBursts::7 7101 # Per bank write bursts system.physmem.perBankWrBursts::8 7221 # Per bank write bursts -system.physmem.perBankWrBursts::9 7001 # Per bank write bursts -system.physmem.perBankWrBursts::10 7100 # Per bank write bursts -system.physmem.perBankWrBursts::11 7020 # Per bank write bursts -system.physmem.perBankWrBursts::12 6992 # Per bank write bursts -system.physmem.perBankWrBursts::13 7297 # Per bank write bursts +system.physmem.perBankWrBursts::9 7003 # Per bank write bursts +system.physmem.perBankWrBursts::10 7101 # Per bank write bursts +system.physmem.perBankWrBursts::11 7022 # Per bank write bursts +system.physmem.perBankWrBursts::12 6991 # Per bank write bursts +system.physmem.perBankWrBursts::13 7296 # Per bank write bursts system.physmem.perBankWrBursts::14 7307 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22296560500 # Total gap between requests +system.physmem.totGap 22274979500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -96,13 +96,13 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114413 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114419 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -193,124 +193,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52310 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.858612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 200.924906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.625607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18434 35.24% 35.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10645 20.35% 55.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5863 11.21% 66.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2906 5.56% 72.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2975 5.69% 78.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1493 2.85% 80.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2022 3.87% 84.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 988 1.89% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6984 13.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 52304 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.896604 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.837447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.790414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18483 35.34% 35.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10568 20.20% 55.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5879 11.24% 66.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2936 5.61% 72.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2943 5.63% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1490 2.85% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2026 3.87% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 952 1.82% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7027 13.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52304 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.610300 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 338.218951 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6987 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.609728 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 338.236069 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6988 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6990 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.364664 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.334270 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.064891 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6098 87.24% 87.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 26 0.37% 87.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 456 6.52% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 208 2.98% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 103 1.47% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 57 0.82% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.30% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.14% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.11% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.364807 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.334911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.053834 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6086 87.07% 87.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.50% 87.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 455 6.51% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 219 3.13% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 100 1.43% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 53 0.76% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 22 0.31% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.16% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 7 0.10% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6990 # Writes before turning the bus around for reads -system.physmem.totQLat 5731685000 # Total ticks spent queuing -system.physmem.totMemAccLat 8826260000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 5740232250 # Total ticks spent queuing +system.physmem.totMemAccLat 8834807250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 825220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34728.22 # Average queueing delay per DRAM burst +system.physmem.avgQLat 34780.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53478.22 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 473.74 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 328.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 473.76 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 328.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53530.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 474.20 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 328.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 474.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 328.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 6.27 # Data bus utilization in percentage system.physmem.busUtilRead 3.70 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 2.57 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing -system.physmem.readRowHits 145441 # Number of row buffer hits during reads -system.physmem.writeRowHits 81669 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.38 # Row buffer hit rate for writes -system.physmem.avgGap 79783.59 # Average gap between requests +system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing +system.physmem.readRowHits 145488 # Number of row buffer hits during reads +system.physmem.writeRowHits 81629 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.34 # Row buffer hit rate for writes +system.physmem.avgGap 79704.65 # Average gap between requests system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190375920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 103875750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 635356800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 369036000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6553881090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7626357750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16934890590 # Total energy per rank (pJ) -system.physmem_0.averagePower 759.674656 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12601715000 # Time in different power states -system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states +system.physmem_0.actEnergy 190428840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 103904625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 635177400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 368951760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6564184695 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7603330500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16920459420 # Total energy per rank (pJ) +system.physmem_0.averagePower 759.821975 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12566232250 # Time in different power states +system.physmem_0.memoryStateTime::REF 743600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8946212500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8959159250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204815520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111754500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 204618960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111647250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 651565200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371893680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6747677955 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7456388250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 17000102385 # Total energy per rank (pJ) -system.physmem_1.averagePower 762.598381 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12320846000 # Time in different power states -system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states +system.physmem_1.writeEnergy 371861280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6822625545 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7376602500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 16993402335 # Total energy per rank (pJ) +system.physmem_1.averagePower 763.098971 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12188749750 # Time in different power states +system.physmem_1.memoryStateTime::REF 743600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9227273000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9336732250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16493971 # Number of BP lookups -system.cpu.branchPred.condPredicted 10685365 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 327092 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8977635 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7282355 # Number of BTB hits +system.cpu.branchPred.lookups 16474744 # Number of BP lookups +system.cpu.branchPred.condPredicted 10670267 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 324432 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8918177 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7235165 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.116630 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1973286 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2952 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.128296 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1973322 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3328 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 39379 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31470 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7909 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2657 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22518673 # DTB read hits -system.cpu.dtb.read_misses 225961 # DTB read misses -system.cpu.dtb.read_acv 15 # DTB read access violations -system.cpu.dtb.read_accesses 22744634 # DTB read accesses -system.cpu.dtb.write_hits 15824450 # DTB write hits -system.cpu.dtb.write_misses 44763 # DTB write misses +system.cpu.dtb.read_hits 22508484 # DTB read hits +system.cpu.dtb.read_misses 226837 # DTB read misses +system.cpu.dtb.read_acv 16 # DTB read access violations +system.cpu.dtb.read_accesses 22735321 # DTB read accesses +system.cpu.dtb.write_hits 15806842 # DTB write hits +system.cpu.dtb.write_misses 44564 # DTB write misses system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15869213 # DTB write accesses -system.cpu.dtb.data_hits 38343123 # DTB hits -system.cpu.dtb.data_misses 270724 # DTB misses -system.cpu.dtb.data_acv 19 # DTB access violations -system.cpu.dtb.data_accesses 38613847 # DTB accesses -system.cpu.itb.fetch_hits 13750650 # ITB hits -system.cpu.itb.fetch_misses 29320 # ITB misses +system.cpu.dtb.write_accesses 15851406 # DTB write accesses +system.cpu.dtb.data_hits 38315326 # DTB hits +system.cpu.dtb.data_misses 271401 # DTB misses +system.cpu.dtb.data_acv 20 # DTB access violations +system.cpu.dtb.data_accesses 38586727 # DTB accesses +system.cpu.itb.fetch_hits 13727245 # ITB hits +system.cpu.itb.fetch_misses 29559 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13779970 # ITB accesses +system.cpu.itb.fetch_accesses 13756804 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,141 +326,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44593188 # number of cpu cycles simulated +system.cpu.numCycles 44550025 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15564341 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105145283 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16493971 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9255641 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27572822 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 891924 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 262 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 325760 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13750650 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 190232 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15536362 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105039044 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16474744 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9239957 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27563903 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 886514 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 244 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4722 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 331564 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 78 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13727245 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187963 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43914039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.394343 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.128103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43880130 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.393772 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.128235 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24384273 55.53% 55.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1520929 3.46% 58.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1376099 3.13% 62.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1504413 3.43% 65.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4198532 9.56% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1828676 4.16% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 668520 1.52% 80.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050487 2.39% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7382110 16.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24375049 55.55% 55.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1515026 3.45% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1375639 3.13% 62.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1503768 3.43% 65.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4189647 9.55% 75.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1825739 4.16% 79.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 668569 1.52% 80.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050805 2.39% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7375888 16.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43914039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369876 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.357878 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14911775 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9756593 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18301996 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 594945 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 348730 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3706760 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98994 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103174683 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312811 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 348730 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15258388 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4434115 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 96788 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18534618 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5241400 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102158813 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5649 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 94745 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 345515 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4735615 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61411273 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123213365 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122896091 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 317273 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43880130 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369803 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.357777 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14899233 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9760394 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18283223 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 591754 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 345526 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3700749 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 99293 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103056970 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 314917 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 345526 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15243567 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4452634 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97322 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18515033 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5226048 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102057831 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7235 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94720 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 348136 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4717245 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61355857 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123078605 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122759511 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319093 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8864392 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5712 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5765 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2362727 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23149705 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16384887 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1256801 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 494099 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90814957 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5561 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88678954 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70817 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11228761 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4483589 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 978 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43914039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.019376 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.246135 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8808976 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5695 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5747 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2360993 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23135657 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16359365 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1252776 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 502701 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90727911 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5569 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88607473 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 70141 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11141723 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4452155 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 986 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43880130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.019307 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.245631 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17441953 39.72% 39.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5726957 13.04% 52.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5104887 11.62% 64.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4381256 9.98% 74.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4320313 9.84% 84.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2639459 6.01% 90.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1947949 4.44% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1377906 3.14% 97.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 973359 2.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17424086 39.71% 39.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5721163 13.04% 52.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5107482 11.64% 64.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4378378 9.98% 74.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4320360 9.85% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2636536 6.01% 90.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1944467 4.43% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1375974 3.14% 97.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 971684 2.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43914039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43880130 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 242855 9.63% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1163309 46.14% 55.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1115010 44.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 243434 9.65% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1167545 46.27% 55.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1112329 44.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49423838 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43986 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49382948 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43980 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121174 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121151 0.14% 55.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120676 0.14% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39089 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120663 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39093 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -480,82 +482,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22912706 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16017331 18.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22902831 25.85% 81.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15996653 18.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88678954 # Type of FU issued -system.cpu.iq.rate 1.988621 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2521174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028430 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223254204 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101651163 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86893480 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 609734 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 418232 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299390 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90895107 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305021 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1671418 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88607473 # Type of FU issued +system.cpu.iq.rate 1.988943 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2523308 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028477 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223077288 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101475255 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86832445 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420100 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299852 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90825011 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305770 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1671661 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2873067 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5610 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20361 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1771510 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2859019 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5476 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20375 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1745988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3045 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 204833 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3024 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 205293 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 348730 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1277507 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2721681 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100319642 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 124919 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23149705 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16384887 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5561 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3725 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2720217 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20361 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 118662 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 150973 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 269635 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87973235 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22745315 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 705719 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 345526 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1271875 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2754338 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100226384 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125320 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23135657 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16359365 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5569 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3722 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2752972 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20375 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 115768 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 151556 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 267324 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87911556 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22736014 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 695917 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9499124 # number of nop insts executed -system.cpu.iew.exec_refs 38614853 # number of memory reference insts executed -system.cpu.iew.exec_branches 15126858 # Number of branches executed -system.cpu.iew.exec_stores 15869538 # Number of stores executed -system.cpu.iew.exec_rate 1.972795 # Inst execution rate -system.cpu.iew.wb_sent 87594856 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87192870 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33852684 # num instructions producing a value -system.cpu.iew.wb_consumers 44279326 # num instructions consuming a value -system.cpu.iew.wb_rate 1.955296 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764526 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8765402 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9492904 # number of nop insts executed +system.cpu.iew.exec_refs 38587764 # number of memory reference insts executed +system.cpu.iew.exec_branches 15119893 # Number of branches executed +system.cpu.iew.exec_stores 15851750 # Number of stores executed +system.cpu.iew.exec_rate 1.973322 # Inst execution rate +system.cpu.iew.wb_sent 87534383 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87132297 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33840523 # num instructions producing a value +system.cpu.iew.wb_consumers 44256350 # num instructions consuming a value +system.cpu.iew.wb_rate 1.955830 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764648 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8655398 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 229860 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42628268 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.072350 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.885151 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 226701 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42610108 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.073233 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.886041 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21157300 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6282680 14.74% 64.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2903206 6.81% 71.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1743375 4.09% 75.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1680050 3.94% 79.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1128930 2.65% 81.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1204133 2.82% 84.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 796945 1.87% 86.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5731649 13.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21149437 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6275459 14.73% 64.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2900348 6.81% 71.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1740796 4.09% 75.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1682035 3.95% 79.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1127009 2.64% 81.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1202859 2.82% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 795530 1.87% 86.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5736635 13.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42628268 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42610108 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -601,339 +603,339 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5731649 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132685351 # The number of ROB reads -system.cpu.rob.rob_writes 195501271 # The number of ROB writes -system.cpu.timesIdled 46319 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 679149 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5736635 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 132552201 # The number of ROB reads +system.cpu.rob.rob_writes 195265380 # The number of ROB writes +system.cpu.timesIdled 45343 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 669895 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.560274 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.560274 # CPI: Total CPI of All Threads -system.cpu.ipc 1.784841 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.784841 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116453986 # number of integer regfile reads -system.cpu.int_regfile_writes 57709287 # number of integer regfile writes -system.cpu.fp_regfile_reads 255067 # number of floating regfile reads -system.cpu.fp_regfile_writes 240450 # number of floating regfile writes -system.cpu.misc_regfile_reads 38270 # number of misc regfile reads +system.cpu.cpi 0.559732 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.559732 # CPI: Total CPI of All Threads +system.cpu.ipc 1.786570 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.786570 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116366061 # number of integer regfile reads +system.cpu.int_regfile_writes 57668563 # number of integer regfile writes +system.cpu.fp_regfile_reads 255567 # number of floating regfile reads +system.cpu.fp_regfile_writes 240367 # number of floating regfile writes +system.cpu.misc_regfile_reads 38271 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 201399 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.676822 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33995451 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205495 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.432011 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 201418 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.642288 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33984828 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205514 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.365026 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 229821500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.676822 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993818 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993818 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.642288 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993809 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993809 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2778 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2776 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1244 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70838999 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70838999 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20434147 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20434147 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561246 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561246 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 58 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 58 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33995393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33995393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33995393 # number of overall hits -system.cpu.dcache.overall_hits::total 33995393 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269170 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052131 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052131 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321301 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321301 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321301 # number of overall misses -system.cpu.dcache.overall_misses::total 1321301 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17282869000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17282869000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89120990413 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89120990413 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106403859413 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106403859413 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106403859413 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106403859413 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20703317 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20703317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70818146 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70818146 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20423642 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20423642 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561123 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561123 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33984765 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33984765 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33984765 # number of overall hits +system.cpu.dcache.overall_hits::total 33984765 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269234 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269234 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052254 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052254 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1321488 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321488 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321488 # number of overall misses +system.cpu.dcache.overall_misses::total 1321488 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17321162000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17321162000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89091667377 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89091667377 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106412829377 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106412829377 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106412829377 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106412829377 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20692876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20692876 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35316694 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35316694 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35316694 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35316694 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013001 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071998 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071998 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037413 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037413 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037413 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037413 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64208.006093 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64208.006093 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84705.222461 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84705.222461 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80529.613928 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80529.613928 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80529.613928 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80529.613928 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6870751 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35306253 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35306253 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35306253 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35306253 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013011 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013011 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072006 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072006 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037429 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037429 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037429 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64334.972552 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64334.972552 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84667.454224 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84667.454224 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80525.006188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80525.006188 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6873080 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 89149 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 89218 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.070421 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.036921 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168802 # number of writebacks -system.cpu.dcache.writebacks::total 168802 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207068 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207068 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908738 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908738 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115806 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115806 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115806 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115806 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62102 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143393 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143393 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205495 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205495 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205495 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205495 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3198491500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3198491500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14240616218 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14240616218 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17439107718 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17439107718 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17439107718 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17439107718 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003000 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 168806 # number of writebacks +system.cpu.dcache.writebacks::total 168806 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207108 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207108 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908866 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 908866 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115974 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115974 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115974 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115974 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62126 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62126 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143388 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143388 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205514 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205514 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205514 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205514 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3205966000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3205966000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14246299714 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14246299714 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17452265714 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17452265714 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17452265714 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17452265714 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005819 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005819 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51503.840456 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51503.840456 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99311.794983 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99311.794983 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84863.902859 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84863.902859 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84863.902859 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84863.902859 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005821 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005821 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51604.255867 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51604.255867 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99354.895207 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99354.895207 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 91476 # number of replacements -system.cpu.icache.tags.tagsinuse 1915.700741 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13644579 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93524 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 145.893878 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18771424500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1915.700741 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.935401 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.935401 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 90292 # number of replacements +system.cpu.icache.tags.tagsinuse 1916.963164 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13622372 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 92340 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.524063 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18757985500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1916.963164 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936017 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936017 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1477 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 380 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 384 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27594820 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27594820 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13644579 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13644579 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13644579 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13644579 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13644579 # number of overall hits -system.cpu.icache.overall_hits::total 13644579 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106069 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106069 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106069 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106069 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106069 # number of overall misses -system.cpu.icache.overall_misses::total 106069 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1942429499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1942429499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1942429499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1942429499 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18326.350208 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18326.350208 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 99.928571 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1869.508141 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1926.294965 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.817872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.058786 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.933711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32093 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3131 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28315 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 361 # 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miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106244.746903 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106244.746903 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81924.535664 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81924.535664 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98625.430663 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98625.430663 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81924.535664 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104906.501349 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 104014.380404 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81924.535664 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104906.501349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104014.380404 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -942,123 +944,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114413 # number of writebacks -system.cpu.l2cache.writebacks::total 114413 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 112 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 112 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12586888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 460830500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 460830500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2469459000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2469459000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 460830500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15056347000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15517177500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 460830500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15056347000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15517177500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.068506 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448624 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448624 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772009 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.551973 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772009 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.551973 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96197.631209 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96197.631209 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72605.587639 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72605.587639 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88379.055994 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88379.055994 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72605.587639 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94824.585235 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93962.081417 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72605.587639 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94824.585235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93962.081417 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912052 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912052 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069384 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448530 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448530 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.554132 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.554132 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96244.746903 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96244.746903 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71926.096457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71926.096457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88625.430663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88625.430663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 591895 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 292875 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 589565 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 291710 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4047 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4047 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4045 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 155625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283215 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 91476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51263 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143394 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143394 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 93525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 278525 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612389 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 890914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11840000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23955008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35795008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133079 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 432099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009366 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.096323 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 154463 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283225 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 90292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51275 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 92341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62123 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 274973 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887419 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11688448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23956480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35644928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133082 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 430937 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009387 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.096428 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 428052 99.06% 99.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4047 0.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 426892 99.06% 99.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4045 0.94% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 432099 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 556225500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 430937 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 553880500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 140299972 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 138521976 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308258967 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308281978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 34266 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114413 # Transaction distribution -system.membus.trans_dist::CleanEvict 14730 # Transaction distribution -system.membus.trans_dist::ReadExReq 130784 # Transaction distribution -system.membus.trans_dist::ReadExResp 130784 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34266 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 459243 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 459243 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17885632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17885632 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 34270 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114419 # Transaction distribution +system.membus.trans_dist::CleanEvict 14728 # Transaction distribution +system.membus.trans_dist::ReadExReq 130780 # Transaction distribution +system.membus.trans_dist::ReadExResp 130780 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34270 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 459247 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 459247 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17886016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17886016 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 294193 # Request fanout histogram +system.membus.snoop_fanout::samples 294197 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294193 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294197 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294193 # Request fanout histogram -system.membus.reqLayer0.occupancy 777045500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294197 # Request fanout histogram +system.membus.reqLayer0.occupancy 776999500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 852834000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 852713250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 357735e21..ec22c8c38 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.056966 # Number of seconds simulated -sim_ticks 56966152500 # Number of ticks simulated -final_tick 56966152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056803 # Number of seconds simulated +sim_ticks 56802974500 # Number of ticks simulated +final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83103 # Simulator instruction rate (inst/s) -host_op_rate 106277 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66756773 # Simulator tick rate (ticks/s) -host_mem_usage 309512 # Number of bytes of host memory used -host_seconds 853.34 # Real time elapsed on the host +host_inst_rate 208655 # Simulator instruction rate (inst/s) +host_op_rate 266840 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167132713 # Simulator tick rate (ticks/s) +host_mem_usage 280072 # Number of bytes of host memory used +host_seconds 339.87 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 285184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory -system.physmem.bytes_read::total 8209856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 285184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 285184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5517504 # Number of bytes written to this memory -system.physmem.bytes_written::total 5517504 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4456 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 285504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5517760 # Number of bytes written to this memory +system.physmem.bytes_written::total 5517760 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4461 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128279 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86211 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5006201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 139111940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 144118141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5006201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5006201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96855830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96855830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96855830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5006201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 139111940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 240973971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128279 # Number of read requests accepted -system.physmem.writeReqs 86211 # Number of write requests accepted -system.physmem.readBursts 128279 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 86211 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8209472 # Total number of bytes read from DRAM +system.physmem.num_reads::total 128284 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86215 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86215 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5026216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139511567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144537783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5026216 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5026216 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97138575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97138575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97138575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5026216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139511567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241676358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128284 # Number of read requests accepted +system.physmem.writeReqs 86215 # Number of write requests accepted +system.physmem.readBursts 128284 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86215 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8209792 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5515584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8209856 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side +system.physmem.bytesWritten 5515904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8210176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5517760 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8061 # Per bank write bursts -system.physmem.perBankRdBursts::1 8314 # Per bank write bursts +system.physmem.perBankRdBursts::0 8062 # Per bank write bursts +system.physmem.perBankRdBursts::1 8315 # Per bank write bursts system.physmem.perBankRdBursts::2 8233 # Per bank write bursts -system.physmem.perBankRdBursts::3 8140 # Per bank write bursts +system.physmem.perBankRdBursts::3 8142 # Per bank write bursts system.physmem.perBankRdBursts::4 8284 # Per bank write bursts system.physmem.perBankRdBursts::5 8403 # Per bank write bursts system.physmem.perBankRdBursts::6 8055 # Per bank write bursts -system.physmem.perBankRdBursts::7 7915 # Per bank write bursts +system.physmem.perBankRdBursts::7 7916 # Per bank write bursts system.physmem.perBankRdBursts::8 8035 # Per bank write bursts system.physmem.perBankRdBursts::9 7587 # Per bank write bursts system.physmem.perBankRdBursts::10 7763 # Per bank write bursts @@ -64,16 +64,16 @@ system.physmem.perBankRdBursts::12 7871 # Pe system.physmem.perBankRdBursts::13 7867 # Per bank write bursts system.physmem.perBankRdBursts::14 7968 # Per bank write bursts system.physmem.perBankRdBursts::15 7962 # Per bank write bursts -system.physmem.perBankWrBursts::0 5394 # Per bank write bursts +system.physmem.perBankWrBursts::0 5395 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts system.physmem.perBankWrBursts::2 5468 # Per bank write bursts -system.physmem.perBankWrBursts::3 5335 # Per bank write bursts +system.physmem.perBankWrBursts::3 5336 # Per bank write bursts system.physmem.perBankWrBursts::4 5366 # Per bank write bursts -system.physmem.perBankWrBursts::5 5559 # Per bank write bursts +system.physmem.perBankWrBursts::5 5560 # Per bank write bursts system.physmem.perBankWrBursts::6 5257 # Per bank write bursts -system.physmem.perBankWrBursts::7 5180 # Per bank write bursts -system.physmem.perBankWrBursts::8 5155 # Per bank write bursts -system.physmem.perBankWrBursts::9 5101 # Per bank write bursts +system.physmem.perBankWrBursts::7 5179 # Per bank write bursts +system.physmem.perBankWrBursts::8 5154 # Per bank write bursts +system.physmem.perBankWrBursts::9 5105 # Per bank write bursts system.physmem.perBankWrBursts::10 5292 # Per bank write bursts system.physmem.perBankWrBursts::11 5270 # Per bank write bursts system.physmem.perBankWrBursts::12 5531 # Per bank write bursts @@ -82,24 +82,24 @@ system.physmem.perBankWrBursts::14 5703 # Pe system.physmem.perBankWrBursts::15 5432 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56966120500 # Total gap between requests +system.physmem.totGap 56802942500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128279 # Read request sizes (log2) +system.physmem.readPktSize::6 128284 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 86211 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86215 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,34 +144,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5314 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -193,102 +193,105 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38803 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.679870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 214.740030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.847890 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12299 31.70% 31.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8268 21.31% 53.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4108 10.59% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2801 7.22% 70.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2598 6.70% 77.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1655 4.27% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1337 3.45% 85.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1145 2.95% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4592 11.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38803 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5292 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.235639 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.487123 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5289 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38880 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.990947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 214.489872 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.589979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12269 31.56% 31.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8336 21.44% 53.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4191 10.78% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2845 7.32% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2490 6.40% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1681 4.32% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1302 3.35% 85.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1149 2.96% 88.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4617 11.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38880 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.227616 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 352.423208 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5291 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5292 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5292 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.285147 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.266957 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.809216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4635 87.59% 87.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.11% 87.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 507 9.58% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 117 2.21% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 17 0.32% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.08% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5292 # Writes before turning the bus around for reads -system.physmem.totQLat 1670425750 # Total ticks spent queuing -system.physmem.totMemAccLat 4075544500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 641365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13022.43 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.279940 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.260845 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.856304 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4659 88.01% 88.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 4 0.08% 88.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 483 9.12% 97.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 119 2.25% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 16 0.30% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 8 0.15% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 3 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads +system.physmem.totQLat 1681541750 # Total ticks spent queuing +system.physmem.totMemAccLat 4086754250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 641390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13108.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31772.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 144.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 144.12 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.86 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31858.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 97.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 97.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.88 # Data bus utilization in percentage +system.physmem.busUtil 1.89 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.35 # Average write queue length when enqueuing -system.physmem.readRowHits 111858 # Number of row buffer hits during reads -system.physmem.writeRowHits 63787 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes -system.physmem.avgGap 265588.70 # Average gap between requests -system.physmem.pageHitRate 81.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 152953920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83457000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 510065400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 279210240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3720624960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11616680655 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 23988608250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40351600425 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.364424 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39782190750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1902160000 # Time in different power states +system.physmem.avgWrQLen 23.24 # Average write queue length when enqueuing +system.physmem.readRowHits 111837 # Number of row buffer hits during reads +system.physmem.writeRowHits 63741 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.93 # Row buffer hit rate for writes +system.physmem.avgGap 264816.82 # Average gap between requests +system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 153127800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 83551875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 510073200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11545672905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 23952789000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40234383180 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.339923 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39720213500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1896700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15280128000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15184054000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140358960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76584750 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 140767200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76807500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 490315800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3720624960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10974085740 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24552288000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40233397170 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.289389 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40717988750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1902160000 # Time in different power states +system.physmem_1.writeEnergy 279158400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11005773750 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24426384750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40129152600 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.487303 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40510168000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1896700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14344414250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14806373 # Number of BP lookups -system.cpu.branchPred.condPredicted 9910083 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 383814 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9538678 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6734058 # Number of BTB hits +system.cpu.branchPred.lookups 14774616 # Number of BP lookups +system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9548677 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6547888 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.597393 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1715002 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 68.573772 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1714315 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 174550 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 157999 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -407,97 +410,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 113932305 # number of cpu cycles simulated +system.cpu.numCycles 113605949 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1148486 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.606600 # CPI: cycles per instruction -system.cpu.ipc 0.622432 # IPC: instructions per cycle -system.cpu.tickCycles 95622082 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18310223 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156441 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.130215 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42625643 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160537 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.519120 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.130215 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992952 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy +system.cpu.cpi 1.601998 # CPI: cycles per instruction +system.cpu.ipc 0.624220 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction +system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 90690106 # Class of committed instruction +system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156448 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1097 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2955 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86019473 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86019473 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22868200 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22868200 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642188 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642188 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83417 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83417 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42510388 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42510388 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42593805 # number of overall hits -system.cpu.dcache.overall_hits::total 42593805 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51522 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51522 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207713 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207713 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259235 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259235 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 303825 # number of overall misses -system.cpu.dcache.overall_misses::total 303825 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1488627000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1488627000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16793358000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16793358000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18281985000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18281985000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18281985000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18281985000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22919722 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22919722 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42505075 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42505075 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42588476 # number of overall hits +system.cpu.dcache.overall_hits::total 42588476 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51661 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51661 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207729 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207729 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44584 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44584 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259390 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259390 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303974 # number of overall misses +system.cpu.dcache.overall_misses::total 303974 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1490194000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1490194000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16811157000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16811157000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18301351000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18301351000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18301351000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18301351000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22914564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22914564 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128007 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128007 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127985 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127985 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42769623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42769623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42897630 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42897630 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002248 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002248 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348340 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348340 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006061 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006061 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28893.035985 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28893.035985 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80848.853948 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80848.853948 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70522.826779 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70522.826779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60172.747470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60172.747470 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 42764465 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42764465 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42892450 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42892450 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002255 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002255 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348353 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.348353 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28845.628230 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28845.628230 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80928.310443 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80928.310443 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70555.345233 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70555.345233 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60206.961780 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -506,110 +544,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128384 # number of writebacks -system.cpu.dcache.writebacks::total 128384 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22002 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22002 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100685 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100685 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122687 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122687 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122687 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122687 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29520 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29520 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23989 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23989 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136548 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136548 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160537 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160537 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 575604000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 575604000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8480832000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8480832000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713530500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713530500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9056436000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9056436000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10769966500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10769966500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128389 # number of writebacks +system.cpu.dcache.writebacks::total 128389 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22138 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22138 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100695 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100695 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122833 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122833 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122833 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122833 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29523 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29523 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23987 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23987 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136557 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136557 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160544 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160544 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 578329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8490118500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8490118500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713467500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713467500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9068448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9068448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10781915500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10781915500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187404 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187404 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187420 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187420 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19498.780488 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19498.780488 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79239.376612 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79239.376612 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71429.842845 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71429.842845 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66324.193690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66324.193690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67087.129447 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67087.129447 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003743 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003743 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19589.116960 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19589.116960 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42871 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.494475 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24951243 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44913 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 555.546123 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 43497 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.494475 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 917 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50037227 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50037227 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24951243 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24951243 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24951243 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24951243 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24951243 # number of overall hits -system.cpu.icache.overall_hits::total 24951243 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44914 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44914 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44914 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44914 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44914 # number of overall misses -system.cpu.icache.overall_misses::total 44914 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 896931500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 896931500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 896931500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 896931500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 896931500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 896931500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24996157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24996157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24996157 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24996157 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24996157 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24996157 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001797 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356201500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 356201500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1872087500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1872087500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 356201500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10151711000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10507912500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 356201500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10151711000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10507912500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 128389 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 128389 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 39908 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 39908 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45540 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 45540 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 45540 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160544 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 206084 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 45540 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160544 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 206084 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955603 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955603 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098265 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098265 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403719 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403719 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098265 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771658 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.622853 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098265 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771658 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.622853 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80948.979293 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80948.979293 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79598.100559 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79598.100559 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86658.681665 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86658.681665 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81862.827205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81862.827205 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,8 +793,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 86211 # number of writebacks -system.cpu.l2cache.writebacks::total 86211 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 86215 # number of writebacks +system.cpu.l2cache.writebacks::total 86215 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits @@ -769,119 +807,119 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 62 system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102276 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102276 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4457 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4457 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21547 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21547 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4457 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102282 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102282 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4462 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4462 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21541 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21541 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4462 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128280 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4457 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128285 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4462 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128280 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7247586500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7247586500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310540000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310540000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649696000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649696000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310540000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8897282500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9207822500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310540000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8897282500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9207822500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 128285 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7256803500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7256803500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310457000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310457000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1652012000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1652012000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310457000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8908815500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9219272500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310457000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8908815500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9219272500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099234 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402680 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402680 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771305 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.624382 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771305 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.624382 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70863.022605 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70863.022605 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69674.669060 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69674.669060 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76562.676939 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76562.676939 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69674.669060 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71854.845223 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71779.096508 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69674.669060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71854.845223 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71779.096508 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955603 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955603 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097980 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402560 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402560 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.622489 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.622489 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70948.979293 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70948.979293 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69577.991932 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69577.991932 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76691.518500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76691.518500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 404763 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 199348 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7815 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3362 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 98422 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214595 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 42871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 38233 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 44914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53509 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132698 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477515 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 610213 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5618176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24109120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 96387 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 301838 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.037245 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.189869 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 612112 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5698304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24190016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 96391 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 302475 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037210 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.189781 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 290625 96.29% 96.29% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11184 3.71% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 291249 96.29% 96.29% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11197 3.70% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 301838 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 373636500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 302475 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 374900500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 67388961 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68328959 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240839931 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 26003 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86211 # Transaction distribution -system.membus.trans_dist::CleanEvict 6909 # Transaction distribution -system.membus.trans_dist::ReadExReq 102276 # Transaction distribution -system.membus.trans_dist::ReadExResp 102276 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26003 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349678 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 349678 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13727360 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 26002 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution +system.membus.trans_dist::CleanEvict 6912 # Transaction distribution +system.membus.trans_dist::ReadExReq 102282 # Transaction distribution +system.membus.trans_dist::ReadExResp 102282 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26002 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 349695 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13727936 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 221399 # Request fanout histogram +system.membus.snoop_fanout::samples 221411 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 221399 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 221411 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 221399 # Request fanout histogram -system.membus.reqLayer0.occupancy 590619000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 221411 # Request fanout histogram +system.membus.reqLayer0.occupancy 590704500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 676896750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 676958000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 7ec2ce465..5ae3909df 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033709 # Number of seconds simulated -sim_ticks 33708718000 # Number of ticks simulated -final_tick 33708718000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033525 # Number of seconds simulated +sim_ticks 33524756000 # Number of ticks simulated +final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58097 # Simulator instruction rate (inst/s) -host_op_rate 74299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27618733 # Simulator tick rate (ticks/s) -host_mem_usage 312228 # Number of bytes of host memory used -host_seconds 1220.50 # Real time elapsed on the host +host_inst_rate 145211 # Simulator instruction rate (inst/s) +host_op_rate 185708 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68655135 # Simulator tick rate (ticks/s) +host_mem_usage 282260 # Number of bytes of host memory used +host_seconds 488.31 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 642112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2851904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6180288 # Number of bytes read from this memory -system.physmem.bytes_read::total 9674304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 642112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 642112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6216192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6216192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10033 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 44561 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96567 # Number of read requests responded to by this memory -system.physmem.num_reads::total 151161 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97128 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97128 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19048841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 84604345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 183343905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 286997091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19048841 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19048841 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 184409030 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 184409030 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 184409030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19048841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 84604345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 183343905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 471406121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 151162 # Number of read requests accepted -system.physmem.writeReqs 97128 # Number of write requests accepted -system.physmem.readBursts 151162 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97128 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9665216 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue -system.physmem.bytesWritten 6214528 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9674368 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6216192 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory +system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 697984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 697984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6216960 # Number of bytes written to this memory +system.physmem.bytes_written::total 6216960 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10906 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 45743 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 153088 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97140 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97140 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20819958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 87325080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 184105620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 292250658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20819958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20819958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 185443855 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 185443855 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 185443855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20819958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 87325080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 184105620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 477694513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 153089 # Number of read requests accepted +system.physmem.writeReqs 97140 # Number of write requests accepted +system.physmem.readBursts 153089 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97140 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9788224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 6215872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9797696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6216960 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9070 # Per bank write bursts -system.physmem.perBankRdBursts::1 9361 # Per bank write bursts -system.physmem.perBankRdBursts::2 9561 # Per bank write bursts -system.physmem.perBankRdBursts::3 11292 # Per bank write bursts -system.physmem.perBankRdBursts::4 10590 # Per bank write bursts -system.physmem.perBankRdBursts::5 10416 # Per bank write bursts -system.physmem.perBankRdBursts::6 9949 # Per bank write bursts -system.physmem.perBankRdBursts::7 8975 # Per bank write bursts -system.physmem.perBankRdBursts::8 9423 # Per bank write bursts -system.physmem.perBankRdBursts::9 9187 # Per bank write bursts -system.physmem.perBankRdBursts::10 9162 # Per bank write bursts -system.physmem.perBankRdBursts::11 8879 # Per bank write bursts -system.physmem.perBankRdBursts::12 8652 # Per bank write bursts -system.physmem.perBankRdBursts::13 8689 # Per bank write bursts -system.physmem.perBankRdBursts::14 8733 # Per bank write bursts -system.physmem.perBankRdBursts::15 9080 # Per bank write bursts -system.physmem.perBankWrBursts::0 5971 # Per bank write bursts -system.physmem.perBankWrBursts::1 6177 # Per bank write bursts -system.physmem.perBankWrBursts::2 6109 # Per bank write bursts -system.physmem.perBankWrBursts::3 6172 # Per bank write bursts -system.physmem.perBankWrBursts::4 6049 # Per bank write bursts -system.physmem.perBankWrBursts::5 6259 # Per bank write bursts -system.physmem.perBankWrBursts::6 6017 # Per bank write bursts -system.physmem.perBankWrBursts::7 5953 # Per bank write bursts -system.physmem.perBankWrBursts::8 5939 # Per bank write bursts -system.physmem.perBankWrBursts::9 6100 # Per bank write bursts -system.physmem.perBankWrBursts::10 6208 # Per bank write bursts -system.physmem.perBankWrBursts::11 5866 # Per bank write bursts -system.physmem.perBankWrBursts::12 6052 # Per bank write bursts -system.physmem.perBankWrBursts::13 6067 # Per bank write bursts -system.physmem.perBankWrBursts::14 6159 # Per bank write bursts -system.physmem.perBankWrBursts::15 6004 # Per bank write bursts +system.physmem.perBankRdBursts::0 9103 # Per bank write bursts +system.physmem.perBankRdBursts::1 9407 # Per bank write bursts +system.physmem.perBankRdBursts::2 9452 # Per bank write bursts +system.physmem.perBankRdBursts::3 11458 # Per bank write bursts +system.physmem.perBankRdBursts::4 10748 # Per bank write bursts +system.physmem.perBankRdBursts::5 11390 # Per bank write bursts +system.physmem.perBankRdBursts::6 10031 # Per bank write bursts +system.physmem.perBankRdBursts::7 8920 # Per bank write bursts +system.physmem.perBankRdBursts::8 9321 # Per bank write bursts +system.physmem.perBankRdBursts::9 9437 # Per bank write bursts +system.physmem.perBankRdBursts::10 9070 # Per bank write bursts +system.physmem.perBankRdBursts::11 9080 # Per bank write bursts +system.physmem.perBankRdBursts::12 8731 # Per bank write bursts +system.physmem.perBankRdBursts::13 8724 # Per bank write bursts +system.physmem.perBankRdBursts::14 9025 # Per bank write bursts +system.physmem.perBankRdBursts::15 9044 # Per bank write bursts +system.physmem.perBankWrBursts::0 5968 # Per bank write bursts +system.physmem.perBankWrBursts::1 6230 # Per bank write bursts +system.physmem.perBankWrBursts::2 6083 # Per bank write bursts +system.physmem.perBankWrBursts::3 6155 # Per bank write bursts +system.physmem.perBankWrBursts::4 6058 # Per bank write bursts +system.physmem.perBankWrBursts::5 6286 # Per bank write bursts +system.physmem.perBankWrBursts::6 6021 # Per bank write bursts +system.physmem.perBankWrBursts::7 5958 # Per bank write bursts +system.physmem.perBankWrBursts::8 5969 # Per bank write bursts +system.physmem.perBankWrBursts::9 6064 # Per bank write bursts +system.physmem.perBankWrBursts::10 6185 # Per bank write bursts +system.physmem.perBankWrBursts::11 5907 # Per bank write bursts +system.physmem.perBankWrBursts::12 6058 # Per bank write bursts +system.physmem.perBankWrBursts::13 6089 # Per bank write bursts +system.physmem.perBankWrBursts::14 6121 # Per bank write bursts +system.physmem.perBankWrBursts::15 5971 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33708706500 # Total gap between requests +system.physmem.totGap 33524744500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 151162 # Read request sizes (log2) +system.physmem.readPktSize::6 153089 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97128 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 48274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 73 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97140 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 50282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 71 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,104 +197,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 94915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 167.290734 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 105.391717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 236.347458 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59184 62.35% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22349 23.55% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4070 4.29% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1460 1.54% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 942 0.99% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 824 0.87% 93.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 583 0.61% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 753 0.79% 95.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4750 5.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 94915 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5848 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.821990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 198.480384 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5847 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 96335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 166.118316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 104.810468 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 234.858667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 60546 62.85% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22368 23.22% 86.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3987 4.14% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1542 1.60% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 931 0.97% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 863 0.90% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 636 0.66% 94.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 773 0.80% 95.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4689 4.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96335 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5845 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.165269 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 198.412430 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5844 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5848 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5848 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.604309 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.557483 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.326112 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4590 78.49% 78.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 34 0.58% 79.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 732 12.52% 91.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 206 3.52% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 140 2.39% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 85 1.45% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 32 0.55% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 13 0.22% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.09% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 7 0.12% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5848 # Writes before turning the bus around for reads -system.physmem.totQLat 6766168330 # Total ticks spent queuing -system.physmem.totMemAccLat 9597774580 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 755095000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44803.42 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5845 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5845 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.616424 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.570046 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.313075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4545 77.76% 77.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 48 0.82% 78.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 753 12.88% 91.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 215 3.68% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 127 2.17% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 88 1.51% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 42 0.72% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 17 0.29% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.09% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5845 # Writes before turning the bus around for reads +system.physmem.totQLat 6714977565 # Total ticks spent queuing +system.physmem.totMemAccLat 9582621315 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 764705000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43905.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 63553.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 286.73 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 184.36 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 287.00 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 184.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 62655.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 291.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 185.41 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 292.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 185.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.68 # Data bus utilization in percentage -system.physmem.busUtilRead 2.24 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.44 # Average write queue length when enqueuing -system.physmem.readRowHits 120218 # Number of row buffer hits during reads -system.physmem.writeRowHits 32977 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.95 # Row buffer hit rate for writes -system.physmem.avgGap 135763.45 # Average gap between requests -system.physmem.pageHitRate 61.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 372428280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 203209875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 617682000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 315563040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2201556240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14512366440 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7494015750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25716821625 # Total energy per rank (pJ) -system.physmem_0.averagePower 762.953400 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12364292410 # Time in different power states -system.physmem_0.memoryStateTime::REF 1125540000 # Time in different power states +system.physmem.busUtil 3.73 # Data bus utilization in percentage +system.physmem.busUtilRead 2.28 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.45 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing +system.physmem.readRowHits 120882 # Number of row buffer hits during reads +system.physmem.writeRowHits 32837 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes +system.physmem.avgGap 133976.26 # Average gap between requests +system.physmem.pageHitRate 61.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 378438480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 206489250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 627572400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 315854640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15155251200 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6817959750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25690916520 # Total energy per rank (pJ) +system.physmem_0.averagePower 766.433942 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11238384768 # Time in different power states +system.physmem_0.memoryStateTime::REF 1119300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 20217117590 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21162395232 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 345038400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 188265000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 559977600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313554240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2201556240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13559944320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 8329473750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25497809550 # Total energy per rank (pJ) -system.physmem_1.averagePower 756.455863 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 13760038430 # Time in different power states -system.physmem_1.memoryStateTime::REF 1125540000 # Time in different power states +system.physmem_1.actEnergy 349513920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 190707000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 564751200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313295040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13737724470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 8061404250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25406746680 # Total energy per rank (pJ) +system.physmem_1.averagePower 757.956338 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 13314860915 # Time in different power states +system.physmem_1.memoryStateTime::REF 1119300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18821462070 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17213709 # Number of BP lookups -system.cpu.branchPred.condPredicted 11523003 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 650148 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9341134 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7678896 # Number of BTB hits +system.cpu.branchPred.lookups 17055826 # Number of BP lookups +system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9258903 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7371283 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.205180 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872990 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 79.612920 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1853216 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101575 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 232758 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 195217 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -413,232 +413,232 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 67417437 # number of cpu cycles simulated +system.cpu.numCycles 67049513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5107349 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88247579 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17213709 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9551886 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60722717 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1326923 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12869 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22781060 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69770 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66511361 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.678949 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300919 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5112037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87027076 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17055826 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9419716 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60300614 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1224115 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12656 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22418203 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 68072 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66043378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.665685 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.303820 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20706181 31.13% 31.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8267608 12.43% 43.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9211127 13.85% 57.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28326445 42.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20904696 31.65% 31.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8151419 12.34% 44.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9105743 13.79% 57.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27881520 42.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66511361 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.255330 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.308973 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8663293 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 20135580 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31585821 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5633203 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 493464 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3182521 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171963 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101430430 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3050546 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 493464 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13424917 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5969682 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 834240 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32240480 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13548578 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99223336 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 980873 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3826325 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 67087 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4382425 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5163178 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103933922 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457817395 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115439825 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 66043378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.254377 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.297952 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8568047 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 20331818 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31035970 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5662045 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 445498 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3138719 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168392 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100377883 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2807284 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 445498 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13201972 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6021135 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 843957 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31848304 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13682512 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98401933 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 864722 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3910657 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69359 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4461482 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5194138 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103316551 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453881397 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114363596 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10304553 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18670 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18666 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12721444 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24327620 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22002844 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1418421 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2362163 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98185716 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34529 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94914966 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 694952 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7537638 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20282691 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66511361 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.427049 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.152183 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9687182 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18952 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18977 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12759909 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24172969 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21779154 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1438398 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2287665 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97467378 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34812 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94518121 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 609879 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6819583 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18149075 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1026 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66043378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.431152 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.152558 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18195190 27.36% 27.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17483152 26.29% 53.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17116175 25.73% 79.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11668879 17.54% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2046998 3.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 967 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17971444 27.21% 27.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17366377 26.30% 53.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17018277 25.77% 79.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11635318 17.62% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2050574 3.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1388 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66511361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66043378 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6715190 22.43% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 42 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11181767 37.35% 59.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12039186 40.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6745698 22.64% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 37 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11091756 37.22% 59.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11960162 40.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49504183 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89872 0.09% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24074068 25.36% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21246803 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49324075 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86626 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 12 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23968009 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21139361 22.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94914966 # Type of FU issued -system.cpu.iq.rate 1.407870 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29936185 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315400 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286972221 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105769455 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93478190 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124851032 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1366282 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94518121 # Type of FU issued +system.cpu.iq.rate 1.409676 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29797653 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315259 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 285486823 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104332871 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93229184 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 329 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 574 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124315586 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1381077 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1461358 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2098 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12063 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1447106 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1306707 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11900 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1223416 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 140885 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 185939 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 147221 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 186554 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 493464 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 630348 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 519071 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98230120 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 445498 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 578203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 566637 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97517928 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24327620 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22002844 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18609 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1657 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 514382 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12063 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 303781 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221600 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 525381 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93994405 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23766194 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 920561 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24172969 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21779154 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18892 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1555 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 562180 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11900 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 250835 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 223196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 474031 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93719339 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23701905 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 798782 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9875 # number of nop insts executed -system.cpu.iew.exec_refs 44755394 # number of memory reference insts executed -system.cpu.iew.exec_branches 14253394 # Number of branches executed -system.cpu.iew.exec_stores 20989200 # Number of stores executed -system.cpu.iew.exec_rate 1.394215 # Inst execution rate -system.cpu.iew.wb_sent 93600457 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93478249 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44984526 # num instructions producing a value -system.cpu.iew.wb_consumers 76573166 # num instructions consuming a value -system.cpu.iew.wb_rate 1.386559 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587471 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6555355 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 15738 # number of nop insts executed +system.cpu.iew.exec_refs 44631646 # number of memory reference insts executed +system.cpu.iew.exec_branches 14212084 # Number of branches executed +system.cpu.iew.exec_stores 20929741 # Number of stores executed +system.cpu.iew.exec_rate 1.397763 # Inst execution rate +system.cpu.iew.wb_sent 93338125 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93229268 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44994314 # num instructions producing a value +system.cpu.iew.wb_consumers 76693481 # num instructions consuming a value +system.cpu.iew.wb_rate 1.390454 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586677 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5957514 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 480151 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 65449475 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.385621 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.157530 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 432296 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 65078464 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.393520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.163869 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31837500 48.64% 48.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16816023 25.69% 74.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4347616 6.64% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4166544 6.37% 87.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1933514 2.95% 90.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1257718 1.92% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 744905 1.14% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 580044 0.89% 94.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3765611 5.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31565690 48.50% 48.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16713735 25.68% 74.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4316875 6.63% 80.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4188712 6.44% 87.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1942227 2.98% 90.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1235606 1.90% 92.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 754913 1.16% 93.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 587526 0.90% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3773180 5.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 65449475 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 65078464 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,388 +684,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3765611 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158902079 # The number of ROB reads -system.cpu.rob.rob_writes 195550630 # The number of ROB writes -system.cpu.timesIdled 26501 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 906076 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3773180 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 157925658 # The number of ROB reads +system.cpu.rob.rob_writes 194257744 # The number of ROB writes +system.cpu.timesIdled 27177 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1006135 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.950778 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.950778 # CPI: Total CPI of All Threads -system.cpu.ipc 1.051770 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.051770 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102290676 # number of integer regfile reads -system.cpu.int_regfile_writes 56801575 # number of integer regfile writes -system.cpu.fp_regfile_reads 38 # number of floating regfile reads -system.cpu.fp_regfile_writes 22 # number of floating regfile writes -system.cpu.cc_regfile_reads 346161860 # number of cc regfile reads -system.cpu.cc_regfile_writes 38808202 # number of cc regfile writes -system.cpu.misc_regfile_reads 44217642 # number of misc regfile reads +system.cpu.cpi 0.945589 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.945589 # CPI: Total CPI of All Threads +system.cpu.ipc 1.057542 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.057542 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102008139 # number of integer regfile reads +system.cpu.int_regfile_writes 56630693 # number of integer regfile writes +system.cpu.fp_regfile_reads 48 # number of floating regfile reads +system.cpu.fp_regfile_writes 42 # number of floating regfile writes +system.cpu.cc_regfile_reads 345209533 # number of cc regfile reads +system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes +system.cpu.misc_regfile_reads 44112766 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485010 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.749644 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40413326 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485522 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.236858 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.749644 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997558 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997558 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 486293 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 486805 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 82.847407 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 150823500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.756058 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997570 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84616114 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84616114 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21490425 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21490425 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831304 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831304 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60283 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60283 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15350 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15350 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18832689 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59994 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59994 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40321729 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40321729 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40382012 # number of overall hits -system.cpu.dcache.overall_hits::total 40382012 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 564289 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 564289 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1018597 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1018597 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68553 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68553 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 576 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 576 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1582886 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1582886 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1651439 # number of overall misses -system.cpu.dcache.overall_misses::total 1651439 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9271463500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9271463500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14268416431 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14268416431 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5543500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5543500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23539879931 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23539879931 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23539879931 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23539879931 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054714 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054714 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40239255 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40239255 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40299249 # number of overall hits +system.cpu.dcache.overall_hits::total 40299249 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 567937 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 567937 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1017212 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1017212 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68679 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68679 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1585149 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1585149 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1653828 # number of overall misses +system.cpu.dcache.overall_misses::total 1653828 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9485185000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9485185000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14264451930 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14264451930 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5633500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5633500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23749636930 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23749636930 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23749636930 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23749636930 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21974503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21974503 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128836 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128836 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128673 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128673 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15924 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15924 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904615 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904615 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42033451 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42033451 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025586 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025586 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051315 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051315 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532095 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532095 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036167 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036167 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037774 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037774 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039289 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039289 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16430.345975 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16430.345975 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14007.911304 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14007.911304 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9624.131944 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9624.131944 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14871.494176 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14871.494176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14254.162540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14254.162540 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2905402 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131245 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.727273 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.137240 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41824404 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41824404 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41953077 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41953077 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025845 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025845 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051245 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.533748 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.533748 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038809 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038809 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037900 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037900 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039421 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039421 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16701.121779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16701.121779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14023.086564 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14023.086564 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9115.695793 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9115.695793 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14982.589605 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14982.589605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14360.403216 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2907482 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 485010 # number of writebacks -system.cpu.dcache.writebacks::total 485010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 264882 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 264882 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870061 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870061 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 576 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 576 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1134943 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1134943 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1134943 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1134943 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299407 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299407 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148536 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148536 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37590 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37590 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447943 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447943 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485533 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485533 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3623952500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3623952500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2306335972 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2306335972 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1883780500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1883780500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5930288472 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5930288472 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7814068972 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7814068972 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291766 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291766 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011551 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011551 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.766779 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.766779 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15527.117817 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15527.117817 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50113.873371 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50113.873371 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13238.935472 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13238.935472 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16093.795833 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16093.795833 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks +system.cpu.dcache.writebacks::total 486293 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 267392 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868636 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 868636 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 486821 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 486821 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3693304500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3693304500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2308719470 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2308719470 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1888982500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1888982500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6002023970 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6002023970 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7891006470 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7891006470 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013677 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013677 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292991 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292991 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010738 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010738 # 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 322968 # number of replacements -system.cpu.icache.tags.tagsinuse 510.276903 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22446876 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323480 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.391851 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1134274500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.276903 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996635 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996635 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 338 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45885393 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45885393 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22446876 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22446876 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22446876 # 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number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3448429403 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3448429403 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22780951 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22780951 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22780951 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22780951 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22780951 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22780951 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014665 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014665 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014665 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10536.290484 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10536.290484 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 264177 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16495 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.025904 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # 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number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323492 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323492 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323492 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323492 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323492 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3173672438 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3173672438 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3173672438 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3173672438 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3173672438 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3173672438 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9810.667460 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9810.667460 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 325000 # number of writebacks +system.cpu.icache.writebacks::total 325000 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9178 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 9178 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 9178 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 9178 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 9178 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 9178 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325529 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 325529 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2736 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12138 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 528 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 795 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001709 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996887 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 24987971 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 24987971 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 259400 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 259400 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 468713 # 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Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16324 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 6 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2742 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 553 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001831 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996338 # 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mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.108037 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.108037 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.031019 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091780 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.067484 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.031019 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091780 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033507 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.110605 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.110605 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069739 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.206758 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 92422.017901 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14950 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14950 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80175.655798 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80175.655798 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69730.217261 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69730.217261 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76185.685246 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76185.685246 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69730.217261 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76916.148650 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75595.448301 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69730.217261 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76916.148650 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86929.953864 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.208431 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91646.708819 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14531.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14531.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79433.009476 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79433.009476 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70741.587971 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70741.587971 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75872.186280 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1617003 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 808019 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 65377 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 9034 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 660441 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 356528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 548578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 77222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 142341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323492 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336950 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 969940 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1456076 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2426016 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41372672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62114048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103486720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 316702 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1125716 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.137094 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.366537 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 79349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 142185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 325529 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 338193 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976039 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1459935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2435974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41632640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62278272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103910912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318692 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1131024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.140178 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.373630 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 980421 87.09% 87.09% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 136261 12.10% 99.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 9034 0.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 983264 86.94% 86.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 136975 12.11% 99.05% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 10785 0.95% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1125716 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1616479500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1131024 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1623114500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485683604 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728543988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 488687208 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 143003 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97128 # Transaction distribution -system.membus.trans_dist::CleanEvict 27951 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 8158 # Transaction distribution -system.membus.trans_dist::ReadExResp 8158 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 143004 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 427412 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 427412 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15890496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15890496 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 144751 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution +system.membus.trans_dist::CleanEvict 28117 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 8337 # Transaction distribution +system.membus.trans_dist::ReadExResp 8337 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 144752 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431450 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 431450 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16014592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16014592 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 276251 # Request fanout histogram +system.membus.snoop_fanout::samples 278362 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 276251 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 278362 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 276251 # Request fanout histogram -system.membus.reqLayer0.occupancy 745073302 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 278362 # Request fanout histogram +system.membus.reqLayer0.occupancy 747889943 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 789293648 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 799798093 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |