diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
| commit | f71fa1715793c764ffa95411e87b73179a7c7b3f (patch) | |
| tree | b4095efe0bda4413326c5860754921b7d8ae78e3 /tests/long/se/50.vortex/ref | |
| parent | 42fe2df35495685e616f74ad3342953714c7dcc1 (diff) | |
| download | gem5-f71fa1715793c764ffa95411e87b73179a7c7b3f.tar.xz | |
stats: arm: updates
Diffstat (limited to 'tests/long/se/50.vortex/ref')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt | 1017 | ||||
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1602 |
2 files changed, 1307 insertions, 1312 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 6d11e3682..22befaf24 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057738 # Number of seconds simulated -sim_ticks 57738195500 # Number of ticks simulated -final_tick 57738195500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057717 # Number of seconds simulated +sim_ticks 57716694500 # Number of ticks simulated +final_tick 57716694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113055 # Simulator instruction rate (inst/s) -host_op_rate 144580 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92047581 # Simulator tick rate (ticks/s) -host_mem_usage 250264 # Number of bytes of host memory used -host_seconds 627.26 # Real time elapsed on the host -sim_insts 70915127 # Number of instructions simulated -sim_ops 90690083 # Number of ops (including micro ops) simulated +host_inst_rate 141604 # Simulator instruction rate (inst/s) +host_op_rate 181090 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115249030 # Simulator tick rate (ticks/s) +host_mem_usage 314220 # Number of bytes of host memory used +host_seconds 500.80 # Real time elapsed on the host +sim_insts 70915128 # Number of instructions simulated +sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7922944 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 324096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324096 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372992 # Number of bytes written to this memory system.physmem.bytes_written::total 5372992 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123796 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 5064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128867 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83953 # Number of write requests responded to by this memory system.physmem.num_writes::total 83953 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5617633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 137221885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 142839518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5617633 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5617633 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 93057844 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 93057844 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 93057844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5617633 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 137221885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 235897362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128864 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 5615290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 137280765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 142896056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5615290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5615290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 93092511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 93092511 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 93092511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5615290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 137280765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 235988567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128867 # Number of read requests accepted system.physmem.writeReqs 83953 # Number of write requests accepted -system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128867 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83953 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 8247040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247488 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372992 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8158 # Per bank write bursts -system.physmem.perBankRdBursts::1 8374 # Per bank write bursts -system.physmem.perBankRdBursts::2 8229 # Per bank write bursts +system.physmem.perBankRdBursts::0 8159 # Per bank write bursts +system.physmem.perBankRdBursts::1 8373 # Per bank write bursts +system.physmem.perBankRdBursts::2 8230 # Per bank write bursts system.physmem.perBankRdBursts::3 8170 # Per bank write bursts -system.physmem.perBankRdBursts::4 8316 # Per bank write bursts +system.physmem.perBankRdBursts::4 8318 # Per bank write bursts system.physmem.perBankRdBursts::5 8449 # Per bank write bursts system.physmem.perBankRdBursts::6 8089 # Per bank write bursts -system.physmem.perBankRdBursts::7 7971 # Per bank write bursts -system.physmem.perBankRdBursts::8 8070 # Per bank write bursts -system.physmem.perBankRdBursts::9 7642 # Per bank write bursts -system.physmem.perBankRdBursts::10 7819 # Per bank write bursts +system.physmem.perBankRdBursts::7 7972 # Per bank write bursts +system.physmem.perBankRdBursts::8 8072 # Per bank write bursts +system.physmem.perBankRdBursts::9 7639 # Per bank write bursts +system.physmem.perBankRdBursts::10 7818 # Per bank write bursts system.physmem.perBankRdBursts::11 7829 # Per bank write bursts -system.physmem.perBankRdBursts::12 7880 # Per bank write bursts -system.physmem.perBankRdBursts::13 7877 # Per bank write bursts -system.physmem.perBankRdBursts::14 7978 # Per bank write bursts -system.physmem.perBankRdBursts::15 8008 # Per bank write bursts -system.physmem.perBankWrBursts::0 5182 # Per bank write bursts +system.physmem.perBankRdBursts::12 7882 # Per bank write bursts +system.physmem.perBankRdBursts::13 7878 # Per bank write bursts +system.physmem.perBankRdBursts::14 7976 # Per bank write bursts +system.physmem.perBankRdBursts::15 8006 # Per bank write bursts +system.physmem.perBankWrBursts::0 5185 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts -system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5197 # Per bank write bursts -system.physmem.perBankWrBursts::7 5047 # Per bank write bursts +system.physmem.perBankWrBursts::5 5518 # Per bank write bursts +system.physmem.perBankWrBursts::6 5200 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5088 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::9 5087 # Per bank write bursts +system.physmem.perBankWrBursts::10 5254 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 5451 # Pe system.physmem.perBankWrBursts::15 5225 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57738161000 # Total gap between requests +system.physmem.totGap 57716659500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128864 # Read request sizes (log2) +system.physmem.readPktSize::6 128867 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 83953 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 116721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,99 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.991784 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.320111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.607526 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12100 31.46% 31.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8198 21.31% 52.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4148 10.78% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2890 7.51% 71.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2484 6.46% 77.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1581 4.11% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1319 3.43% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1187 3.09% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4555 11.84% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 38389 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 354.703274 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.932875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.531195 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12049 31.39% 31.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8167 21.27% 52.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4156 10.83% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2841 7.40% 70.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2531 6.59% 77.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1630 4.25% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1300 3.39% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1165 3.03% 88.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4550 11.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38389 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.974593 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 361.421207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.991854 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 361.399783 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.276571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.259351 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.782645 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4530 87.86% 87.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 9 0.17% 88.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 479 9.29% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 112 2.17% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 15 0.29% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8 0.16% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.278898 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.261929 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.774840 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4519 87.65% 87.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.14% 87.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 495 9.60% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 111 2.15% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 19 0.37% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 3 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads -system.physmem.totQLat 1653247250 # Total ticks spent queuing -system.physmem.totMemAccLat 4069353500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12829.89 # Average queueing delay per DRAM burst +system.physmem.totQLat 1645819000 # Total ticks spent queuing +system.physmem.totMemAccLat 4061944000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644300000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12772.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31579.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 142.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 93.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 142.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 93.06 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31522.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 142.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 93.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 142.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 93.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.84 # Data bus utilization in percentage system.physmem.busUtilRead 1.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.36 # Average write queue length when enqueuing -system.physmem.readRowHits 112168 # Number of row buffer hits during reads -system.physmem.writeRowHits 62144 # Number of row buffer hits during writes +system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing +system.physmem.readRowHits 112172 # Number of row buffer hits during reads +system.physmem.writeRowHits 62224 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.02 # Row buffer hit rate for writes -system.physmem.avgGap 271304.27 # Average gap between requests -system.physmem.pageHitRate 81.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 151283160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82545375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512694000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272322000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3770972400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11678597190 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24396798750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40865212875 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.802856 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40459125250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1927900000 # Time in different power states +system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes +system.physmem.avgGap 271199.41 # Average gap between requests +system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 151063920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82425750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512577000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272309040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11829284955 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24250601250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40867708635 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.132582 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40213391000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15348292250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15571447750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139489560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76110375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492070800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 271492560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3770972400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11151778680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24858920250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40760834625 # Total energy per rank (pJ) -system.physmem_1.averagePower 705.994980 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41228847750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1927900000 # Time in different power states +system.physmem_1.actEnergy 139058640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 75875250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492008400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 271479600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11209873365 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24793944750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40751686725 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.122220 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41121510500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14578569750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14663764500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14838314 # Number of BP lookups -system.cpu.branchPred.condPredicted 9926302 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 397118 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9672403 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6752101 # Number of BTB hits +system.cpu.branchPred.lookups 14827145 # Number of BP lookups +system.cpu.branchPred.condPredicted 9920468 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 395132 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9565987 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6746821 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 69.807896 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719649 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.529272 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1718856 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -405,97 +404,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 115476391 # number of cpu cycles simulated +system.cpu.numCycles 115433389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70915127 # Number of instructions committed -system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1150638 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 70915128 # Number of instructions committed +system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1146778 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.628375 # CPI: cycles per instruction -system.cpu.ipc 0.614109 # IPC: instructions per cycle -system.cpu.tickCycles 96920862 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18555529 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156418 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.282815 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42627759 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160514 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.570349 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 830513250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.282815 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992989 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992989 # Average percentage of cache occupancy +system.cpu.cpi 1.627768 # CPI: cycles per instruction +system.cpu.ipc 0.614338 # IPC: instructions per cycle +system.cpu.tickCycles 96895866 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18537523 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156436 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.344190 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42626825 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.534753 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 829717250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.344190 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993004 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993004 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2916 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2911 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86021754 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86021754 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22869180 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22869180 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642188 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642188 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 84553 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 84553 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86020072 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86020072 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22868301 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22868301 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 84507 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 84507 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42511368 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42511368 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42595921 # number of overall hits -system.cpu.dcache.overall_hits::total 42595921 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51489 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51489 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207713 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207713 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 43659 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 43659 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259202 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259202 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 302861 # number of overall misses -system.cpu.dcache.overall_misses::total 302861 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1477411436 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1477411436 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16920342250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16920342250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18397753686 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18397753686 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18397753686 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18397753686 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22920669 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22920669 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42510480 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42510480 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42594987 # number of overall hits +system.cpu.dcache.overall_hits::total 42594987 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 43690 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 43690 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 302945 # number of overall misses +system.cpu.dcache.overall_misses::total 302945 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1474342937 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1474342937 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16908501000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16908501000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18382843937 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18382843937 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18382843937 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18382843937 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22919834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22919834 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128212 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128212 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128197 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128197 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42770570 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42770570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42898782 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42898782 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002246 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002246 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340522 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.340522 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006060 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006060 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007060 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28693.729457 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28693.729457 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81460.198688 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81460.198688 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70978.440313 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70978.440313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60746.526248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60746.526248 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 42769735 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42769735 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42897932 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42897932 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002248 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002248 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340804 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.340804 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28609.685774 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28609.685774 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81399.663974 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81399.663974 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70906.420077 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70906.420077 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60680.466543 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60680.466543 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -504,110 +503,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128435 # number of writebacks -system.cpu.dcache.writebacks::total 128435 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21989 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21989 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100683 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100683 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122672 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122672 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122672 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122672 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29500 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29500 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23984 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23984 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136530 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136530 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160514 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160514 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558489314 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 558489314 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444692500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444692500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1685620500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1685620500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9003181814 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9003181814 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10688802314 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10688802314 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks +system.cpu.dcache.writebacks::total 128445 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22036 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22036 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100688 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100688 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122724 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122724 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122724 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122724 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29497 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29497 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24001 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 24001 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136531 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136531 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558577313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 558577313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8440191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8440191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682073500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682073500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8998768313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8998768313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10680841813 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10680841813 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001287 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001287 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187065 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187065 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187220 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187220 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18931.841153 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18931.841153 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78900.238251 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78900.238251 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70281.041528 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70281.041528 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65942.882985 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65942.882985 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66591.090584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66591.090584 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18936.749941 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18936.749941 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78855.232917 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78855.232917 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70083.475689 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70083.475689 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65910.073998 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65910.073998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66534.035663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66534.035663 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42756 # number of replacements -system.cpu.icache.tags.tagsinuse 1854.448619 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25096729 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44798 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 560.219854 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42847 # number of replacements +system.cpu.icache.tags.tagsinuse 1854.482229 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25082964 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44889 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 558.777518 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1854.448619 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.905492 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.905492 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1854.482229 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.905509 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.905509 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 916 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50327854 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50327854 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25096729 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25096729 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25096729 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25096729 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25096729 # number of overall hits -system.cpu.icache.overall_hits::total 25096729 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44799 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44799 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44799 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44799 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44799 # number of overall misses -system.cpu.icache.overall_misses::total 44799 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 934736739 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 934736739 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 934736739 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 934736739 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 934736739 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 934736739 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25141528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25141528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25141528 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25141528 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25141528 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25141528 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001782 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001782 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001782 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001782 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001782 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001782 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20865.125092 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20865.125092 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20865.125092 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20865.125092 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20865.125092 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20865.125092 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50300597 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50300597 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25082964 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25082964 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25082964 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25082964 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25082964 # number of overall hits +system.cpu.icache.overall_hits::total 25082964 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44890 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44890 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44890 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44890 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44890 # number of overall misses +system.cpu.icache.overall_misses::total 44890 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 936252739 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 936252739 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 936252739 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 936252739 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 936252739 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 936252739 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25127854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25127854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25127854 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25127854 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25127854 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25127854 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001786 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001786 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001786 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001786 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001786 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001786 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20856.599220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20856.599220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20856.599220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20856.599220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20856.599220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20856.599220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -616,123 +615,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44799 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44799 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44799 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44799 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44799 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44799 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 865619261 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 865619261 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 865619261 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 865619261 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 865619261 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 865619261 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001782 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001782 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001782 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001782 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001782 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19322.289806 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19322.289806 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19322.289806 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19322.289806 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19322.289806 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19322.289806 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44890 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44890 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44890 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44890 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44890 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44890 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 867000761 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 867000761 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 867000761 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 867000761 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 867000761 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 867000761 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001786 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001786 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001786 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001786 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001786 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001786 # 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Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.786541 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95728 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29864.649447 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99882 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126846 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.787427 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26746.709888 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1560.467773 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1559.401189 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.816245 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047622 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771247 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.627651 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113150 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771247 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.627651 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66967.794437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73513.049642 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72264.962570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68527.228642 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68527.228642 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66967.794437 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69393.694061 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69298.269507 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66967.794437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69393.694061 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69298.269507 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5065 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21523 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26588 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5065 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5065 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123803 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128868 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 339808000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1578466750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1918274750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7004628000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7004628000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339808000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8583094750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8922902750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339808000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8583094750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8922902750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402314 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270236 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955584 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955584 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771204 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.627333 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771204 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.627333 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67089.437315 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73338.602890 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72148.140138 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68484.825968 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68484.825968 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67089.437315 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69328.649144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69240.639647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67089.437315 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69328.649144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69240.639647 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98283 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98282 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89597 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 539060 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2867072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21359808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98387 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449509 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 539288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2872896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21367424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333748 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333867 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 333748 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 333867 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333748 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295309000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 333867 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295378500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68157239 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68292739 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268247686 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268237687 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 26582 # Transaction distribution -system.membus.trans_dist::ReadResp 26582 # Transaction distribution +system.membus.trans_dist::ReadReq 26587 # Transaction distribution +system.membus.trans_dist::ReadResp 26587 # Transaction distribution system.membus.trans_dist::Writeback 83953 # Transaction distribution -system.membus.trans_dist::ReadExReq 102282 # Transaction distribution -system.membus.trans_dist::ReadExResp 102282 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341681 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341681 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620288 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341687 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212817 # Request fanout histogram +system.membus.snoop_fanout::samples 212820 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212817 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212820 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212817 # Request fanout histogram -system.membus.reqLayer0.occupancy 578407500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 212820 # Request fanout histogram +system.membus.reqLayer0.occupancy 578469000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 680129500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 680054250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 46a8a5ebb..e0d8233d1 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033359 # Number of seconds simulated -sim_ticks 33359312000 # Number of ticks simulated -final_tick 33359312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033331 # Number of seconds simulated +sim_ticks 33330913000 # Number of ticks simulated +final_tick 33330913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119579 # Simulator instruction rate (inst/s) -host_op_rate 152928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56257417 # Simulator tick rate (ticks/s) -host_mem_usage 252556 # Number of bytes of host memory used -host_seconds 592.98 # Real time elapsed on the host -sim_insts 70907629 # Number of instructions simulated -sim_ops 90682584 # Number of ops (including micro ops) simulated +host_inst_rate 93420 # Simulator instruction rate (inst/s) +host_op_rate 119473 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43913176 # Simulator tick rate (ticks/s) +host_mem_usage 317168 # Number of bytes of host memory used +host_seconds 759.02 # Real time elapsed on the host +sim_insts 70907630 # Number of instructions simulated +sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 593600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2515776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6204544 # Number of bytes read from this memory -system.physmem.bytes_read::total 9313920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 593600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 593600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6264768 # Number of bytes written to this memory -system.physmem.bytes_written::total 6264768 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39309 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96946 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145530 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97887 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97887 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17794132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75414505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 185991366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 279200003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17794132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17794132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 187796679 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 187796679 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 187796679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17794132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75414505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 185991366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 466996681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145530 # Number of read requests accepted -system.physmem.writeReqs 97887 # Number of write requests accepted -system.physmem.readBursts 145530 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97887 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9306560 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 6263296 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9313920 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6264768 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 583488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2505024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6203200 # Number of bytes read from this memory +system.physmem.bytes_read::total 9291712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 583488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 583488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6256128 # Number of bytes written to this memory +system.physmem.bytes_written::total 6256128 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39141 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96925 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145183 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97752 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97752 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17505911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75156177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 186109513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 278771602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17505911 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17505911 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 187697469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 187697469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 187697469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17505911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75156177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 186109513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 466469070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145183 # Number of read requests accepted +system.physmem.writeReqs 97752 # Number of write requests accepted +system.physmem.readBursts 145183 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97752 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9284992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 6254720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9291712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6256128 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9160 # Per bank write bursts -system.physmem.perBankRdBursts::1 9419 # Per bank write bursts -system.physmem.perBankRdBursts::2 9305 # Per bank write bursts -system.physmem.perBankRdBursts::3 9483 # Per bank write bursts -system.physmem.perBankRdBursts::4 9789 # Per bank write bursts -system.physmem.perBankRdBursts::5 9711 # Per bank write bursts -system.physmem.perBankRdBursts::6 9074 # Per bank write bursts -system.physmem.perBankRdBursts::7 9074 # Per bank write bursts -system.physmem.perBankRdBursts::8 9205 # Per bank write bursts -system.physmem.perBankRdBursts::9 8628 # Per bank write bursts -system.physmem.perBankRdBursts::10 8849 # Per bank write bursts -system.physmem.perBankRdBursts::11 8741 # Per bank write bursts -system.physmem.perBankRdBursts::12 8642 # Per bank write bursts -system.physmem.perBankRdBursts::13 8695 # Per bank write bursts -system.physmem.perBankRdBursts::14 8691 # Per bank write bursts -system.physmem.perBankRdBursts::15 8949 # Per bank write bursts -system.physmem.perBankWrBursts::0 5976 # Per bank write bursts -system.physmem.perBankWrBursts::1 6255 # Per bank write bursts -system.physmem.perBankWrBursts::2 6149 # Per bank write bursts -system.physmem.perBankWrBursts::3 6169 # Per bank write bursts -system.physmem.perBankWrBursts::4 6151 # Per bank write bursts -system.physmem.perBankWrBursts::5 6334 # Per bank write bursts -system.physmem.perBankWrBursts::6 6086 # Per bank write bursts -system.physmem.perBankWrBursts::7 6007 # Per bank write bursts -system.physmem.perBankWrBursts::8 5979 # Per bank write bursts -system.physmem.perBankWrBursts::9 6153 # Per bank write bursts -system.physmem.perBankWrBursts::10 6241 # Per bank write bursts -system.physmem.perBankWrBursts::11 5938 # Per bank write bursts -system.physmem.perBankWrBursts::12 6061 # Per bank write bursts -system.physmem.perBankWrBursts::13 6105 # Per bank write bursts -system.physmem.perBankWrBursts::14 6219 # Per bank write bursts -system.physmem.perBankWrBursts::15 6041 # Per bank write bursts +system.physmem.perBankRdBursts::0 9145 # Per bank write bursts +system.physmem.perBankRdBursts::1 9372 # Per bank write bursts +system.physmem.perBankRdBursts::2 9233 # Per bank write bursts +system.physmem.perBankRdBursts::3 9500 # Per bank write bursts +system.physmem.perBankRdBursts::4 9743 # Per bank write bursts +system.physmem.perBankRdBursts::5 9700 # Per bank write bursts +system.physmem.perBankRdBursts::6 9083 # Per bank write bursts +system.physmem.perBankRdBursts::7 8995 # Per bank write bursts +system.physmem.perBankRdBursts::8 9233 # Per bank write bursts +system.physmem.perBankRdBursts::9 8567 # Per bank write bursts +system.physmem.perBankRdBursts::10 8856 # Per bank write bursts +system.physmem.perBankRdBursts::11 8704 # Per bank write bursts +system.physmem.perBankRdBursts::12 8629 # Per bank write bursts +system.physmem.perBankRdBursts::13 8694 # Per bank write bursts +system.physmem.perBankRdBursts::14 8697 # Per bank write bursts +system.physmem.perBankRdBursts::15 8927 # Per bank write bursts +system.physmem.perBankWrBursts::0 5993 # Per bank write bursts +system.physmem.perBankWrBursts::1 6233 # Per bank write bursts +system.physmem.perBankWrBursts::2 6131 # Per bank write bursts +system.physmem.perBankWrBursts::3 6188 # Per bank write bursts +system.physmem.perBankWrBursts::4 6147 # Per bank write bursts +system.physmem.perBankWrBursts::5 6290 # Per bank write bursts +system.physmem.perBankWrBursts::6 6056 # Per bank write bursts +system.physmem.perBankWrBursts::7 6014 # Per bank write bursts +system.physmem.perBankWrBursts::8 6000 # Per bank write bursts +system.physmem.perBankWrBursts::9 6152 # Per bank write bursts +system.physmem.perBankWrBursts::10 6228 # Per bank write bursts +system.physmem.perBankWrBursts::11 5920 # Per bank write bursts +system.physmem.perBankWrBursts::12 6078 # Per bank write bursts +system.physmem.perBankWrBursts::13 6086 # Per bank write bursts +system.physmem.perBankWrBursts::14 6193 # Per bank write bursts +system.physmem.perBankWrBursts::15 6021 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33359040500 # Total gap between requests +system.physmem.totGap 33330641500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145530 # Read request sizes (log2) +system.physmem.readPktSize::6 145183 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97887 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 42093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4669 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97752 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 41867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 51877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,104 +197,101 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.072858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.491943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 238.713124 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52339 58.86% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22656 25.48% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4441 4.99% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1741 1.96% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1037 1.17% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 849 0.95% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 689 0.77% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 765 0.86% 95.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4410 4.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88927 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.598207 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.088924 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 187.219466 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.273178 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.551570 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 239.030923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52157 58.84% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22538 25.42% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4461 5.03% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1758 1.98% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1068 1.20% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 785 0.89% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 713 0.80% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 748 0.84% 95.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4421 4.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88649 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.566130 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.054973 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 187.117675 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5904 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.556251 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.512708 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.281856 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4715 79.77% 79.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 33 0.56% 80.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 741 12.54% 92.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 193 3.27% 96.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 104 1.76% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 53 0.90% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 34 0.58% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 17 0.29% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 11 0.19% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 4 0.07% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads -system.physmem.totQLat 7478329771 # Total ticks spent queuing -system.physmem.totMemAccLat 10204861021 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 727075000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51427.50 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.550381 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.508750 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.243905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4712 79.80% 79.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 29 0.49% 80.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 757 12.82% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 163 2.76% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 111 1.88% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 62 1.05% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 43 0.73% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 20 0.34% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.10% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads +system.physmem.totQLat 7425181339 # Total ticks spent queuing +system.physmem.totMemAccLat 10145393839 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 725390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51180.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70177.50 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 278.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 187.75 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 279.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 187.80 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 69930.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 278.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 187.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 278.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 187.70 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.65 # Data bus utilization in percentage +system.physmem.busUtil 3.64 # Data bus utilization in percentage system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing -system.physmem.readRowHits 118188 # Number of row buffer hits during reads -system.physmem.writeRowHits 36158 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.94 # Row buffer hit rate for writes -system.physmem.avgGap 137044.83 # Average gap between requests -system.physmem.pageHitRate 63.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 343556640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 187456500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 584859600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 318226320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2178671040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11869125390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9602419500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25084314990 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.005565 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15876395968 # Time in different power states -system.physmem_0.memoryStateTime::REF 1113840000 # Time in different power states +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing +system.physmem.readRowHits 117819 # Number of row buffer hits during reads +system.physmem.writeRowHits 36329 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.16 # Row buffer hit rate for writes +system.physmem.avgGap 137199.83 # Average gap between requests +system.physmem.pageHitRate 63.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 342679680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186978000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 582769200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 317714400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2176636800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11943657450 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9518358000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25068793530 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.242445 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15735797307 # Time in different power states +system.physmem_0.memoryStateTime::REF 1112800000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16366332782 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16476833443 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328413960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179194125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 548948400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315725040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2178671040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11416289175 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 9999644250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24966885990 # Total energy per rank (pJ) -system.physmem_1.averagePower 748.485148 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16542747198 # Time in different power states -system.physmem_1.memoryStateTime::REF 1113840000 # Time in different power states +system.physmem_1.actEnergy 327053160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178451625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 548121600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315264960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2176636800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11265215805 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 10113486000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24924229950 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.904367 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16730540892 # Time in different power states +system.physmem_1.memoryStateTime::REF 1112800000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15699981552 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15482244108 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17207670 # Number of BP lookups -system.cpu.branchPred.condPredicted 11518844 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648137 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9345275 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7675164 # Number of BTB hits +system.cpu.branchPred.lookups 17205793 # Number of BP lookups +system.cpu.branchPred.condPredicted 11516695 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648305 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9352037 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7676056 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.128819 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1873048 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101561 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.078974 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1873350 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101557 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -413,129 +410,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66718625 # number of cpu cycles simulated +system.cpu.numCycles 66661827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4981358 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88194612 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17207670 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9548212 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60206161 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322349 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5969 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 4979954 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88191186 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17205793 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9549406 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60159688 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322593 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6446 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13195 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22764676 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68972 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65867882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.694526 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296864 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 13285 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22768352 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 68999 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65820694 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.695691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296532 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20086614 30.50% 30.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8263984 12.55% 43.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9201027 13.97% 57.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28316257 42.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20039717 30.45% 30.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8265549 12.56% 43.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9200264 13.98% 56.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28315164 43.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65867882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257914 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.321889 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8560400 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19609685 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31575881 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5629864 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492052 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3179520 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171002 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101414286 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3048471 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492052 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13316863 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5341740 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 787564 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32235527 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13694136 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99203918 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 983561 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3871797 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 66642 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4317748 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5384160 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103925780 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457714134 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115415425 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 65820694 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258106 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.322964 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8562659 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19557917 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31575920 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5632021 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492177 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3179708 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171007 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101418024 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3051775 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492177 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13320782 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5331170 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 788978 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32236803 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13650784 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99206458 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 984473 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3857341 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 63915 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4307533 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5353775 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103928524 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457724306 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115417327 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10296554 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18650 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12695794 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24322207 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21994092 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1403605 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2365005 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98166864 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94891849 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 694587 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7518802 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20250811 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65867882 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.440639 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150059 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10299298 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18661 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18655 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12693692 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24322711 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21993814 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1396246 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2340033 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98168548 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34521 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94889336 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694958 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7520484 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20257229 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 735 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 65820694 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.441634 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150001 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17597825 26.72% 26.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17436284 26.47% 53.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17101122 25.96% 79.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11678255 17.73% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2053424 3.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 972 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17560123 26.68% 26.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17422684 26.47% 53.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17103546 25.99% 79.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11678791 17.74% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2054563 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 987 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65867882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65820694 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6717330 22.42% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 38 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11201861 37.39% 59.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12041280 40.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6715459 22.40% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11205581 37.37% 59.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12062957 40.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49497025 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89873 0.09% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49498174 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89865 0.09% 52.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.26% # Type of FU issued @@ -563,96 +560,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.26% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24063293 25.36% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21241620 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24060336 25.36% 77.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21240923 22.38% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94891849 # Type of FU issued -system.cpu.iq.rate 1.422269 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29960509 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315733 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286306469 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105731477 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93465742 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94889336 # Type of FU issued +system.cpu.iq.rate 1.423443 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29984036 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315990 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286278153 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105734805 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93465836 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124852240 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124873254 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1363033 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1363649 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1455945 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2039 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11790 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1438354 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1456449 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2030 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11752 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1438076 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 142055 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 176720 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 138616 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 176709 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492052 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 623106 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 467581 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98211247 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 492177 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 621288 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 454814 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98212928 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24322207 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21994092 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1655 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 463043 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11790 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 303168 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221686 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524854 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93974313 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23756309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 917536 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24322711 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21993814 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18601 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1642 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 450257 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11752 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303335 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221647 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524982 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93971179 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23753264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 918157 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9861 # number of nop insts executed -system.cpu.iew.exec_refs 44740784 # number of memory reference insts executed -system.cpu.iew.exec_branches 14252664 # Number of branches executed -system.cpu.iew.exec_stores 20984475 # Number of stores executed -system.cpu.iew.exec_rate 1.408517 # Inst execution rate -system.cpu.iew.wb_sent 93587501 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93465799 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44986533 # num instructions producing a value -system.cpu.iew.wb_consumers 76576760 # num instructions consuming a value +system.cpu.iew.exec_nop 9859 # number of nop insts executed +system.cpu.iew.exec_refs 44736876 # number of memory reference insts executed +system.cpu.iew.exec_branches 14252919 # Number of branches executed +system.cpu.iew.exec_stores 20983612 # Number of stores executed +system.cpu.iew.exec_rate 1.409670 # Inst execution rate +system.cpu.iew.wb_sent 93587571 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93465893 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44982416 # num instructions producing a value +system.cpu.iew.wb_consumers 76564206 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.400895 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587470 # average fanout of values written-back +system.cpu.iew.wb_rate 1.402090 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587512 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6538748 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6539953 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479015 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64808930 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.399315 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.164562 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 479186 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64761460 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.400341 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.165093 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31222194 48.18% 48.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16795938 25.92% 74.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4338232 6.69% 80.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4159188 6.42% 87.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1936724 2.99% 90.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1268170 1.96% 92.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 738929 1.14% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 579590 0.89% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3769965 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31172018 48.13% 48.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16800427 25.94% 74.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4337432 6.70% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4161423 6.43% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1935218 2.99% 90.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1264756 1.95% 92.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 739046 1.14% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 579471 0.89% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3771669 5.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64808930 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70913181 # Number of instructions committed -system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 64761460 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70913182 # Number of instructions committed +system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 43422000 # Number of memory references committed system.cpu.commit.loads 22866262 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13741485 # Number of branches committed +system.cpu.commit.branches 13741486 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 81528487 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47186010 52.03% 52.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47186011 52.03% 52.03% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction @@ -685,381 +682,380 @@ system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Cl system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction -system.cpu.commit.bw_lim_events 3769965 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158240550 # The number of ROB reads -system.cpu.rob.rob_writes 195514428 # The number of ROB writes -system.cpu.timesIdled 23835 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 850743 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70907629 # Number of Instructions Simulated -system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.940923 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.940923 # CPI: Total CPI of All Threads -system.cpu.ipc 1.062786 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.062786 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102271067 # number of integer regfile reads -system.cpu.int_regfile_writes 56793819 # number of integer regfile writes +system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction +system.cpu.commit.bw_lim_events 3771669 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158192582 # The number of ROB reads +system.cpu.rob.rob_writes 195517129 # The number of ROB writes +system.cpu.timesIdled 23763 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 841133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70907630 # Number of Instructions Simulated +system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.940122 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.940122 # CPI: Total CPI of All Threads +system.cpu.ipc 1.063692 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.063692 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102266688 # number of integer regfile reads +system.cpu.int_regfile_writes 56794481 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346093039 # number of cc regfile reads -system.cpu.cc_regfile_writes 38805147 # number of cc regfile writes -system.cpu.misc_regfile_reads 44210055 # number of misc regfile reads +system.cpu.cc_regfile_reads 346084159 # number of cc regfile reads +system.cpu.cc_regfile_writes 38805382 # number of cc regfile writes +system.cpu.misc_regfile_reads 44209334 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485079 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.744077 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40428139 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485591 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.255536 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 152734000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.744077 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997547 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485106 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.740457 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40427935 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485618 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.250487 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 152807000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.740457 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997540 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997540 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84616103 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84616103 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21501727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21501727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18833421 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18833421 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 61667 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 61667 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 84615616 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84615616 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21501539 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21501539 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18833357 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18833357 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 61715 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 61715 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40335148 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40335148 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40396815 # number of overall hits -system.cpu.dcache.overall_hits::total 40396815 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 552941 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 552941 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1016480 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1016480 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 67175 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 67175 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 40334896 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40334896 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40396611 # number of overall hits +system.cpu.dcache.overall_hits::total 40396611 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 552871 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 552871 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1016544 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1016544 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 67128 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 67128 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1569421 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1569421 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1636596 # number of overall misses -system.cpu.dcache.overall_misses::total 1636596 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9116754245 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9116754245 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14723087903 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14723087903 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5168250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5168250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23839842148 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23839842148 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23839842148 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23839842148 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054668 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054668 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1569415 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1569415 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1636543 # number of overall misses +system.cpu.dcache.overall_misses::total 1636543 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9102953011 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9102953011 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14661434456 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14661434456 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5113500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5113500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23764387467 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23764387467 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23764387467 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23764387467 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054410 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054410 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128842 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128842 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128843 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128843 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904569 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904569 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42033411 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42033411 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025071 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025071 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051208 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051208 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.521375 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.521375 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41904311 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904311 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42033154 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42033154 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025069 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025069 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051212 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051212 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.521006 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.521006 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.037452 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.037452 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038936 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038936 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16487.752301 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16487.752301 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14484.385234 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14484.385234 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9448.354662 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9448.354662 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15190.214830 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15190.214830 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14566.723949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14566.723949 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 97 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3023244 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 128456 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.818182 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.535249 # average number of cycles each access was blocked +system.cpu.dcache.overall_miss_rate::cpu.data 0.038935 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038935 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16464.876998 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16464.876998 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14422.823268 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14422.823268 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9348.263254 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9348.263254 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15142.194682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15142.194682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14521.089557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14521.089557 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3013610 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 128472 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23.457329 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 262833 # number of writebacks -system.cpu.dcache.writebacks::total 262833 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 253459 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 253459 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 867955 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 867955 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 264409 # number of writebacks +system.cpu.dcache.writebacks::total 264409 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 253375 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 253375 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868011 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 868011 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 547 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 547 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1121414 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1121414 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1121414 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1121414 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299482 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299482 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148525 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148525 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37595 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37595 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 448007 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 448007 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485602 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485602 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3044598863 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3044598863 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2289083292 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2289083292 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2038189218 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2038189218 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5333682155 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5333682155 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7371871373 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7371871373 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013579 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013579 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291791 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291791 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010691 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1121386 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1121386 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1121386 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1121386 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299496 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299496 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148533 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148533 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37600 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37600 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 448029 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 448029 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485629 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485629 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3035888114 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3035888114 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279411901 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279411901 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2033283784 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2033283784 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5315300015 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5315300015 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7348583799 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7348583799 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013580 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013580 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291828 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291828 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010692 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010692 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011553 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.011553 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10166.216544 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10166.216544 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15412.107672 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15412.107672 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54214.369411 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54214.369411 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11905.354503 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11905.354503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15180.891703 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15180.891703 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10136.656630 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10136.656630 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15346.164832 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15346.164832 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54076.696383 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54076.696383 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11863.740997 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11863.740997 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15132.094251 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15132.094251 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 322801 # number of replacements -system.cpu.icache.tags.tagsinuse 510.305225 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22431720 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323313 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.380817 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1103729250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.305225 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996690 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996690 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 322771 # number of replacements +system.cpu.icache.tags.tagsinuse 510.304013 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22435446 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323283 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.398781 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1099609250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.304013 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996688 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 352 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 354 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45852448 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45852448 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22431720 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22431720 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22431720 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22431720 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22431720 # number of overall hits -system.cpu.icache.overall_hits::total 22431720 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 332842 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 332842 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 332842 # 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mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055667 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055667 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080951 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060062 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080951 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.054876 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.054876 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028201 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059659 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028201 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080600 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.199496 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69610.297251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79439.189214 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77177.866275 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96760.706913 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13834.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13834.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74344.471100 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74344.471100 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69610.297251 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78367.340049 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76695.563910 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69610.297251 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78367.340049 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90719.765072 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.198990 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69779.012833 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79124.864270 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77000.288094 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96490.636919 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13667.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13667.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74306.149516 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74306.149516 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69779.012833 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78121.134641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76545.123938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69779.012833 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78121.134641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90510.811957 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 660352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 660352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 262833 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 151427 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 660341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 660341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 264409 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 151292 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148563 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148563 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646637 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234037 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1880674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20692032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47899136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68591168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 151438 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1223186 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.123797 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.329350 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148571 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148571 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1235667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1882243 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20690048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48001728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68691776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 151304 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1224624 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.123542 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.329058 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 1071759 87.62% 87.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 151427 12.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1073332 87.65% 87.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 151292 12.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1223186 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 798712500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1224624 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 801075000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486658187 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 486570693 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 734620345 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 734618165 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 137260 # Transaction distribution -system.membus.trans_dist::ReadResp 137260 # Transaction distribution -system.membus.trans_dist::Writeback 97887 # Transaction distribution +system.membus.trans_dist::ReadReq 137030 # Transaction distribution +system.membus.trans_dist::ReadResp 137030 # Transaction distribution +system.membus.trans_dist::Writeback 97752 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8270 # Transaction distribution -system.membus.trans_dist::ReadExResp 8270 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388959 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 388959 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15578688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15578688 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8153 # Transaction distribution +system.membus.trans_dist::ReadExResp 8153 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 388130 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15547840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15547840 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 243423 # Request fanout histogram +system.membus.snoop_fanout::samples 242941 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 243423 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 242941 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 243423 # Request fanout histogram -system.membus.reqLayer0.occupancy 692237323 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 242941 # Request fanout histogram +system.membus.reqLayer0.occupancy 691321050 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 758965490 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 757153835 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |