diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
| commit | 4bc7dfb697bd779b12f1fd95fbe72144ae134055 (patch) | |
| tree | 532cea8e118ac27336792282c7023bb1b2d01be4 /tests/long/se/50.vortex | |
| parent | cea1d14a937f27fa49423bd01eb900e578993a43 (diff) | |
| download | gem5-4bc7dfb697bd779b12f1fd95fbe72144ae134055.tar.xz | |
stats: Update MinorCPU regressions after accounting fix
Diffstat (limited to 'tests/long/se/50.vortex')
| -rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt | 1032 | ||||
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt | 1056 |
2 files changed, 1044 insertions, 1044 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index acacb719c..bd4df05db 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.059745 # Number of seconds simulated -sim_ticks 59744560000 # Number of ticks simulated -final_tick 59744560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059732 # Number of seconds simulated +sim_ticks 59731559000 # Number of ticks simulated +final_tick 59731559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 336953 # Simulator instruction rate (inst/s) -host_op_rate 336953 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 227629544 # Simulator tick rate (ticks/s) -host_mem_usage 304552 # Number of bytes of host memory used -host_seconds 262.46 # Real time elapsed on the host +host_inst_rate 330143 # Simulator instruction rate (inst/s) +host_op_rate 330143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 222980587 # Simulator tick rate (ticks/s) +host_mem_usage 304704 # Number of bytes of host memory used +host_seconds 267.88 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 517248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10147776 # Number of bytes read from this memory -system.physmem.bytes_read::total 10665024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 517248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 517248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7299008 # Number of bytes written to this memory -system.physmem.bytes_written::total 7299008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166641 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114047 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114047 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8657659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169852720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 178510378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8657659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8657659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122170253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122170253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122170253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8657659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169852720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 300680631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166641 # Number of read requests accepted -system.physmem.writeReqs 114047 # Number of write requests accepted -system.physmem.readBursts 166641 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114047 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10664448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10665024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7299008 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 516416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10147392 # Number of bytes read from this memory +system.physmem.bytes_read::total 10663808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 516416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 516416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7298880 # Number of bytes written to this memory +system.physmem.bytes_written::total 7298880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158553 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166622 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114045 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114045 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8645614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169883261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 178528874 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8645614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8645614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122194701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122194701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122194701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8645614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169883261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 300723576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166622 # Number of read requests accepted +system.physmem.writeReqs 114045 # Number of write requests accepted +system.physmem.readBursts 166622 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114045 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10663168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297280 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10663808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7298880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10464 # Per bank write bursts -system.physmem.perBankRdBursts::1 10514 # Per bank write bursts -system.physmem.perBankRdBursts::2 10315 # Per bank write bursts -system.physmem.perBankRdBursts::3 10095 # Per bank write bursts -system.physmem.perBankRdBursts::4 10432 # Per bank write bursts -system.physmem.perBankRdBursts::5 10431 # Per bank write bursts -system.physmem.perBankRdBursts::6 9850 # Per bank write bursts -system.physmem.perBankRdBursts::7 10303 # Per bank write bursts -system.physmem.perBankRdBursts::8 10594 # Per bank write bursts -system.physmem.perBankRdBursts::9 10644 # Per bank write bursts -system.physmem.perBankRdBursts::10 10596 # Per bank write bursts -system.physmem.perBankRdBursts::11 10260 # Per bank write bursts +system.physmem.perBankRdBursts::0 10463 # Per bank write bursts +system.physmem.perBankRdBursts::1 10512 # Per bank write bursts +system.physmem.perBankRdBursts::2 10314 # Per bank write bursts +system.physmem.perBankRdBursts::3 10093 # Per bank write bursts +system.physmem.perBankRdBursts::4 10430 # Per bank write bursts +system.physmem.perBankRdBursts::5 10428 # Per bank write bursts +system.physmem.perBankRdBursts::6 9849 # Per bank write bursts +system.physmem.perBankRdBursts::7 10305 # Per bank write bursts +system.physmem.perBankRdBursts::8 10593 # Per bank write bursts +system.physmem.perBankRdBursts::9 10642 # Per bank write bursts +system.physmem.perBankRdBursts::10 10591 # Per bank write bursts +system.physmem.perBankRdBursts::11 10259 # Per bank write bursts system.physmem.perBankRdBursts::12 10303 # Per bank write bursts -system.physmem.perBankRdBursts::13 10654 # Per bank write bursts +system.physmem.perBankRdBursts::13 10653 # Per bank write bursts system.physmem.perBankRdBursts::14 10528 # Per bank write bursts system.physmem.perBankRdBursts::15 10649 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts -system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::2 7256 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts -system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7178 # Per bank write bursts +system.physmem.perBankWrBursts::4 7125 # Per bank write bursts +system.physmem.perBankWrBursts::5 7180 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7080 # Per bank write bursts -system.physmem.perBankWrBursts::8 7224 # Per bank write bursts -system.physmem.perBankWrBursts::9 6940 # Per bank write bursts -system.physmem.perBankWrBursts::10 7097 # Per bank write bursts -system.physmem.perBankWrBursts::11 6990 # Per bank write bursts -system.physmem.perBankWrBursts::12 6967 # Per bank write bursts +system.physmem.perBankWrBursts::7 7091 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::9 6938 # Per bank write bursts +system.physmem.perBankWrBursts::10 7094 # Per bank write bursts +system.physmem.perBankWrBursts::11 6991 # Per bank write bursts +system.physmem.perBankWrBursts::12 6965 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts -system.physmem.perBankWrBursts::14 7284 # Per bank write bursts +system.physmem.perBankWrBursts::14 7283 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 59744533000 # Total gap between requests +system.physmem.totGap 59731532000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166641 # Read request sizes (log2) +system.physmem.readPktSize::6 166622 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114047 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114045 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6196 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 6985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7041 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 7057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -193,121 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.521940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.158907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.861003 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19447 35.57% 35.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11824 21.63% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5661 10.35% 67.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3636 6.65% 74.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2772 5.07% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2160 3.95% 83.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1686 3.08% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1520 2.78% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5967 10.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54673 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.740134 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.174119 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54759 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.975602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.612520 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.469121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19499 35.61% 35.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11959 21.84% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5687 10.39% 67.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3574 6.53% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2717 4.96% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2083 3.80% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1679 3.07% 86.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1528 2.79% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6033 11.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54759 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.742625 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.245058 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7015 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.245939 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.230597 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.737975 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6255 89.13% 89.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 17 0.24% 89.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 574 8.18% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 144 2.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 20 0.28% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7017 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.249109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.233383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.749815 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6248 89.04% 89.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 18 0.26% 89.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 569 8.11% 97.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 155 2.21% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 21 0.30% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.03% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7018 # Writes before turning the bus around for reads -system.physmem.totQLat 1983100250 # Total ticks spent queuing -system.physmem.totMemAccLat 5107450250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11901.08 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7017 # Writes before turning the bus around for reads +system.physmem.totQLat 1993187750 # Total ticks spent queuing +system.physmem.totMemAccLat 5117162750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11963.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30651.08 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 178.50 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 178.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30713.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 178.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 178.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.35 # Data bus utilization in percentage system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.05 # Average write queue length when enqueuing -system.physmem.readRowHits 144723 # Number of row buffer hits during reads -system.physmem.writeRowHits 81251 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.24 # Row buffer hit rate for writes -system.physmem.avgGap 212850.33 # Average gap between requests -system.physmem.pageHitRate 80.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199115280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108644250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 642735600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367778880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12699594585 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24706498500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42626547975 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.484810 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40950314500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1994980000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.13 # Average write queue length when enqueuing +system.physmem.readRowHits 144646 # Number of row buffer hits during reads +system.physmem.writeRowHits 81220 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.22 # Row buffer hit rate for writes +system.physmem.avgGap 212819.93 # Average gap between requests +system.physmem.pageHitRate 80.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199621800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108920625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 642564000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367681680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3901163760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12761553015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24642806250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42624311130 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.633365 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40844346250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1994460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16799112000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16889792000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214197480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116873625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 656962800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371031840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13192492680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24274131750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42727871055 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.180760 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40226086750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1994980000 # Time in different power states +system.physmem_1.actEnergy 214235280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116894250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 656728800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370960560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3901163760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13264546950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24201582750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42726112350 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.337777 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40104532750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1994460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17523103250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17629849250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14679718 # Number of BP lookups -system.cpu.branchPred.condPredicted 9498983 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 392764 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10434122 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6393495 # Number of BTB hits +system.cpu.branchPred.lookups 14669488 # Number of BP lookups +system.cpu.branchPred.condPredicted 9491497 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 392361 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10408467 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6389552 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.274873 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1709689 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 85822 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.388022 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1708748 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 85394 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20566953 # DTB read hits -system.cpu.dtb.read_misses 96874 # DTB read misses -system.cpu.dtb.read_acv 11 # DTB read access violations -system.cpu.dtb.read_accesses 20663827 # DTB read accesses -system.cpu.dtb.write_hits 14666692 # DTB write hits -system.cpu.dtb.write_misses 9419 # DTB write misses +system.cpu.dtb.read_hits 20569996 # DTB read hits +system.cpu.dtb.read_misses 97344 # DTB read misses +system.cpu.dtb.read_acv 10 # DTB read access violations +system.cpu.dtb.read_accesses 20667340 # DTB read accesses +system.cpu.dtb.write_hits 14665866 # DTB write hits +system.cpu.dtb.write_misses 9405 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14676111 # DTB write accesses -system.cpu.dtb.data_hits 35233645 # DTB hits -system.cpu.dtb.data_misses 106293 # DTB misses -system.cpu.dtb.data_acv 11 # DTB access violations -system.cpu.dtb.data_accesses 35339938 # DTB accesses -system.cpu.itb.fetch_hits 25640132 # ITB hits -system.cpu.itb.fetch_misses 5244 # ITB misses +system.cpu.dtb.write_accesses 14675271 # DTB write accesses +system.cpu.dtb.data_hits 35235862 # DTB hits +system.cpu.dtb.data_misses 106749 # DTB misses +system.cpu.dtb.data_acv 10 # DTB access violations +system.cpu.dtb.data_accesses 35342611 # DTB accesses +system.cpu.itb.fetch_hits 25629903 # ITB hits +system.cpu.itb.fetch_misses 5247 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25645376 # ITB accesses +system.cpu.itb.fetch_accesses 25635150 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -321,81 +321,81 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 119489120 # number of cpu cycles simulated +system.cpu.numCycles 119463118 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1100288 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1109771 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.351105 # CPI: cycles per instruction -system.cpu.ipc 0.740135 # IPC: instructions per cycle -system.cpu.tickCycles 91601603 # Number of cycles that the object actually ticked -system.cpu.idleCycles 27887517 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 200784 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.582702 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34615842 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204880 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.956667 # Average number of references to valid blocks. +system.cpu.cpi 1.350811 # CPI: cycles per instruction +system.cpu.ipc 0.740296 # IPC: instructions per cycle +system.cpu.tickCycles 91541167 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27921951 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200768 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.577182 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616116 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204864 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.971200 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 693853250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.582702 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993795 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993795 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.577182 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993793 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993793 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 678 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3372 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 679 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3369 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70175650 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70175650 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20282569 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20282569 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333273 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333273 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34615842 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34615842 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34615842 # number of overall hits -system.cpu.dcache.overall_hits::total 34615842 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89439 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89439 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280104 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280104 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369543 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369543 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369543 # number of overall misses -system.cpu.dcache.overall_misses::total 369543 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4793461000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4793461000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21859170750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21859170750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26652631750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26652631750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26652631750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26652631750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70176158 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70176158 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20282855 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20282855 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333261 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333261 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34616116 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616116 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34616116 # number of overall hits +system.cpu.dcache.overall_hits::total 34616116 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89415 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89415 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280116 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280116 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369531 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369531 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369531 # number of overall misses +system.cpu.dcache.overall_misses::total 369531 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4791422750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4791422750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21873540250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21873540250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26664963000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26664963000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26664963000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26664963000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372270 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372270 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34985385 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34985385 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34985385 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34985385 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 34985647 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34985647 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34985647 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34985647 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010563 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010563 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010563 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010563 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53594.751730 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53594.751730 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78039.480871 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 78039.480871 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72123.221790 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72123.221790 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.010562 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010562 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010562 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010562 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53586.341777 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53586.341777 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78087.436098 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78087.436098 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72158.933892 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72158.933892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72158.933892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72158.933892 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -404,102 +404,102 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168547 # number of writebacks -system.cpu.dcache.writebacks::total 168547 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28118 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28118 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136545 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136545 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164663 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164663 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164663 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61321 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61321 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143559 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143559 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204880 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204880 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204880 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204880 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2650982250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2650982250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10919810750 # 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number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43231.229921 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43231.229921 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76064.968062 # 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Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943568 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943568 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 152979 # number of replacements +system.cpu.icache.tags.tagsinuse 1932.259039 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25474875 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155027 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 164.325408 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42450985250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1932.259039 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943486 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51436170 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51436170 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25484225 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25484225 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25484225 # 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number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2574589242 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2574589242 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2574589242 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2574589242 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25629903 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25629903 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25629903 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25629903 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25629903 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25629903 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16607.253154 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16607.253154 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16607.253154 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16607.253154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16607.253154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16607.253154 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -508,123 +508,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155907 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 155907 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 155907 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 155907 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 155907 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 155907 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2348059258 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2348059258 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2348059258 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2348059258 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2348059258 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2348059258 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006081 # 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number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 155028 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 155028 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 155028 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 155028 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 155028 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2338939258 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2338939258 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2338939258 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2338939258 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2338939258 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2338939258 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15087.205266 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15087.205266 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15087.205266 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15087.205266 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8070 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158553 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166623 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 539590750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1887128000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2426718750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9017256750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9017256750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 539590750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10904384750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11443975500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 539590750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10904384750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11443975500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.052055 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.451418 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165218 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911650 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911650 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.052055 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773943 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.462981 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.052055 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773943 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.462981 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66863.785626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68198.764049 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67897.337791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68896.080057 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68896.080057 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66863.785626 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68774.383014 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68681.847644 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66863.785626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68774.383014 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68681.847644 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 217227 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 217226 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143560 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578307 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 890120 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9977984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33877312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 216326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 216325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168537 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143566 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143566 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 310055 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 888320 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9921728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33819392 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 529334 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 528429 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 529334 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 528429 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 529334 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 433214000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 528429 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 432751500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 235419242 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 234095242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343262500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 343202250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35759 # Transaction distribution -system.membus.trans_dist::ReadResp 35759 # Transaction distribution -system.membus.trans_dist::Writeback 114047 # Transaction distribution +system.membus.trans_dist::ReadReq 35740 # Transaction distribution +system.membus.trans_dist::ReadResp 35740 # Transaction distribution +system.membus.trans_dist::Writeback 114045 # Transaction distribution system.membus.trans_dist::ReadExReq 130882 # Transaction distribution system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447329 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447329 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17964032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17964032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447289 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17962688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280688 # Request fanout histogram +system.membus.snoop_fanout::samples 280667 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280688 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 280667 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280688 # Request fanout histogram -system.membus.reqLayer0.occupancy 817068000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 280667 # Request fanout histogram +system.membus.reqLayer0.occupancy 816993000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 879892750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 879772000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 12a478a63..c3c27d986 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057717 # Number of seconds simulated -sim_ticks 57716694500 # Number of ticks simulated -final_tick 57716694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057148 # Number of seconds simulated +sim_ticks 57147901500 # Number of ticks simulated +final_tick 57147901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 194770 # Simulator instruction rate (inst/s) -host_op_rate 249082 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158520150 # Simulator tick rate (ticks/s) -host_mem_usage 322420 # Number of bytes of host memory used -host_seconds 364.10 # Real time elapsed on the host +host_inst_rate 198372 # Simulator instruction rate (inst/s) +host_op_rate 253689 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 159860838 # Simulator tick rate (ticks/s) +host_mem_usage 323444 # Number of bytes of host memory used +host_seconds 357.49 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 324096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372992 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372992 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128867 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83953 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83953 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5615290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 137280765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 142896056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5615290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5615290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 93092511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 93092511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 93092511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5615290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 137280765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 235988567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128867 # Number of read requests accepted -system.physmem.writeReqs 83953 # Number of write requests accepted -system.physmem.readBursts 128867 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83953 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247488 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372992 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 324160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7923136 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324160 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123799 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5672299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138642641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144314940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5672299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5672299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94015701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94015701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94015701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5672299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138642641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 238330641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128864 # Number of read requests accepted +system.physmem.writeReqs 83950 # Number of write requests accepted +system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 5370816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8159 # Per bank write bursts -system.physmem.perBankRdBursts::1 8373 # Per bank write bursts -system.physmem.perBankRdBursts::2 8230 # Per bank write bursts +system.physmem.perBankRdBursts::0 8158 # Per bank write bursts +system.physmem.perBankRdBursts::1 8375 # Per bank write bursts +system.physmem.perBankRdBursts::2 8229 # Per bank write bursts system.physmem.perBankRdBursts::3 8170 # Per bank write bursts -system.physmem.perBankRdBursts::4 8318 # Per bank write bursts -system.physmem.perBankRdBursts::5 8449 # Per bank write bursts +system.physmem.perBankRdBursts::4 8317 # Per bank write bursts +system.physmem.perBankRdBursts::5 8450 # Per bank write bursts system.physmem.perBankRdBursts::6 8089 # Per bank write bursts -system.physmem.perBankRdBursts::7 7972 # Per bank write bursts -system.physmem.perBankRdBursts::8 8072 # Per bank write bursts +system.physmem.perBankRdBursts::7 7970 # Per bank write bursts +system.physmem.perBankRdBursts::8 8070 # Per bank write bursts system.physmem.perBankRdBursts::9 7639 # Per bank write bursts system.physmem.perBankRdBursts::10 7818 # Per bank write bursts -system.physmem.perBankRdBursts::11 7829 # Per bank write bursts +system.physmem.perBankRdBursts::11 7830 # Per bank write bursts system.physmem.perBankRdBursts::12 7882 # Per bank write bursts -system.physmem.perBankRdBursts::13 7878 # Per bank write bursts -system.physmem.perBankRdBursts::14 7976 # Per bank write bursts -system.physmem.perBankRdBursts::15 8006 # Per bank write bursts -system.physmem.perBankWrBursts::0 5185 # Per bank write bursts -system.physmem.perBankWrBursts::1 5376 # Per bank write bursts +system.physmem.perBankRdBursts::13 7879 # Per bank write bursts +system.physmem.perBankRdBursts::14 7978 # Per bank write bursts +system.physmem.perBankRdBursts::15 8005 # Per bank write bursts +system.physmem.perBankWrBursts::0 5181 # Per bank write bursts +system.physmem.perBankWrBursts::1 5374 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts -system.physmem.perBankWrBursts::5 5518 # Per bank write bursts -system.physmem.perBankWrBursts::6 5200 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts +system.physmem.perBankWrBursts::5 5517 # Per bank write bursts +system.physmem.perBankWrBursts::6 5197 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts system.physmem.perBankWrBursts::9 5087 # Per bank write bursts -system.physmem.perBankWrBursts::10 5254 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5225 # Per bank write bursts +system.physmem.perBankWrBursts::15 5224 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57716659500 # Total gap between requests +system.physmem.totGap 57147867000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128867 # Read request sizes (log2) +system.physmem.readPktSize::6 128864 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83953 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83950 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116734 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5188 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,98 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38389 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.703274 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.932875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.531195 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12049 31.39% 31.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8167 21.27% 52.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4156 10.83% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2841 7.40% 70.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2531 6.59% 77.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1630 4.25% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1300 3.39% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1165 3.03% 88.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4550 11.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38389 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.991854 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 361.399783 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38410 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 354.471023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.710692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.512328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12078 31.44% 31.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8121 21.14% 52.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4196 10.92% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2833 7.38% 70.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2487 6.47% 77.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1687 4.39% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1308 3.41% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1147 2.99% 88.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4553 11.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38410 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.969750 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 360.703721 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5155 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.278898 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.261929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.774840 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4519 87.65% 87.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 87.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 495 9.60% 97.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 111 2.15% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 19 0.37% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 3 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads -system.physmem.totQLat 1645819000 # Total ticks spent queuing -system.physmem.totMemAccLat 4061944000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12772.15 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.272833 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.256213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.766988 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4532 87.88% 87.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 8 0.16% 88.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 487 9.44% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 109 2.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 13 0.25% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.08% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads +system.physmem.totQLat 1657207000 # Total ticks spent queuing +system.physmem.totMemAccLat 4073313250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12860.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31522.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 142.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 93.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 142.90 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 93.09 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31610.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 93.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 94.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.84 # Data bus utilization in percentage -system.physmem.busUtilRead 1.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.86 # Data bus utilization in percentage +system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing -system.physmem.readRowHits 112172 # Number of row buffer hits during reads -system.physmem.writeRowHits 62224 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes -system.physmem.avgGap 271199.41 # Average gap between requests -system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 151063920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82425750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512577000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272309040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11829284955 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24250601250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40867708635 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.132582 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40213391000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing +system.physmem.readRowHits 112198 # Number of row buffer hits during reads +system.physmem.writeRowHits 62160 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.04 # Row buffer hit rate for writes +system.physmem.avgGap 268534.34 # Average gap between requests +system.physmem.pageHitRate 81.93 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 150580080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82161750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512592600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11751586830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 23977725000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40479283620 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.378781 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39762160500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1908140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15571447750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15473270000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139058640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 75875250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492008400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 139769280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76263000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492016200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 271479600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11209873365 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24793944750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40751686725 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.122220 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41121510500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_1.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11244014370 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24422958750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40378823040 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.620851 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40500942500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1908140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14663764500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14734649500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14827145 # Number of BP lookups -system.cpu.branchPred.condPredicted 9920468 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 395132 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9565987 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6746821 # Number of BTB hits +system.cpu.branchPred.lookups 14823153 # Number of BP lookups +system.cpu.branchPred.condPredicted 9921447 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 393425 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9508830 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6745421 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.529272 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1718856 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.938496 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1716328 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,97 +404,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 115433389 # number of cpu cycles simulated +system.cpu.numCycles 114295803 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1146778 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1165738 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.627768 # CPI: cycles per instruction -system.cpu.ipc 0.614338 # IPC: instructions per cycle -system.cpu.tickCycles 96895866 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18537523 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156436 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.344190 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42626825 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.534753 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 829717250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.344190 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993004 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993004 # Average percentage of cache occupancy +system.cpu.cpi 1.611727 # CPI: cycles per instruction +system.cpu.ipc 0.620453 # IPC: instructions per cycle +system.cpu.tickCycles 95732462 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18563341 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156421 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.059654 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42628242 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160517 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.568395 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 829804250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.059654 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992934 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992934 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2911 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2909 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86020072 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86020072 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22868301 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22868301 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 84507 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 84507 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86023319 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86023319 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22869697 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22869697 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642191 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642191 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 84516 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 84516 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42510480 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42510480 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42594987 # number of overall hits -system.cpu.dcache.overall_hits::total 42594987 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 43690 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 43690 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 302945 # number of overall misses -system.cpu.dcache.overall_misses::total 302945 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1474342937 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1474342937 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16908501000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16908501000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18382843937 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18382843937 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18382843937 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18382843937 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22919834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22919834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42511888 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42511888 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42596404 # number of overall hits +system.cpu.dcache.overall_hits::total 42596404 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51738 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51738 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207710 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207710 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 43711 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 43711 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259448 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259448 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303159 # number of overall misses +system.cpu.dcache.overall_misses::total 303159 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1479377187 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1479377187 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16921529000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16921529000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18400906187 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18400906187 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18400906187 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18400906187 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22921435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22921435 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128197 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128197 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128227 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128227 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42769735 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42769735 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42897932 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42897932 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002248 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002248 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340804 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.340804 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28609.685774 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28609.685774 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81399.663974 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81399.663974 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70906.420077 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70906.420077 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60680.466543 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60680.466543 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 42771336 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42771336 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42899563 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42899563 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002257 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002257 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340888 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.340888 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007067 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007067 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28593.629189 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28593.629189 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81467.088729 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81467.088729 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70923.291708 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70923.291708 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60697.212311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60697.212311 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,110 +503,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks -system.cpu.dcache.writebacks::total 128445 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22036 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22036 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100688 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100688 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122724 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122724 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122724 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122724 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29497 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29497 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24001 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 24001 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136531 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136531 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558577313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 558577313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8440191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8440191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682073500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682073500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8998768313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8998768313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10680841813 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10680841813 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001287 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001287 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 128425 # number of writebacks +system.cpu.dcache.writebacks::total 128425 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22255 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22255 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100680 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100680 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122935 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122935 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122935 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122935 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29483 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29483 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24004 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 24004 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136513 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136513 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160517 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160517 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 559151063 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 559151063 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8446390250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8446390250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1684744250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1684744250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9005541313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9005541313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10690285563 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10690285563 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001286 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187220 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187220 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187199 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187199 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18936.749941 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18936.749941 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78855.232917 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78855.232917 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70083.475689 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70083.475689 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65910.073998 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65910.073998 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66534.035663 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66534.035663 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18965.202422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18965.202422 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78916.100626 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78916.100626 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70185.979420 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70185.979420 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65968.378931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65968.378931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66599.086471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66599.086471 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42847 # number of replacements -system.cpu.icache.tags.tagsinuse 1854.482229 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25082964 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44889 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 558.777518 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42924 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.595671 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24987535 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44966 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 555.698417 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1854.482229 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.905509 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.905509 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.595671 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904588 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904588 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 916 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50300597 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50300597 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25082964 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25082964 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25082964 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25082964 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25082964 # number of overall hits -system.cpu.icache.overall_hits::total 25082964 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44890 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44890 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44890 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 98454 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128425 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128425 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107030 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107030 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 44967 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160517 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205484 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 44967 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160517 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205484 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.112905 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403537 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.270797 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955601 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955601 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.112905 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771644 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.627489 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.112905 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771644 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.627489 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80213.708883 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85946.036416 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 84854.440944 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81047.999081 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81047.999081 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80213.708883 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81901.523470 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81835.065419 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80213.708883 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81901.523470 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81835.065419 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,114 +740,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83953 # number of writebacks -system.cpu.l2cache.writebacks::total 83953 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 83950 # number of writebacks +system.cpu.l2cache.writebacks::total 83950 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5065 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1578466750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1918274750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7004628000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7004628000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339808000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8583094750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8922902750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339808000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8583094750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8922902750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402314 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270236 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955584 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955584 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771204 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.627333 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.112831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771204 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.627333 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67089.437315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73338.602890 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72148.140138 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68484.825968 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68484.825968 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67089.437315 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69328.649144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69240.639647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67089.437315 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69328.649144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69240.639647 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5066 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21521 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26587 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102278 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102278 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5066 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123799 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128865 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5066 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123799 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128865 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 342787750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1580541000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1923328750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7010820250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7010820250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 342787750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8591361250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8934149000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 342787750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8591361250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8934149000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402359 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270045 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771252 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.627129 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771252 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.627129 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67664.380182 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73441.801032 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72340.946703 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68546.708481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68546.708481 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67664.380182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69397.662744 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69329.523144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67664.380182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69397.662744 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69329.523144 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98388 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98387 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89779 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449509 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 539288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2872896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21367424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98453 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89933 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449459 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 539392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2877824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21370112 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333867 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333909 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 333867 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 333909 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333867 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295378500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 333909 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295379500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68292739 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68407488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268237687 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268248937 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 26587 # Transaction distribution -system.membus.trans_dist::ReadResp 26587 # Transaction distribution -system.membus.trans_dist::Writeback 83953 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341687 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 26586 # Transaction distribution +system.membus.trans_dist::ReadResp 26586 # Transaction distribution +system.membus.trans_dist::Writeback 83950 # Transaction distribution +system.membus.trans_dist::ReadExReq 102278 # Transaction distribution +system.membus.trans_dist::ReadExResp 102278 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341678 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341678 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212820 # Request fanout histogram +system.membus.snoop_fanout::samples 212814 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212820 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212814 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212820 # Request fanout histogram -system.membus.reqLayer0.occupancy 578469000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 212814 # Request fanout histogram +system.membus.reqLayer0.occupancy 578378500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 680054250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 680081000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |