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authorAli Saidi <saidi@eecs.umich.edu>2013-03-04 23:33:47 -0500
committerAli Saidi <saidi@eecs.umich.edu>2013-03-04 23:33:47 -0500
commit09b2430e95df4f744a000bac34100eeb9ebcb878 (patch)
tree1db0ab99b4186f15335a866fd7239ba51755b7d9 /tests/long/se/50.vortex
parentf205d83359dfb3c4f75159f83081b5e356c3c4b4 (diff)
downloadgem5-09b2430e95df4f744a000bac34100eeb9ebcb878.tar.xz
stats: update patches for branch predictor and fetch updates.
Diffstat (limited to 'tests/long/se/50.vortex')
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini21
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr1
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/o3-timing/simout10
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt1238
4 files changed, 637 insertions, 633 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 0d9336fbc..39e20487b 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -511,6 +511,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
@@ -527,7 +528,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -543,6 +544,7 @@ type=CoherentBus
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
@@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
index e45cd058f..b6a1a957f 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
+warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4]
hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index b7ae68a85..9f7f9be51 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -1,13 +1,11 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:59:12
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Mar 3 2013 21:21:53
+gem5 started Mar 4 2013 01:35:26
+gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 26275145500 because target called exit()
+Exiting @ tick 25578307500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index bd8287e69..6f25374e1 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,102 +1,102 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.025578 # Number of seconds simulated
-sim_ticks 25577832000 # Number of ticks simulated
-final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 25578307500 # Number of ticks simulated
+final_tick 25578307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 133487 # Simulator instruction rate (inst/s)
-host_op_rate 189436 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48151664 # Simulator tick rate (ticks/s)
-host_mem_usage 268312 # Number of bytes of host memory used
-host_seconds 531.19 # Real time elapsed on the host
+host_inst_rate 122516 # Simulator instruction rate (inst/s)
+host_op_rate 173866 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44194830 # Simulator tick rate (ticks/s)
+host_mem_usage 267056 # Number of bytes of host memory used
+host_seconds 578.76 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 100626876 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8241856 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5372416 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5372416 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 128779 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 83944 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 83944 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 11662599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 310563929 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 322226528 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 11662599 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 11662599 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 210041883 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 210041883 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 210041883 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 11662599 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 310563929 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 532268411 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128779 # Total number of read requests seen
-system.physmem.writeReqs 83944 # Total number of write requests seen
-system.physmem.cpureqs 213035 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 8241856 # Total number of bytes read from memory
-system.physmem.bytesWritten 5372416 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 8241856 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 5372416 # bytesWritten derated as per pkt->getSize()
+system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory
+system.physmem.bytes_read::total 8241536 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5372288 # Number of bytes written to this memory
+system.physmem.bytes_written::total 5372288 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 128774 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 83942 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 83942 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 11654876 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 310553151 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 322208027 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 11654876 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 11654876 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 210032974 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 210032974 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 210032974 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 11654876 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 310553151 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 532241001 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 128775 # Total number of read requests seen
+system.physmem.writeReqs 83942 # Total number of write requests seen
+system.physmem.cpureqs 213036 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 8241536 # Total number of bytes read from memory
+system.physmem.bytesWritten 5372288 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 8241536 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 5372288 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 7976 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 8188 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 8062 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 8171 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 319 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 7977 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 8191 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 8064 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 8161 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 8170 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 8108 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 7991 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 7993 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 8127 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 8038 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 7985 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 7996 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 7987 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 8126 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 8035 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 7981 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 7987 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 5141 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::0 5142 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 5371 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 5372 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 5263 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 5277 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 5350 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 5125 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 5133 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 5152 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 25577735000 # Total gap between requests
+system.physmem.totGap 25578289000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 128779 # Categorize read packet sizes
+system.physmem.readPktSize::6 128775 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 83944 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 83942 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 70073 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 56517 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2103 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -124,11 +124,11 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3546 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3640 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3648 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see
@@ -139,53 +139,53 @@ system.physmem.wrQLenPdf::11 3650 # Wh
system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 104 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests
-system.physmem.totBusLat 643885000 # Total cycles spent in databus access
-system.physmem.totBankLat 1400217500 # Total cycles spent in bank access
-system.physmem.avgQLat 24884.85 # Average queueing delay per request
-system.physmem.avgBankLat 10873.20 # Average bank access latency per request
+system.physmem.totQLat 3208033250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 5250782000 # Sum of mem lat for all requests
+system.physmem.totBusLat 643865000 # Total cycles spent in databus access
+system.physmem.totBankLat 1398883750 # Total cycles spent in bank access
+system.physmem.avgQLat 24912.31 # Average queueing delay per request
+system.physmem.avgBankLat 10863.18 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 40758.05 # Average memory access latency
-system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 210.04 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 40775.49 # Average memory access latency
+system.physmem.avgRdBW 322.21 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 210.03 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 322.21 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 210.03 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 4.16 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.21 # Average read queue length over time
-system.physmem.avgWrQLen 9.73 # Average write queue length over time
-system.physmem.readRowHits 116758 # Number of row buffer hits during reads
-system.physmem.writeRowHits 52879 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 9.59 # Average write queue length over time
+system.physmem.readRowHits 116753 # Number of row buffer hits during reads
+system.physmem.writeRowHits 52875 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes
-system.physmem.avgGap 120239.63 # Average gap between requests
-system.cpu.branchPred.lookups 16629564 # Number of BP lookups
-system.cpu.branchPred.condPredicted 12762911 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 603280 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 10503277 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7769578 # Number of BTB hits
+system.physmem.avgGap 120245.63 # Average gap between requests
+system.cpu.branchPred.lookups 16623364 # Number of BP lookups
+system.cpu.branchPred.condPredicted 12760071 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 602765 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 10462695 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7764975 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 73.972894 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1825196 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 113459 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 74.215821 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1825729 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 113390 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -229,136 +229,136 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 51155665 # number of cpu cycles simulated
+system.cpu.numCycles 51156616 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 12528030 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 85177625 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16623364 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9590704 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21186632 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2363015 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 10581483 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 556 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11675113 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 179601 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 46030680 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.591102 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.335075 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1466538 3.19% 70.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1380808 3.00% 73.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 959441 2.08% 75.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1192836 2.59% 78.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24864286 54.02% 54.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2136700 4.64% 58.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1964680 4.27% 62.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2042011 4.44% 67.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1465176 3.18% 70.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1378812 3.00% 73.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 958023 2.08% 75.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1192746 2.59% 78.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10028246 21.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 46030680 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.324950 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.665036 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 14611647 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 8930047 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19464619 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1393461 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1630906 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3329793 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 104768 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 116826129 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 364020 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1630906 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 16323488 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2561901 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 880060 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19095828 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5538497 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 114955733 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 140 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 16360 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4684188 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 269 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 115265758 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 529627924 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 529622592 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 5332 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 274406 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 16133086 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 20210 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 20206 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13085457 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29620481 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 22434207 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 3897313 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 4409985 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 111515856 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 35838 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 107234062 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 271666 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10778201 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 25823888 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 2052 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 46030680 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.329622 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.987561 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10772740 23.40% 23.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 8089543 17.57% 40.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7436956 16.16% 57.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7132439 15.49% 72.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5411666 11.76% 84.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3908589 8.49% 92.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1839107 4.00% 96.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 868081 1.89% 98.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 571559 1.24% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 46030680 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 112263 4.55% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1357458 55.03% 59.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 996979 40.42% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 56638968 52.80% 52.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 91700 0.09% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 56624593 52.80% 52.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 91608 0.09% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 212 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 187 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued
@@ -384,292 +384,292 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 28903478 26.95% 79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21630689 20.17% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 28897959 26.95% 79.84% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21619708 20.16% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued
-system.cpu.iq.rate 2.096836 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 107234062 # Type of FU issued
+system.cpu.iq.rate 2.096191 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2466700 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.023003 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 263236655 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 122357738 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 105553758 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 515 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes
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+system.cpu.iq.int_alu_accesses 109700502 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2321749 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6850 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30026 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1892744 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2313373 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 29813 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1878469 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 507 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute
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+system.cpu.iew.iewBlockCycles 1049242 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 45608 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 111561445 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewDispLoadInsts 29620481 # Number of dispatched load instructions
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+system.cpu.iew.iewDispNonSpecInsts 19918 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 6795 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 5249 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 29813 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 391440 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 181697 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 573137 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 106207608 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 28598944 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1026454 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9761 # number of nop insts executed
-system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14602542 # Number of branches executed
-system.cpu.iew.exec_stores 21344564 # Number of stores executed
-system.cpu.iew.exec_rate 2.076700 # Inst execution rate
-system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 53282087 # num instructions producing a value
-system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value
+system.cpu.iew.exec_nop 9751 # number of nop insts executed
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+system.cpu.iew.exec_rate 2.076127 # Inst execution rate
+system.cpu.iew.wb_sent 105772826 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 105553928 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 53290488 # num instructions producing a value
+system.cpu.iew.wb_consumers 103570522 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.063349 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.514533 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 10929916 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::mean 2.266508 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.764024 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 15322992 34.51% 34.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11640164 26.22% 60.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3466305 7.81% 68.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2879897 6.49% 75.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1880990 4.24% 79.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1948005 4.39% 83.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 685170 1.54% 85.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 565050 1.27% 86.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6011201 13.54% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 44399774 # Number of insts commited each cycle
system.cpu.commit.committedInsts 70913181 # Number of instructions committed
system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 47862846 # Number of memory references committed
system.cpu.commit.loads 27307108 # Number of loads committed
system.cpu.commit.membars 15920 # Number of memory barriers committed
-system.cpu.commit.branches 13741505 # Number of branches committed
+system.cpu.commit.branches 13741485 # Number of branches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6011201 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 149959530 # The number of ROB reads
-system.cpu.rob.rob_writes 224865260 # The number of ROB writes
-system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 149925618 # The number of ROB reads
+system.cpu.rob.rob_writes 224764611 # The number of ROB writes
+system.cpu.timesIdled 74074 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5125936 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70907629 # Number of Instructions Simulated
system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
-system.cpu.cpi 0.721441 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 511661173 # number of integer regfile reads
-system.cpu.int_regfile_writes 103341311 # number of integer regfile writes
-system.cpu.fp_regfile_reads 804 # number of floating regfile reads
-system.cpu.fp_regfile_writes 688 # number of floating regfile writes
-system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads
+system.cpu.cpi 0.721454 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.721454 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.386089 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.386089 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 511542927 # number of integer regfile reads
+system.cpu.int_regfile_writes 103323311 # number of integer regfile writes
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+system.cpu.misc_regfile_reads 49174075 # number of misc regfile reads
system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
-system.cpu.icache.replacements 28586 # number of replacements
-system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use
-system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks.
+system.cpu.icache.replacements 28620 # number of replacements
+system.cpu.icache.tagsinuse 1814.212486 # Cycle average of tags in use
+system.cpu.icache.total_refs 11640356 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 30656 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 379.708899 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 11645446 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 11645446 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 11645446 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 11645446 # number of overall hits
-system.cpu.icache.overall_hits::total 11645446 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 34686 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 34686 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 34686 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses
-system.cpu.icache.overall_misses::total 34686 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11680132 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11680132 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11680132 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002970 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.002970 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked
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+system.cpu.icache.ReadReq_misses::cpu.inst 34752 # number of ReadReq misses
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+system.cpu.icache.overall_misses::total 34752 # number of overall misses
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+system.cpu.icache.ReadReq_accesses::cpu.inst 11675113 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11675113 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11675113 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11675113 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 11675113 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002977 # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21065.176105 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21065.176105 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21065.176105 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21065.176105 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21065.176105 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21065.176105 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 767 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 30.440000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 31.958333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3741 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 3741 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 3741 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34100.965093 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34100.965093 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62205.290202 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62205.290202 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28822.222222 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28822.222222 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 60156.592009 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60156.592009 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 5240 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 121 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.352459 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.305785 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks
-system.cpu.dcache.writebacks::total 129109 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 129088 # number of writebacks
+system.cpu.dcache.writebacks::total 129088 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69028 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 69028 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475364 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1475364 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107343 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 162756 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data 1544392 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1544392 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1544392 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1544392 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55416 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55416 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 162748 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 162748 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 162748 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 162748 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1874890000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1874890000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6816019991 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 6816019991 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8690909991 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8690909991 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8690909991 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8690909991 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33833.008517 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33833.008517 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63504.080712 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63504.080712 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------