diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/50.vortex | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/50.vortex')
21 files changed, 2250 insertions, 2254 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 738c09057..ef879d8e7 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 91ee744be..23e06e448 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:25:13 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:15:35 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 47232621500 because target called exit() +Exiting @ tick 47017029500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 0593fb6f2..0041bdcc8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.047233 # Number of seconds simulated -sim_ticks 47232621500 # Number of ticks simulated -final_tick 47232621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.047017 # Number of seconds simulated +sim_ticks 47017029500 # Number of ticks simulated +final_tick 47017029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102058 # Simulator instruction rate (inst/s) -host_op_rate 102058 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54566702 # Simulator tick rate (ticks/s) -host_mem_usage 223484 # Number of bytes of host memory used -host_seconds 865.59 # Real time elapsed on the host +host_inst_rate 156470 # Simulator instruction rate (inst/s) +host_op_rate 156470 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83276889 # Simulator tick rate (ticks/s) +host_mem_usage 227180 # Number of bytes of host memory used +host_seconds 564.59 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 602240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10564992 # Number of bytes read from this memory -system.physmem.bytes_read::total 11167232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 602240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 602240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7713024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7713024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165078 # Number of read requests responded to by this memory -system.physmem.num_reads::total 174488 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120516 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120516 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 12750510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 223679984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 236430493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 12750510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 12750510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163298664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163298664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163298664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 12750510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 223679984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 399729158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 515072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10272768 # Number of bytes read from this memory +system.physmem.bytes_read::total 10787840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 515072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 515072 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160512 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168560 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10955009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 218490366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 229445376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10955009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10955009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 157866205 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 157866205 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 157866205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10955009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 218490366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 387311580 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -42,18 +42,18 @@ system.cpu.dtb.read_hits 20277221 # DT system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 20367369 # DTB read accesses -system.cpu.dtb.write_hits 14736811 # DTB write hits +system.cpu.dtb.write_hits 14736814 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14744063 # DTB write accesses -system.cpu.dtb.data_hits 35014032 # DTB hits +system.cpu.dtb.write_accesses 14744066 # DTB write accesses +system.cpu.dtb.data_hits 35014035 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111432 # DTB accesses -system.cpu.itb.fetch_hits 12477897 # ITB hits -system.cpu.itb.fetch_misses 13095 # ITB misses +system.cpu.dtb.data_accesses 35111435 # DTB accesses +system.cpu.itb.fetch_hits 12478267 # ITB hits +system.cpu.itb.fetch_misses 13087 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12490992 # ITB accesses +system.cpu.itb.fetch_accesses 12491354 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 94465244 # number of cpu cycles simulated +system.cpu.numCycles 94034060 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18828991 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12440560 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5024685 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16222590 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5048183 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660950 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 18830633 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12442208 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5026177 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16228748 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5052031 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660951 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.118231 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8476014 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10352977 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74323677 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 31.130134 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8480322 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10350311 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74324480 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126642927 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65289 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126643730 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65335 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292919 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14127497 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064147 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4680877 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 233308 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4914185 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8858001 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.681953 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44775654 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292965 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14127744 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064158 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4682153 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 233524 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4915677 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8856497 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.692818 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44775466 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78066794 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78068863 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 305627 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24182755 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70282489 # Number of cycles cpu stages are processed. -system.cpu.activity 74.400368 # Percentage of cycles cpu is active +system.cpu.timesIdled 305152 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23747130 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70286930 # Number of cycles cpu stages are processed. +system.cpu.activity 74.746246 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.069329 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.064448 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.069329 # CPI: Total CPI of All Threads -system.cpu.ipc 0.935166 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.064448 # CPI: Total CPI of All Threads +system.cpu.ipc 0.939454 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.935166 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 41039233 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53426011 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 56.556262 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 51809989 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42655255 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.154443 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 51339314 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43125930 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.652695 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 72336276 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22128968 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.425513 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 48368266 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46096978 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 48.797818 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85310 # number of replacements -system.cpu.icache.tagsinuse 1887.040544 # Cycle average of tags in use -system.cpu.icache.total_refs 12359577 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87356 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.485153 # Average number of references to valid blocks. +system.cpu.ipc_total 0.939454 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 40602486 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53431574 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 56.821511 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 51377982 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42656078 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.362370 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 50907944 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43126116 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.862229 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 71905105 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22128955 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.532915 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47936936 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46097124 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 49.021731 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85298 # number of replacements +system.cpu.icache.tagsinuse 1887.307132 # Cycle average of tags in use +system.cpu.icache.total_refs 12360070 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87344 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.510235 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1887.040544 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.921407 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.921407 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12359577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12359577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12359577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12359577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12359577 # number of overall hits -system.cpu.icache.overall_hits::total 12359577 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118263 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118263 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118263 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118263 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118263 # number of overall misses -system.cpu.icache.overall_misses::total 118263 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2089534000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2089534000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2089534000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2089534000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2089534000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2089534000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12477840 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12477840 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12477840 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12477840 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12477840 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12477840 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009478 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009478 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009478 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009478 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009478 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009478 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17668.535383 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17668.535383 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17668.535383 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17668.535383 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1887.307132 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.921537 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.921537 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12360070 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12360070 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12360070 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12360070 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12360070 # number of overall hits +system.cpu.icache.overall_hits::total 12360070 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118149 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118149 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118149 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118149 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118149 # number of overall misses +system.cpu.icache.overall_misses::total 118149 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2012242500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2012242500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2012242500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2012242500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2012242500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2012242500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12478219 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12478219 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12478219 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12478219 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12478219 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12478219 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17031.396796 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17031.396796 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17031.396796 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17031.396796 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17031.396796 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17031.396796 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1485500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1223500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 122 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 109 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 12176.229508 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 11224.770642 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30907 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30907 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30907 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30907 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30907 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30907 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87356 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87356 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87356 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87356 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87356 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87356 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1366128500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1366128500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1366128500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1366128500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1366128500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1366128500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007001 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007001 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15638.633866 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15638.633866 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15638.633866 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15638.633866 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30805 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30805 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30805 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30805 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30805 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30805 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87344 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87344 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87344 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87344 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87344 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87344 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1308493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1308493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1308493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1308493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1308493500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1308493500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14980.920269 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14980.920269 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14980.920269 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14980.920269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14980.920269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14980.920269 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.126583 # Cycle average of tags in use -system.cpu.dcache.total_refs 34125996 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4073.021699 # Cycle average of tags in use +system.cpu.dcache.total_refs 34126085 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000230 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 167.000666 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 487962000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.126583 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994416 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994416 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180455 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180455 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945541 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945541 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34125996 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34125996 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34125996 # number of overall hits -system.cpu.dcache.overall_hits::total 34125996 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96183 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96183 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667836 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667836 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 764019 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 764019 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 764019 # number of overall misses -system.cpu.dcache.overall_misses::total 764019 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158611000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4158611000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35328865500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35328865500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39487476500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39487476500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39487476500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39487476500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 4073.021699 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994390 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994390 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180546 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180546 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945539 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945539 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34126085 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34126085 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34126085 # number of overall hits +system.cpu.dcache.overall_hits::total 34126085 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96092 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96092 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667838 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667838 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 763930 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 763930 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 763930 # number of overall misses +system.cpu.dcache.overall_misses::total 763930 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3967104000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3967104000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35310638000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35310638000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39277742000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39277742000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39277742000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39277742000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -260,40 +260,40 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004744 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004744 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004739 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004739 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021898 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021898 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43236.445110 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43236.445110 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52900.510754 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52900.510754 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51683.893332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51683.893332 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.021895 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021895 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021895 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021895 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41284.435749 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41284.435749 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52873.059035 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52873.059035 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51415.367900 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51415.367900 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51415.367900 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51415.367900 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6329431500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6330819000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124110 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124116 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50998.561760 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51007.275452 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161215 # number of writebacks -system.cpu.dcache.writebacks::total 161215 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35416 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35416 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524256 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524256 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559672 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559672 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559672 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559672 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 165812 # number of writebacks +system.cpu.dcache.writebacks::total 165812 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35325 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35325 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524258 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524258 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559583 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559583 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559583 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559583 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088876000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088876000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254482000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254482000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343358000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9343358000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343358000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9343358000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1914810500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1914810500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7237342000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7237342000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9152152500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9152152500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9152152500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9152152500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -318,98 +318,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34375.170734 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34375.170734 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.713888 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50525.713888 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45723.000582 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45723.000582 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31510.696595 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31510.696595 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50406.337930 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50406.337930 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44787.310310 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44787.310310 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44787.310310 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44787.310310 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 148111 # number of replacements -system.cpu.l2cache.tagsinuse 18671.690365 # Cycle average of tags in use -system.cpu.l2cache.total_refs 132979 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 173456 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.766644 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 136133 # number of replacements +system.cpu.l2cache.tagsinuse 28807.621629 # Cycle average of tags in use +system.cpu.l2cache.total_refs 146477 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 166996 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.877129 # 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number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 161215 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12270 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12270 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 77946 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 39269 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 117215 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 77946 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 39269 # number of overall hits -system.cpu.l2cache.overall_hits::total 117215 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 9410 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 42988 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 131500 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 131500 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 9410 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 165078 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 174488 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 9410 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 165078 # number of overall misses -system.cpu.l2cache.overall_misses::total 174488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 492013000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752923000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2244936000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854378000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6854378000 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 87356 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 87344 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 291703 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 87356 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 291691 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 87344 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 291703 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.107720 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554303 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.290591 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.914655 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.107720 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.807832 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.598170 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.107720 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.807832 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.598170 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.184910 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52204.508905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52222.387643 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.547529 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52124.547529 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52148.652056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52148.652056 # average overall miss latency +system.cpu.l2cache.overall_accesses::total 291691 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092141 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.486389 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.253595 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911511 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911511 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092141 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.785487 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.577872 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092141 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.785487 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.577872 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52282.057654 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52192.268531 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52211.532310 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52110.169556 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52110.169556 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52282.057654 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52125.239857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52132.727219 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52282.057654 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52125.239857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52132.727219 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.598170 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.598170 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40077.417641 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.244803 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.948823 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.931559 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40020.931559 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.921278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.921278 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 115975 # number of writebacks +system.cpu.l2cache.writebacks::total 115975 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8048 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29464 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37512 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131048 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131048 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8048 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160512 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168560 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8048 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160512 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168560 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 322504500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1178813500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1501318000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5243991500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5243991500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 322504500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6422805000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6745309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 322504500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6422805000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6745309500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486389 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253595 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911511 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911511 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785487 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.577872 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785487 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.577872 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40072.626740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40008.603720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40022.339518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.807185 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.807185 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40072.626740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40014.484898 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40017.260916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40072.626740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40014.484898 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40017.260916 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 51735fdde..6543d2325 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 331fe5e75..109541527 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:07:55 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:20:14 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 21302882000 because target called exit() +Exiting @ tick 21029927000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index f6437b65f..3719775b2 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021303 # Number of seconds simulated -sim_ticks 21302882000 # Number of ticks simulated -final_tick 21302882000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021030 # Number of seconds simulated +sim_ticks 21029927000 # Number of ticks simulated +final_tick 21029927000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166406 # Simulator instruction rate (inst/s) -host_op_rate 166406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44538843 # Simulator tick rate (ticks/s) -host_mem_usage 224724 # Number of bytes of host memory used -host_seconds 478.30 # Real time elapsed on the host +host_inst_rate 262496 # Simulator instruction rate (inst/s) +host_op_rate 262496 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69357396 # Simulator tick rate (ticks/s) +host_mem_usage 228212 # Number of bytes of host memory used +host_seconds 303.21 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 658624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10591744 # Number of bytes read from this memory -system.physmem.bytes_read::total 11250368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 658624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 658624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7713792 # Number of bytes written to this memory -system.physmem.bytes_written::total 7713792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165496 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175787 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120528 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120528 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 30917131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 497197703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 528114834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 30917131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 30917131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 362100865 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 362100865 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 362100865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 30917131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 497197703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 890215699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 558848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10293248 # Number of bytes read from this memory +system.physmem.bytes_read::total 10852096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 558848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 558848 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7426112 # Number of bytes written to this memory +system.physmem.bytes_written::total 7426112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8732 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160832 # Number of read requests responded to by this memory +system.physmem.num_reads::total 169564 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116033 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116033 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 26573939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 489457144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 516031083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 26573939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 26573939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 353121150 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 353121150 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 353121150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 26573939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 489457144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 869152232 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22551743 # DTB read hits -system.cpu.dtb.read_misses 221888 # DTB read misses -system.cpu.dtb.read_acv 31 # DTB read access violations -system.cpu.dtb.read_accesses 22773631 # DTB read accesses -system.cpu.dtb.write_hits 15815895 # DTB write hits -system.cpu.dtb.write_misses 41880 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 15857775 # DTB write accesses -system.cpu.dtb.data_hits 38367638 # DTB hits -system.cpu.dtb.data_misses 263768 # DTB misses -system.cpu.dtb.data_acv 34 # DTB access violations -system.cpu.dtb.data_accesses 38631406 # DTB accesses -system.cpu.itb.fetch_hits 14242802 # ITB hits -system.cpu.itb.fetch_misses 40881 # ITB misses +system.cpu.dtb.read_hits 22489459 # DTB read hits +system.cpu.dtb.read_misses 217588 # DTB read misses +system.cpu.dtb.read_acv 44 # DTB read access violations +system.cpu.dtb.read_accesses 22707047 # DTB read accesses +system.cpu.dtb.write_hits 15786869 # DTB write hits +system.cpu.dtb.write_misses 41269 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 15828138 # DTB write accesses +system.cpu.dtb.data_hits 38276328 # DTB hits +system.cpu.dtb.data_misses 258857 # DTB misses +system.cpu.dtb.data_acv 44 # DTB access violations +system.cpu.dtb.data_accesses 38535185 # DTB accesses +system.cpu.itb.fetch_hits 14133999 # ITB hits +system.cpu.itb.fetch_misses 38583 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14283683 # ITB accesses +system.cpu.itb.fetch_accesses 14172582 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,247 +67,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 42605767 # number of cpu cycles simulated +system.cpu.numCycles 42059856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16836861 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10841966 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 504890 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12277416 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7519870 # Number of BTB hits +system.cpu.BPredUnit.lookups 16727417 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10795081 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 475795 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12310974 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7475407 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 2023035 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 69381 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15349105 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 107382964 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16836861 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9542905 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19934365 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2235712 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4959568 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8744 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 326008 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14242802 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 231176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42192824 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.545053 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.166401 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1997632 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44950 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15195386 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106731428 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16727417 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9473039 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19807941 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2142694 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4831440 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 318425 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14133999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 219929 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 41712717 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.558726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.170110 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22258459 52.75% 52.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1558399 3.69% 56.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1415455 3.35% 59.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1535754 3.64% 63.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4212607 9.98% 73.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1888173 4.48% 77.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 696328 1.65% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1104060 2.62% 82.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7523589 17.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21904776 52.51% 52.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1546832 3.71% 56.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1409518 3.38% 59.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1517307 3.64% 63.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4200862 10.07% 73.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1863663 4.47% 77.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 687442 1.65% 79.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1091312 2.62% 82.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7491005 17.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42192824 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.395178 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.520386 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16468277 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4517812 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18984446 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 716137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1506152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3833098 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 111400 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 105432186 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 305241 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1506152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16967340 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2377848 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 83482 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19155996 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2102006 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103893842 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 209 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2243 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1985062 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62645887 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 125253216 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124792086 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 461130 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 41712717 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.397705 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.537608 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16282600 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4400388 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18871589 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 713555 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1444585 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3801857 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109351 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104838793 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305565 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1444585 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16762775 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2290284 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 81927 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19061483 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2071663 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103408033 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 177 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1890 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1956072 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62335498 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124694291 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124234000 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 460291 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10099006 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6339 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6334 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4415607 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23483376 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16437713 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1109953 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 422268 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91768592 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5634 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89301611 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 133191 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11574502 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5080166 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1051 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42192824 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.116512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.120688 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9788617 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5545 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5542 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4401091 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23371275 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16383320 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1113297 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 382577 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91444399 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5409 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89052036 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 123621 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11266129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4895344 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 826 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 41712717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.134889 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.120974 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13823160 32.76% 32.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6872678 16.29% 49.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5530993 13.11% 62.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4799446 11.38% 73.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4794506 11.36% 84.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2657744 6.30% 91.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1943834 4.61% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1324843 3.14% 98.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 445620 1.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13445094 32.23% 32.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6815105 16.34% 48.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5522712 13.24% 61.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4804260 11.52% 73.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4760133 11.41% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2656664 6.37% 91.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1952953 4.68% 95.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1309211 3.14% 98.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 446585 1.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42192824 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 41712717 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 129735 6.85% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 797111 42.11% 48.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 966009 51.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 129648 6.83% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 800646 42.16% 48.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 968600 51.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49865595 55.84% 55.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121283 0.14% 56.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121847 0.14% 56.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38973 0.04% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23075616 25.84% 82.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16034269 17.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49748943 55.87% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43836 0.05% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121395 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 122222 0.14% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38945 0.04% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22978145 25.80% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15998405 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89301611 # Type of FU issued -system.cpu.iq.rate 2.095998 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1892856 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021196 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222206616 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102943544 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87154270 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 615477 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 421862 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299078 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90886504 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 307963 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1459837 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89052036 # Type of FU issued +system.cpu.iq.rate 2.117269 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1898894 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021323 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221228638 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102311745 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87003241 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 610666 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420329 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 297405 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90645490 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305440 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1454782 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3206738 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5121 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17710 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1824336 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3094637 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5405 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17198 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1769943 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2474 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 2465 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1506152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1422947 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 61908 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101335985 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 260919 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23483376 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16437713 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5634 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42556 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17710 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 285901 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 175983 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 461884 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88268407 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22778571 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1033204 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1444585 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1378750 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 59667 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100988081 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 245674 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23371275 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16383320 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5409 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41936 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 387 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17198 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 251719 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 174529 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 426248 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88078074 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22710515 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 973962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9561759 # number of nop insts executed -system.cpu.iew.exec_refs 38636897 # number of memory reference insts executed -system.cpu.iew.exec_branches 15172966 # Number of branches executed -system.cpu.iew.exec_stores 15858326 # Number of stores executed -system.cpu.iew.exec_rate 2.071748 # Inst execution rate -system.cpu.iew.wb_sent 87882567 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87453348 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33493281 # num instructions producing a value -system.cpu.iew.wb_consumers 43663372 # num instructions consuming a value +system.cpu.iew.exec_nop 9538273 # number of nop insts executed +system.cpu.iew.exec_refs 38539046 # number of memory reference insts executed +system.cpu.iew.exec_branches 15143390 # Number of branches executed +system.cpu.iew.exec_stores 15828531 # Number of stores executed +system.cpu.iew.exec_rate 2.094113 # Inst execution rate +system.cpu.iew.wb_sent 87713914 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87300646 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33458604 # num instructions producing a value +system.cpu.iew.wb_consumers 43597958 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.052618 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767080 # average fanout of values written-back +system.cpu.iew.wb_rate 2.075629 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767435 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitCommittedOps 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9892654 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9531604 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 396008 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 40686672 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.171243 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.822339 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 368829 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 40268132 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.193811 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.828127 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17747243 43.62% 43.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7065292 17.37% 60.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3424426 8.42% 69.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2111790 5.19% 74.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2029147 4.99% 79.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1183341 2.91% 82.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1120057 2.75% 85.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 705485 1.73% 86.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5299891 13.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17348502 43.08% 43.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7047839 17.50% 60.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3405424 8.46% 69.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2108778 5.24% 74.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2046687 5.08% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1183274 2.94% 82.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1130602 2.81% 85.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 707287 1.76% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5289739 13.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 40686672 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 40268132 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5299891 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5289739 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132302765 # The number of ROB reads -system.cpu.rob.rob_writes 197976180 # The number of ROB writes -system.cpu.timesIdled 17931 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 412943 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 131533327 # The number of ROB reads +system.cpu.rob.rob_writes 197192647 # The number of ROB writes +system.cpu.timesIdled 15699 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 347139 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.535304 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.535304 # CPI: Total CPI of All Threads -system.cpu.ipc 1.868098 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.868098 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116852046 # number of integer regfile reads -system.cpu.int_regfile_writes 57987678 # number of integer regfile writes -system.cpu.fp_regfile_reads 254259 # number of floating regfile reads -system.cpu.fp_regfile_writes 241396 # number of floating regfile writes -system.cpu.misc_regfile_reads 38319 # number of misc regfile reads +system.cpu.cpi 0.528445 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.528445 # CPI: Total CPI of All Threads +system.cpu.ipc 1.892345 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.892345 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116616744 # number of integer regfile reads +system.cpu.int_regfile_writes 57879304 # number of integer regfile writes +system.cpu.fp_regfile_reads 252339 # number of floating regfile reads +system.cpu.fp_regfile_writes 241658 # number of floating regfile writes +system.cpu.misc_regfile_reads 38301 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 94879 # number of replacements -system.cpu.icache.tagsinuse 1931.404224 # Cycle average of tags in use -system.cpu.icache.total_refs 14141018 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 96927 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 145.893487 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 17852736000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1931.404224 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.943068 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.943068 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14141018 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14141018 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14141018 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14141018 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14141018 # number of overall hits -system.cpu.icache.overall_hits::total 14141018 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 101784 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 101784 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 101784 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 101784 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 101784 # number of overall misses -system.cpu.icache.overall_misses::total 101784 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 964559500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 964559500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 964559500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 964559500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 964559500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 964559500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14242802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14242802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14242802 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14242802 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14242802 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14242802 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007146 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007146 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007146 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007146 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007146 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007146 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9476.533640 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 9476.533640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 9476.533640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9476.533640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 9476.533640 # average overall miss latency +system.cpu.icache.replacements 93371 # number of replacements +system.cpu.icache.tagsinuse 1930.973067 # Cycle average of tags in use +system.cpu.icache.total_refs 14034495 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 95419 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.082814 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 17612659000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1930.973067 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942858 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942858 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14034495 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14034495 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14034495 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14034495 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14034495 # number of overall hits +system.cpu.icache.overall_hits::total 14034495 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 99504 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 99504 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 99504 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 99504 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 99504 # number of overall misses +system.cpu.icache.overall_misses::total 99504 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 887461000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 887461000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 887461000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 887461000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 887461000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 887461000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14133999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14133999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14133999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14133999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14133999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14133999 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007040 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007040 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007040 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007040 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007040 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007040 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8918.847484 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8918.847484 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8918.847484 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8918.847484 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8918.847484 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8918.847484 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,286 +390,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4856 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4856 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4856 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4856 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4856 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4856 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 96928 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 96928 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 96928 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 96928 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 96928 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 96928 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 566036000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 566036000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 566036000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 566036000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 566036000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 566036000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006805 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006805 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006805 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006805 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5839.757346 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5839.757346 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 5839.757346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5839.757346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 5839.757346 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4084 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4084 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4084 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4084 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4084 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4084 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95420 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 95420 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 95420 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 95420 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 95420 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 95420 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 511334500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 511334500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 511334500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 511334500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 511334500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 511334500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006751 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006751 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006751 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5358.776986 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5358.776986 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5358.776986 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5358.776986 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5358.776986 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5358.776986 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201683 # number of replacements -system.cpu.dcache.tagsinuse 4076.258401 # Cycle average of tags in use -system.cpu.dcache.total_refs 34409774 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205779 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.217131 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 158059000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.258401 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995180 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995180 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20831540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20831540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13578164 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13578164 # number of WriteReq hits +system.cpu.dcache.replacements 201494 # number of replacements +system.cpu.dcache.tagsinuse 4076.242085 # Cycle average of tags in use +system.cpu.dcache.total_refs 34356241 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205590 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.110467 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 156434000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.242085 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995176 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995176 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20778024 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20778024 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13578147 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13578147 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 70 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34409704 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34409704 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34409704 # number of overall hits -system.cpu.dcache.overall_hits::total 34409704 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 257782 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 257782 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1035213 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1035213 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1292995 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1292995 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1292995 # number of overall misses -system.cpu.dcache.overall_misses::total 1292995 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8279025500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8279025500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 34022399498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 34022399498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42301424998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42301424998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42301424998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42301424998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21089322 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21089322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 34356171 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34356171 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34356171 # number of overall hits +system.cpu.dcache.overall_hits::total 34356171 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 254081 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 254081 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1035230 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1035230 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1289311 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1289311 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1289311 # number of overall misses +system.cpu.dcache.overall_misses::total 1289311 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7948579000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7948579000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 34030906498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 34030906498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41979485498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41979485498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41979485498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41979485498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21032105 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21032105 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 70 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 70 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35702699 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35702699 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35702699 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35702699 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012223 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012223 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070840 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.070840 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036216 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036216 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036216 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036216 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32116.383223 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32116.383223 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32865.120027 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32865.120027 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32715.845767 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32715.845767 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 96500 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 35645482 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35645482 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35645482 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35645482 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012081 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012081 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070841 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.070841 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036170 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036170 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036170 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036170 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31283.641831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31283.641831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32872.797830 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32872.797830 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32559.627195 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32559.627195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32559.627195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32559.627195 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 100500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6433.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5911.764706 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161705 # number of writebacks -system.cpu.dcache.writebacks::total 161705 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 195431 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 195431 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891785 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 891785 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1087216 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1087216 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1087216 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1087216 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62351 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62351 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143428 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143428 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205779 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205779 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205779 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205779 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1281958000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1281958000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4735775500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4735775500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6017733500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6017733500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6017733500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6017733500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002957 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 166286 # number of writebacks +system.cpu.dcache.writebacks::total 166286 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191915 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 191915 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891806 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891806 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1083721 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1083721 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1083721 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1083721 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62166 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62166 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143424 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5863785000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5863785000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002956 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002956 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005764 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005764 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005764 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20560.343860 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20560.343860 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33018.486627 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33018.486627 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29243.671609 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29243.671609 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29243.671609 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005768 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005768 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005768 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31267.004955 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 116033 # number of writebacks +system.cpu.l2cache.writebacks::total 116033 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8732 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29871 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 38603 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130961 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130961 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160832 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 169564 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8732 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160832 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 169564 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 271655000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 927105000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1198760000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4112324500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4112324500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 271655000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5039429500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5311084500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 271655000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5039429500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5311084500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091511 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480519 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.244968 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913091 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913091 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091511 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782295 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.563317 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091511 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782295 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.563317 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31110.284013 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.958923 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31053.545061 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31401.138507 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31401.138507 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31110.284013 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31333.500174 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31322.005261 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31110.284013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31333.500174 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31322.005261 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 92307a506..db5db2a63 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout index 8571fc6fb..1808f3b15 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:21:00 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:25:28 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 134276988000 because target called exit() +Exiting @ tick 134036748000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 026fc581b..9facba206 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.134277 # Number of seconds simulated -sim_ticks 134276988000 # Number of ticks simulated -final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.134037 # Number of seconds simulated +sim_ticks 134036748000 # Number of ticks simulated +final_tick 134036748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1431789 # Simulator instruction rate (inst/s) -host_op_rate 1431788 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2176303972 # Simulator tick rate (ticks/s) -host_mem_usage 222880 # Number of bytes of host memory used -host_seconds 61.70 # Real time elapsed on the host +host_inst_rate 2004374 # Simulator instruction rate (inst/s) +host_op_rate 2004373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3041175629 # Simulator tick rate (ticks/s) +host_mem_usage 226164 # Number of bytes of host memory used +host_seconds 44.07 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 558272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10563648 # Number of bytes read from this memory -system.physmem.bytes_read::total 11121920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 558272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 558272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7712384 # Number of bytes written to this memory -system.physmem.bytes_written::total 7712384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8723 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165057 # Number of read requests responded to by this memory -system.physmem.num_reads::total 173780 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120506 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120506 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4157615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 78670576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 82828191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4157615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4157615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 57436379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 57436379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 57436379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4157615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 78670576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 140264570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10270528 # Number of bytes read from this memory +system.physmem.bytes_read::total 10755840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 485312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 485312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7421120 # Number of bytes written to this memory +system.physmem.bytes_written::total 7421120 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160477 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168060 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115955 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115955 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 3620738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 76624718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 80245456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3620738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3620738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55366309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55366309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55366309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3620738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 76624718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 135611765 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 268553976 # number of cpu cycles simulated +system.cpu.numCycles 268073496 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 268553976 # Number of busy cycles +system.cpu.num_busy_cycles 268073496 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.539157 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.404551 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913772 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913772 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1871.539157 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.913837 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.913837 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1436470000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1436470000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1436470000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1436470000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1436470000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1436470000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1388590000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1388590000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1388590000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1388590000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1388590000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1388590000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18793.107960 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18793.107960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18793.107960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18793.107960 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18166.701554 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18166.701554 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18166.701554 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18166.701554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18166.701554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18166.701554 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1207162000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1207162000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1207162000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1207162000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1207162000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1207162000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1159282000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1159282000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1159282000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1159282000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1159282000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1159282000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15793.107960 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15793.107960 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15793.107960 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15793.107960 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15166.701554 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15166.701554 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15166.701554 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15166.701554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15166.701554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15166.701554 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.827650 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.858373 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995815 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995815 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4078.827650 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995808 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995808 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2261000000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2261000000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7532210000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7532210000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9793210000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9793210000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9793210000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9793210000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2087582000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2087582000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7513268000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7513268000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9600850000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9600850000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9600850000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9600850000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37208.307277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37208.307277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52460.753040 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52460.753040 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47925.116470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47925.116470 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34354.441629 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34354.441629 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52328.824750 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52328.824750 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46983.762675 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46983.762675 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46983.762675 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46983.762675 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161222 # number of writebacks -system.cpu.dcache.writebacks::total 161222 # number of writebacks +system.cpu.dcache.writebacks::writebacks 165828 # number of writebacks +system.cpu.dcache.writebacks::total 165828 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7101476000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7101476000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9180178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9180178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9180178000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9180178000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1905284000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1905284000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7082534000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7082534000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987818000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8987818000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8987818000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8987818000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34208.307277 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34208.307277 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49460.753040 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49460.753040 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44925.116470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44925.116470 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.441629 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31354.441629 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49328.824750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49328.824750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43983.762675 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43983.762675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43983.762675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43983.762675 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 147405 # number of replacements -system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use -system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 135625 # number of replacements +system.cpu.l2cache.tagsinuse 29002.202656 # Cycle average of tags in use +system.cpu.l2cache.total_refs 136279 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 166491 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.818537 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15808.263557 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1305.254425 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1501.295351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.482430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.039833 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.045816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.568079 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 67713 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 27188 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 94901 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 161222 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 161222 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12099 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12099 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 67713 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 39287 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 107000 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 67713 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 39287 # number of overall hits -system.cpu.l2cache.overall_hits::total 107000 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8723 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.786677 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.050277 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.048123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.885077 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 68853 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31317 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 100170 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 165828 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 165828 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12550 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12550 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 68853 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 43867 # 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number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses @@ -328,17 +328,17 @@ system.cpu.l2cache.demand_accesses::total 280780 # n system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.114122 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.552579 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.308312 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.915732 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.915732 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.114122 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.807741 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.618919 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.114122 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.807741 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.618919 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099207 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.484630 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.269909 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912591 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912591 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099207 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.785328 # 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number of writebacks -system.cpu.l2cache.writebacks::total 120506 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8723 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 42301 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131479 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131479 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8723 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 165057 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 173780 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8723 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 165057 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 173780 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 348920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1692040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5259160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5259160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 348920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6602280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6951200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 348920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6602280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6951200000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.552579 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308312 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.915732 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.915732 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.618919 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.618919 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 115955 # number of writebacks +system.cpu.l2cache.writebacks::total 115955 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7583 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29449 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37032 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131028 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131028 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160477 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168060 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160477 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168060 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1177960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1481280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5241120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5241120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6419080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6722400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6419080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6722400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.484630 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269909 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912591 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912591 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785328 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.598547 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785328 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.598547 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 566c57286..33fd8bc7c 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index cb33c4c0f..462a53b1f 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:32:39 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:13:16 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24560764000 because target called exit() +Exiting @ tick 23981004500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 826f949e8..8d4101747 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024561 # Number of seconds simulated -sim_ticks 24560764000 # Number of ticks simulated -final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023981 # Number of seconds simulated +sim_ticks 23981004500 # Number of ticks simulated +final_tick 23981004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104807 # Simulator instruction rate (inst/s) -host_op_rate 148726 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36296181 # Simulator tick rate (ticks/s) -host_mem_usage 240672 # Number of bytes of host memory used -host_seconds 676.68 # Real time elapsed on the host -sim_insts 70920072 # Number of instructions simulated -sim_ops 100639320 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 367552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8319680 # Number of bytes read from this memory -system.physmem.bytes_read::total 8687232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 367552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 367552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5661632 # Number of bytes written to this memory -system.physmem.bytes_written::total 5661632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 129995 # Number of read requests responded to by this memory -system.physmem.num_reads::total 135738 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 88463 # Number of write requests responded to by this memory -system.physmem.num_writes::total 88463 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 14965007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 338738648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 353703655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 14965007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 14965007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 230515305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 230515305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 230515305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 14965007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 338738648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 584218960 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 169152 # Simulator instruction rate (inst/s) +host_op_rate 240031 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57193739 # Simulator tick rate (ticks/s) +host_mem_usage 242580 # Number of bytes of host memory used +host_seconds 419.29 # Real time elapsed on the host +sim_insts 70924419 # Number of instructions simulated +sim_ops 100643666 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8029184 # Number of bytes read from this memory +system.physmem.bytes_read::total 8356160 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417856 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125456 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130565 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84654 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84654 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13634792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 334814332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 348449124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13634792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13634792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 225922813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 225922813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 225922813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13634792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 334814332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 574371937 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +77,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 49121529 # number of cpu cycles simulated +system.cpu.numCycles 47962010 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17484643 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13346532 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 763895 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12042742 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8272877 # Number of BTB hits +system.cpu.BPredUnit.lookups 16947214 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12982117 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 655322 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11804628 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7961599 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1873235 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 186435 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13233353 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 89314081 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17484643 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10146112 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22235900 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3054378 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9993886 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 494 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12432222 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 242141 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47666513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.625620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.342151 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1880669 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114490 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12764738 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87540471 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16947214 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9842268 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21772804 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2768546 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10027678 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 361 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12061426 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 218802 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46590944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.639937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.350838 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25452916 53.40% 53.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2276272 4.78% 58.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2010669 4.22% 62.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2082167 4.37% 66.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1606372 3.37% 70.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1473384 3.09% 73.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1003270 2.10% 75.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1293693 2.71% 78.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10467770 21.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24839551 53.31% 53.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2175787 4.67% 57.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1999394 4.29% 62.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2026993 4.35% 66.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1551688 3.33% 69.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1408138 3.02% 72.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 990048 2.12% 75.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1240896 2.66% 77.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10358449 22.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47666513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.355947 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.818227 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15402794 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8395926 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20419082 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1357324 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2091387 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3552582 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 114889 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 122010152 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 381349 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2091387 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17235553 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2381046 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 774700 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19895179 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5288648 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 118965286 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 65 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 10051 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4471697 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 173 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 119289544 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 547314245 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 547305502 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8743 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99152581 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20136963 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50089 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 50062 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12897670 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30342934 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22764283 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3373932 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4070444 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 114201865 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 59946 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108885427 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 355885 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 13447173 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32642565 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 23673 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47666513 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.284317 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.003120 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 46590944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.353347 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.825204 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14883106 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8408681 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19993372 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1386692 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1919093 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3458129 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108409 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 120163882 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 373498 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1919093 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16645469 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2316120 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 802815 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19569476 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5337971 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117636894 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9686 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4512387 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 221 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117778889 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541771281 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541766916 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4365 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159536 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18619353 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37368 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37363 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12895568 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30067923 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22776958 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3590168 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4248242 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113315749 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51911 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108455143 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 350648 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12554662 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29999283 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14767 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46590944 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.327816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.997244 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11902735 24.97% 24.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8314690 17.44% 42.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7496951 15.73% 58.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7072171 14.84% 72.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5553695 11.65% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3902484 8.19% 92.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1926147 4.04% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 904880 1.90% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 592760 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11127507 23.88% 23.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8067707 17.32% 41.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7375197 15.83% 57.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7162683 15.37% 72.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5557871 11.93% 84.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3930157 8.44% 92.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1905355 4.09% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 881142 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 583325 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47666513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46590944 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112261 4.35% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1423319 55.12% 59.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1046695 40.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112830 4.40% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1425910 55.61% 60.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1025351 39.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57627292 52.92% 52.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 88925 0.08% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 277 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29380371 26.98% 79.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21788555 20.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57362458 52.89% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91498 0.08% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 129 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29209051 26.93% 79.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21792000 20.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108885427 # Type of FU issued -system.cpu.iq.rate 2.216654 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2582277 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023716 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 268374678 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127734912 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106613834 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 851 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 211 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 111467277 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 427 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2219770 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108455143 # Type of FU issued +system.cpu.iq.rate 2.261272 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2564091 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023642 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 266415556 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125949072 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106420629 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 111019028 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 206 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2223683 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3033338 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8348 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28761 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2206058 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2757457 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7931 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28755 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2217862 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 51 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2091387 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 991755 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 31052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 114342127 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 442332 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30342934 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22764283 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 43712 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1891 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1967 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28761 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 532244 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 266639 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 798883 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107583415 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28980389 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1302012 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1919093 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 944512 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 30820 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113447794 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342667 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30067923 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22776958 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35363 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1047 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28755 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 424789 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 263529 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 688318 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107242187 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28840669 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1212956 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80316 # number of nop insts executed -system.cpu.iew.exec_refs 50461236 # number of memory reference insts executed -system.cpu.iew.exec_branches 14752818 # Number of branches executed -system.cpu.iew.exec_stores 21480847 # Number of stores executed -system.cpu.iew.exec_rate 2.190148 # Inst execution rate -system.cpu.iew.wb_sent 106971474 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106614045 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53628736 # num instructions producing a value -system.cpu.iew.wb_consumers 104822222 # num instructions consuming a value +system.cpu.iew.exec_nop 80134 # number of nop insts executed +system.cpu.iew.exec_refs 50312690 # number of memory reference insts executed +system.cpu.iew.exec_branches 14662886 # Number of branches executed +system.cpu.iew.exec_stores 21472021 # Number of stores executed +system.cpu.iew.exec_rate 2.235982 # Inst execution rate +system.cpu.iew.wb_sent 106754958 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106420762 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53610539 # num instructions producing a value +system.cpu.iew.wb_consumers 104702454 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.170414 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511616 # average fanout of values written-back +system.cpu.iew.wb_rate 2.218855 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512028 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 70925624 # The number of committed instructions -system.cpu.commit.commitCommittedOps 100644872 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 13697900 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 36273 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 715054 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45575127 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.208329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.734720 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 70929971 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100649218 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 12799085 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37144 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 611847 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44671852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.253079 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.750865 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16228357 35.61% 35.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11797211 25.89% 61.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3508330 7.70% 69.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2972714 6.52% 75.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1972056 4.33% 80.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1932722 4.24% 84.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 698627 1.53% 85.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 551617 1.21% 87.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5913493 12.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15424353 34.53% 34.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11724908 26.25% 60.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3540913 7.93% 68.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2916552 6.53% 75.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1906207 4.27% 79.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1948042 4.36% 83.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 684228 1.53% 85.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 590770 1.32% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5935879 13.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45575127 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70925624 # Number of instructions committed -system.cpu.commit.committedOps 100644872 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 44671852 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929971 # Number of instructions committed +system.cpu.commit.committedOps 100649218 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47867821 # Number of memory references committed -system.cpu.commit.loads 27309596 # Number of loads committed +system.cpu.commit.refs 47869562 # Number of memory references committed +system.cpu.commit.loads 27310466 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13671115 # Number of branches committed +system.cpu.commit.branches 13671985 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91482735 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486211 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5913493 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5935879 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153979107 # The number of ROB reads -system.cpu.rob.rob_writes 230788170 # The number of ROB writes -system.cpu.timesIdled 64143 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1455016 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70920072 # Number of Instructions Simulated -system.cpu.committedOps 100639320 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70920072 # Number of Instructions Simulated -system.cpu.cpi 0.692632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692632 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443768 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443768 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 517371049 # number of integer regfile reads -system.cpu.int_regfile_writes 104514948 # number of integer regfile writes -system.cpu.fp_regfile_reads 1051 # number of floating regfile reads -system.cpu.fp_regfile_writes 886 # number of floating regfile writes -system.cpu.misc_regfile_reads 147913903 # number of misc regfile reads -system.cpu.misc_regfile_writes 36814 # number of misc regfile writes -system.cpu.icache.replacements 31518 # number of replacements -system.cpu.icache.tagsinuse 1822.469235 # Cycle average of tags in use -system.cpu.icache.total_refs 12397113 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 33561 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 369.390453 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 152158977 # The number of ROB reads +system.cpu.rob.rob_writes 228826081 # The number of ROB writes +system.cpu.timesIdled 61655 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1371066 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924419 # Number of Instructions Simulated +system.cpu.committedOps 100643666 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924419 # Number of Instructions Simulated +system.cpu.cpi 0.676241 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.676241 # CPI: Total CPI of All Threads +system.cpu.ipc 1.478762 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.478762 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516206868 # number of integer regfile reads +system.cpu.int_regfile_writes 104370444 # number of integer regfile writes +system.cpu.fp_regfile_reads 520 # number of floating regfile reads +system.cpu.fp_regfile_writes 444 # number of floating regfile writes +system.cpu.misc_regfile_reads 146052754 # number of misc regfile reads +system.cpu.misc_regfile_writes 38556 # number of misc regfile writes +system.cpu.icache.replacements 29824 # number of replacements +system.cpu.icache.tagsinuse 1820.810833 # Cycle average of tags in use +system.cpu.icache.total_refs 12028408 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 31867 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 377.456554 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1822.469235 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.889878 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.889878 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12397114 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12397114 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12397114 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12397114 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12397114 # number of overall hits -system.cpu.icache.overall_hits::total 12397114 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35108 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35108 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35108 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35108 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35108 # number of overall misses -system.cpu.icache.overall_misses::total 35108 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 406151000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 406151000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 406151000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 406151000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 406151000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002824 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002824 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002824 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11568.616839 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11568.616839 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11568.616839 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1820.810833 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.889068 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.889068 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12028408 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12028408 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12028408 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12028408 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12028408 # number of overall hits +system.cpu.icache.overall_hits::total 12028408 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33018 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33018 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33018 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33018 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33018 # number of overall misses +system.cpu.icache.overall_misses::total 33018 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 367424500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 367424500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 367424500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 367424500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 367424500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 367424500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12061426 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12061426 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12061426 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12061426 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12061426 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12061426 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002737 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002737 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002737 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11128.005936 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11128.005936 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11128.005936 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11128.005936 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,258 +401,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1474 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1474 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1474 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1474 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1474 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1474 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33634 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 33634 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 33634 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 33634 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 33634 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 33634 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268782500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002705 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002705 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002705 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7991.392638 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1111 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1111 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1111 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1111 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1111 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31907 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31907 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31907 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31907 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31907 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31907 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244055000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 244055000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244055000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 244055000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244055000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 244055000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002645 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002645 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002645 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7648.948507 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7648.948507 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158907 # number of replacements -system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use -system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.993836 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.993836 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26393302 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26393302 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18309799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18309799 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 19644 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 19644 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 18406 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 18406 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44703101 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44703101 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2434975500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 52525381000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 52525381000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 425000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 425000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54960356500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54960356500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54960356500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54960356500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26503495 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26503495 # 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number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20534 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20534 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19277 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19277 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44571602 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44571602 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44571602 # number of overall hits +system.cpu.dcache.overall_hits::total 44571602 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 105369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 105369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1548293 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1548293 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 39 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 39 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1653662 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1653662 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1653662 # number of overall misses +system.cpu.dcache.overall_misses::total 1653662 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2114831500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2114831500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 52578719498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 52578719498 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 447000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54693550998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54693550998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54693550998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54693550998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26375363 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26375363 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19679 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 19679 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 18406 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 18406 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004158 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.077587 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001779 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035602 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.035602 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22097.370069 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34105.131348 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12142.857143 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33303.352734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33303.352734 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20573 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20573 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19277 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19277 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46225264 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46225264 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46225264 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46225264 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003995 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003995 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078000 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078000 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001896 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001896 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.035774 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20070.718143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20070.718143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33959.153402 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33959.153402 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11461.538462 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11461.538462 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33074.201982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33074.201982 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19600 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123795 # number of writebacks -system.cpu.dcache.writebacks::total 123795 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54073 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54073 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1433145 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18700.810763 # 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number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 63 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 63 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102587 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102587 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5743 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 129995 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 135738 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5743 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 129995 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 135738 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 178439000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 852007500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1030446500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1955000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1955000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3195019500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3195019500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178439000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4047027000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4225466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178439000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4047027000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 4225466000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.488696 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.369828 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.851351 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.851351 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959483 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.959483 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.690575 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.171152 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.797501 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.690575 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.421315 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.746032 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31144.487118 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31129.573148 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 84654 # number of writebacks +system.cpu.l2cache.writebacks::total 84654 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 68 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 68 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5109 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23142 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 28251 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 37 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102314 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102314 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5109 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130565 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5109 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130565 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 158798500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 719908500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 878707000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1150000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1150000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3191239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3191239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158798500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3911148000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4069946500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158798500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3911148000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4069946500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415759 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.322780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.925000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.925000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771121 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.671096 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771121 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.671096 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31082.110002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31108.309567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31103.571555 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31190.643509 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31190.643509 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.110002 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31175.455937 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31171.803316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.110002 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31175.455937 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31171.803316 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index 311edc8c7..5344e06dd 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index f1623eafd..64d9d48cf 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:34:04 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:19:28 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 53932162000 because target called exit() +Exiting @ tick 53932157000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index b5b6453b4..875e92986 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.053932 # Number of seconds simulated -sim_ticks 53932162000 # Number of ticks simulated -final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 53932157000 # Number of ticks simulated +final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1760373 # Simulator instruction rate (inst/s) -host_op_rate 2498132 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1338828629 # Simulator tick rate (ticks/s) -host_mem_usage 228700 # Number of bytes of host memory used -host_seconds 40.28 # Real time elapsed on the host -sim_insts 70913189 # Number of instructions simulated -sim_ops 100632437 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 312580308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 106573346 # Number of bytes read from this memory -system.physmem.bytes_read::total 419153654 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 312580308 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 312580308 # Number of instructions bytes read from this memory +host_inst_rate 2430593 # Simulator instruction rate (inst/s) +host_op_rate 3449236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1848555696 # Simulator tick rate (ticks/s) +host_mem_usage 232076 # Number of bytes of host memory used +host_seconds 29.18 # Real time elapsed on the host +sim_insts 70913181 # Number of instructions simulated +sim_ops 100632428 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory +system.physmem.bytes_read::total 419153617 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 312580272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 312580272 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 78145077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27156253 # Number of read requests responded to by this memory -system.physmem.num_reads::total 105301330 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27156252 # Number of read requests responded to by this memory +system.physmem.num_reads::total 105301320 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5795805256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1976062929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7771868185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5795805256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5795805256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1458502832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1458502832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5795805256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3434565761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9230371017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 5795805126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1976063093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7771868220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5795805126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5795805126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1458502967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1458502967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5795805126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3434566060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9230371187 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 107864325 # number of cpu cycles simulated +system.cpu.numCycles 107864315 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70913189 # Number of instructions committed -system.cpu.committedOps 100632437 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses +system.cpu.committedInsts 70913181 # Number of instructions committed +system.cpu.committedOps 100632428 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls -system.cpu.num_int_insts 91472788 # number of integer instructions +system.cpu.num_func_calls 3311620 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10711742 # number of instructions that are conditional controls +system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 452177233 # number of times the integer registers were read -system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written +system.cpu.num_int_register_reads 452177195 # number of times the integer registers were read +system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_mem_refs 47862848 # number of memory refs -system.cpu.num_load_insts 27307109 # Number of load instructions +system.cpu.num_mem_refs 47862847 # number of memory refs +system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 107864325 # Number of busy cycles +system.cpu.num_busy_cycles 107864315 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 678b8b9b7..c08fcfcdd 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index d480c9ad1..b1460f18e 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:34:55 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:20:08 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 133117442000 because target called exit() +Exiting @ tick 132924820000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index f1e03b8eb..b1eb24a6a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133117 # Number of seconds simulated -sim_ticks 133117442000 # Number of ticks simulated -final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132925 # Number of seconds simulated +sim_ticks 132924820000 # Number of ticks simulated +final_tick 132924820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 828989 # Simulator instruction rate (inst/s) -host_op_rate 1175527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1568098699 # Simulator tick rate (ticks/s) -host_mem_usage 237868 # Number of bytes of host memory used -host_seconds 84.89 # Real time elapsed on the host -sim_insts 70373636 # Number of instructions simulated -sim_ops 99791663 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 294208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8276480 # Number of bytes read from this memory -system.physmem.bytes_read::total 8570688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 294208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 294208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5660736 # Number of bytes written to this memory -system.physmem.bytes_written::total 5660736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 129320 # Number of read requests responded to by this memory -system.physmem.num_reads::total 133917 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 88449 # Number of write requests responded to by this memory -system.physmem.num_writes::total 88449 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2210139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62174272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64384410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2210139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2210139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42524375 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42524375 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42524375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2210139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62174272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106908785 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 1112405 # Simulator instruction rate (inst/s) +host_op_rate 1577419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2101158995 # Simulator tick rate (ticks/s) +host_mem_usage 240528 # Number of bytes of host memory used +host_seconds 63.26 # Real time elapsed on the host +sim_insts 70373628 # Number of instructions simulated +sim_ops 99791654 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8003456 # Number of bytes read from this memory +system.physmem.bytes_read::total 8277184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 273728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 273728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5403392 # Number of bytes written to this memory +system.physmem.bytes_written::total 5403392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125054 # Number of read requests responded to by this memory +system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2059269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60210396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 62269665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2059269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2059269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40649985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40649985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40649985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2059269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60210396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 102919650 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,73 +77,73 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 266234884 # number of cpu cycles simulated +system.cpu.numCycles 265849640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373636 # Number of instructions committed -system.cpu.committedOps 99791663 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses +system.cpu.committedInsts 70373628 # Number of instructions committed +system.cpu.committedOps 99791654 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls -system.cpu.num_int_insts 91472788 # number of integer instructions +system.cpu.num_func_calls 3311620 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10711742 # number of instructions that are conditional controls +system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read -system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written +system.cpu.num_int_register_reads 533542872 # number of times the integer registers were read +system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_mem_refs 47862848 # number of memory refs -system.cpu.num_load_insts 27307109 # Number of load instructions +system.cpu.num_mem_refs 47862847 # number of memory refs +system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 266234884 # Number of busy cycles +system.cpu.num_busy_cycles 265849640 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.182852 # Cycle average of tags in use -system.cpu.icache.total_refs 78126170 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1736.286948 # Cycle average of tags in use +system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.182852 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847746 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847746 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 78126170 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126170 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126170 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126170 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126170 # number of overall hits -system.cpu.icache.overall_hits::total 78126170 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 1736.286948 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847796 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847796 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78126161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78126161 # number of overall hits +system.cpu.icache.overall_hits::total 78126161 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 457786000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 457786000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 457786000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 457786000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 457786000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 457786000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145078 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145078 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145078 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145078 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145078 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145078 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 444346000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 444346000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 444346000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 444346000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 444346000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 444346000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78145069 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78145069 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78145069 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24211.233340 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24211.233340 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24211.233340 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23500.423101 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23500.423101 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23500.423101 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23500.423101 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23500.423101 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23500.423101 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,46 +158,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 401062000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 401062000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 401062000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 401062000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 401062000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 401062000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387622000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 387622000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387622000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 387622000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387622000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 387622000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21211.233340 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20500.423101 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20500.423101 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20500.423101 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20500.423101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20500.423101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20500.423101 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use -system.cpu.dcache.total_refs 46862075 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4076.906689 # Cycle average of tags in use +system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.934010 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995345 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995345 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 27087368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27087368 # number of ReadReq hits +system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1079631000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.906689 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995339 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995339 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46830237 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46830237 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46830237 # number of overall hits -system.cpu.dcache.overall_hits::total 46830237 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits +system.cpu.dcache.overall_hits::total 46830236 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1862630000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1862630000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5808782000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5808782000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7671412000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7671412000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7671412000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7671412000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27140334 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27140334 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1695470000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1695470000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5796770000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5796770000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7492240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7492240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7492240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7492240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46990235 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46990235 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46990235 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46990235 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35166.521920 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35166.521920 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54271.451529 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54271.451529 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47946.924337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47946.924337 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32010.535060 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32010.535060 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54159.223410 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54159.223410 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46827.085339 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46827.085339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46827.085339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46827.085339 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 122808 # number of writebacks -system.cpu.dcache.writebacks::total 122808 # number of writebacks +system.cpu.dcache.writebacks::writebacks 127057 # number of writebacks +system.cpu.dcache.writebacks::total 127057 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1703732000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1703732000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5487686000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5487686000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7191418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7191418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7191418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7191418000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012246000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7012246000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012246000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7012246000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32166.521920 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32166.521920 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51271.451529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51271.451529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29010.535060 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29010.535060 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.223410 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.223410 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.085339 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.085339 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.085339 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.085339 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 113660 # number of replacements -system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use -system.cpu.l2cache.total_refs 61800 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.466454 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 96735 # number of replacements +system.cpu.l2cache.tagsinuse 28872.647154 # Cycle average of tags in use +system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16025.699940 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 701.722418 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1464.198671 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.489066 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021415 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.044684 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.555164 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14311 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 26273 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 40584 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 122808 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 122808 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4405 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4405 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14311 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 30678 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 44989 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14311 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 30678 # number of overall hits -system.cpu.l2cache.overall_hits::total 44989 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4597 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 26693 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 31290 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102627 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102627 # 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number of overall hits +system.cpu.l2cache.overall_hits::total 49575 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4277 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 22713 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26990 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102341 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102341 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4277 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 125054 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 129331 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4277 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 125054 # number of overall misses +system.cpu.l2cache.overall_misses::total 129331 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222404000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181076000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1403480000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321732000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5321732000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 222404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6502808000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6725212000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 222404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6502808000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6725212000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 122808 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 122808 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 127057 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 127057 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_accesses::total 178906 # n system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243125 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.503965 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.435345 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.958844 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.958844 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243125 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.808260 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.748533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243125 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.808260 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.748533 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.226201 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.428822 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.375518 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.956172 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.956172 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.226201 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.781597 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.722899 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.226201 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.781597 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.722899 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88449 # number of writebacks -system.cpu.l2cache.writebacks::total 88449 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4597 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 26693 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102627 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102627 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4597 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 129320 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 133917 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4597 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 129320 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 133917 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1067720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1251600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4105080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4105080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5172800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5356680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5172800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5356680000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.503965 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.435345 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.958844 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.958844 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.748533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.748533 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 84428 # number of writebacks +system.cpu.l2cache.writebacks::total 84428 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4277 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 22713 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26990 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102341 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102341 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125054 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 129331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4277 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125054 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 129331 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093640000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093640000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5173240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5173240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.428822 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.375518 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956172 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956172 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.722899 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.722899 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 3ca0a8939..480848980 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout index f3517e2c4..2acf8263c 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:59:31 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:58:54 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 202941992000 because target called exit() +Exiting @ tick 202680458000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 3b1cc6fcd..b1d40b1a6 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202942 # Number of seconds simulated -sim_ticks 202941992000 # Number of ticks simulated -final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202680 # Number of seconds simulated +sim_ticks 202680458000 # Number of ticks simulated +final_tick 202680458000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1325068 # Simulator instruction rate (inst/s) -host_op_rate 1342225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2000847198 # Simulator tick rate (ticks/s) -host_mem_usage 231252 # Number of bytes of host memory used -host_seconds 101.43 # Real time elapsed on the host +host_inst_rate 1918134 # Simulator instruction rate (inst/s) +host_op_rate 1942970 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2892641209 # Simulator tick rate (ticks/s) +host_mem_usage 229316 # Number of bytes of host memory used +host_seconds 70.07 # Real time elapsed on the host sim_insts 134398975 # Number of instructions simulated sim_ops 136139203 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 835264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8135040 # Number of bytes read from this memory -system.physmem.bytes_read::total 8970304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 835264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 835264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5584960 # Number of bytes written to this memory -system.physmem.bytes_written::total 5584960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13051 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 127110 # Number of read requests responded to by this memory -system.physmem.num_reads::total 140161 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 87265 # Number of write requests responded to by this memory -system.physmem.num_writes::total 87265 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4115777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 40085543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 44201320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4115777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4115777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27519982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27519982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27519982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4115777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 40085543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 71721303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7906112 # Number of bytes read from this memory +system.physmem.bytes_read::total 8571776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 665664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 665664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5301376 # Number of bytes written to this memory +system.physmem.bytes_written::total 5301376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10401 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123533 # Number of read requests responded to by this memory +system.physmem.num_reads::total 133934 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 3284303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39007767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 42292069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3284303 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3284303 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26156325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26156325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26156325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3284303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39007767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 68448395 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 405883984 # number of cpu cycles simulated +system.cpu.numCycles 405360916 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398975 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 58160249 # nu system.cpu.num_load_insts 37275868 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 405883984 # Number of busy cycles +system.cpu.num_busy_cycles 405360916 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.721102 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2004.741762 # Cycle average of tags in use system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 144544557000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.721102 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978868 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978868 # Average percentage of cache occupancy +system.cpu.icache.warmup_cycle 144318639000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 2004.741762 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.978878 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.978878 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366560 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3166478000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3166478000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3166478000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3166478000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3166478000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3166478000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3055178000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3055178000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3055178000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3055178000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3055178000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3055178000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553584 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553584 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553584 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16930.864488 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16930.864488 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16930.864488 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16335.753700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16335.753700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16335.753700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16335.753700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16335.753700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16335.753700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2605406000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2605406000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2605406000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2605406000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2605406000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2605406000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2494106000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2494106000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2494106000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2494106000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2494106000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2494106000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13930.864488 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13930.864488 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13930.864488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13930.864488 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.753700 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.753700 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.753700 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.753700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.753700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.753700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.606333 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 776708000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.617150 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997953 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997953 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4087.606333 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997951 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997951 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185802 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185802 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1709246000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1709246000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5738404000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5738404000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 462000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 462000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7447650000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7447650000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7447650000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7447650000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1569302000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1569302000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5728156000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5728156000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 420000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 420000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7297458000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7297458000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7297458000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7297458000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37566.671795 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37566.671795 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54566.239398 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54566.239398 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 30800 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 30800 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49432.508313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49432.508313 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34490.911888 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34490.911888 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54468.791602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54468.791602 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 28000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 28000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48435.634496 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48435.634496 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48435.634496 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48435.634496 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 118818 # number of writebacks -system.cpu.dcache.writebacks::total 118818 # number of writebacks +system.cpu.dcache.writebacks::writebacks 122378 # number of writebacks +system.cpu.dcache.writebacks::total 122378 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1572749000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1572749000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5422912000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5422912000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 417000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 417000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6995661000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6995661000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6995661000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6995661000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1432805000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1432805000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6845469000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6845469000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6845469000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6845469000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34566.671795 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34566.671795 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51566.239398 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51566.239398 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 27800 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 27800 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46432.508313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46432.508313 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.911888 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31490.911888 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.634496 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.634496 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.634496 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.634496 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 120138 # number of replacements -system.cpu.l2cache.tagsinuse 19734.031622 # Cycle average of tags in use -system.cpu.l2cache.total_refs 212003 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 139002 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.525179 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 101560 # number of replacements +system.cpu.l2cache.tagsinuse 29288.840921 # Cycle average of tags in use +system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15768.107062 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2612.732810 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1353.191750 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.481204 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.079734 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.041296 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.602235 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 173973 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 19969 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 193942 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 118818 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 118818 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3599 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3599 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 173973 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 23568 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 197541 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 173973 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 23568 # number of overall hits -system.cpu.l2cache.overall_hits::total 197541 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1249.791870 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.756015 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.099669 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.038141 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.893824 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 176623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 23301 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 199924 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 122378 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 122378 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3844 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3844 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 176623 # 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