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authorAndreas Hansson <andreas.hansson@arm.com>2015-03-02 05:04:20 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-03-02 05:04:20 -0500
commit8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch)
tree446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/50.vortex
parentfc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff)
downloadgem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/50.vortex')
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt991
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt1573
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt462
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt976
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt1668
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt22
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt346
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt492
8 files changed, 3259 insertions, 3271 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 47efecce5..acacb719c 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,105 +1,105 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.058585 # Number of seconds simulated
-sim_ticks 58584661500 # Number of ticks simulated
-final_tick 58584661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.059745 # Number of seconds simulated
+sim_ticks 59744560000 # Number of ticks simulated
+final_tick 59744560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 201524 # Simulator instruction rate (inst/s)
-host_op_rate 201524 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 133496887 # Simulator tick rate (ticks/s)
-host_mem_usage 290684 # Number of bytes of host memory used
-host_seconds 438.85 # Real time elapsed on the host
+host_inst_rate 336953 # Simulator instruction rate (inst/s)
+host_op_rate 336953 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 227629544 # Simulator tick rate (ticks/s)
+host_mem_usage 304552 # Number of bytes of host memory used
+host_seconds 262.46 # Real time elapsed on the host
sim_insts 88438073 # Number of instructions simulated
sim_ops 88438073 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 516608 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 517248 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10147776 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10664384 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 516608 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 516608 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 8072 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 10665024 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 517248 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 517248 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7299008 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7299008 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 8082 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158559 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 166631 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 8818144 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 173215578 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 182033722 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8818144 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8818144 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 124590154 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 124590154 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 124590154 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 8818144 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 173215578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 306623876 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 166631 # Number of read requests accepted
-system.physmem.writeReqs 114048 # Number of write requests accepted
-system.physmem.readBursts 166631 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10663872 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10664384 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total 166641 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 114047 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 114047 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 8657659 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 169852720 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 178510378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 8657659 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 8657659 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 122170253 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 122170253 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 122170253 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 8657659 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 169852720 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 300680631 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 166641 # Number of read requests accepted
+system.physmem.writeReqs 114047 # Number of write requests accepted
+system.physmem.readBursts 166641 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 114047 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10664448 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7297216 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10665024 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7299008 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10466 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10512 # Per bank write bursts
+system.physmem.perBankRdBursts::0 10464 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10514 # Per bank write bursts
system.physmem.perBankRdBursts::2 10315 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10093 # Per bank write bursts
-system.physmem.perBankRdBursts::4 10429 # Per bank write bursts
+system.physmem.perBankRdBursts::3 10095 # Per bank write bursts
+system.physmem.perBankRdBursts::4 10432 # Per bank write bursts
system.physmem.perBankRdBursts::5 10431 # Per bank write bursts
-system.physmem.perBankRdBursts::6 9849 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10302 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10595 # Per bank write bursts
+system.physmem.perBankRdBursts::6 9850 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10303 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10594 # Per bank write bursts
system.physmem.perBankRdBursts::9 10644 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10598 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10258 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10302 # Per bank write bursts
-system.physmem.perBankRdBursts::13 10653 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10596 # Per bank write bursts
+system.physmem.perBankRdBursts::11 10260 # Per bank write bursts
+system.physmem.perBankRdBursts::12 10303 # Per bank write bursts
+system.physmem.perBankRdBursts::13 10654 # Per bank write bursts
system.physmem.perBankRdBursts::14 10528 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10648 # Per bank write bursts
+system.physmem.perBankRdBursts::15 10649 # Per bank write bursts
system.physmem.perBankWrBursts::0 7087 # Per bank write bursts
system.physmem.perBankWrBursts::1 7261 # Per bank write bursts
system.physmem.perBankWrBursts::2 7255 # Per bank write bursts
system.physmem.perBankWrBursts::3 6998 # Per bank write bursts
system.physmem.perBankWrBursts::4 7126 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7176 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7178 # Per bank write bursts
system.physmem.perBankWrBursts::6 6771 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7084 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7223 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6938 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7096 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6991 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6966 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7080 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7224 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6940 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7097 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6990 # Per bank write bursts
+system.physmem.perBankWrBursts::12 6967 # Per bank write bursts
system.physmem.perBankWrBursts::13 7289 # Per bank write bursts
system.physmem.perBankWrBursts::14 7284 # Per bank write bursts
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 58584634500 # Total gap between requests
+system.physmem.totGap 59744533000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 166631 # Read request sizes (log2)
+system.physmem.readPktSize::6 166641 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 114048 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 165000 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1595 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 114047 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 165067 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1538 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 751 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 770 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6975 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 7034 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 7027 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7043 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7044 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 7064 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 7071 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 7065 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7192 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7177 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 7138 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7067 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 7016 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 757 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 6170 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6985 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 7023 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7039 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 7048 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 7057 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 7086 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 7064 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 7260 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 7109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 7129 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 7372 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 7071 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
@@ -193,122 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 54549 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 329.259345 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 194.795576 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 332.998077 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 19535 35.81% 35.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 11763 21.56% 57.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5616 10.30% 67.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3566 6.54% 74.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2684 4.92% 79.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2055 3.77% 82.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1672 3.07% 85.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1540 2.82% 88.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6118 11.22% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 54549 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 7016 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 23.746152 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 348.264922 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 7014 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 54673 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 328.521940 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 195.158907 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 330.861003 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 19447 35.57% 35.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 11824 21.63% 57.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5661 10.35% 67.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3636 6.65% 74.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2772 5.07% 79.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2160 3.95% 83.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1686 3.08% 86.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1520 2.78% 89.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5967 10.91% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 54673 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 23.740134 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 348.174119 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 7016 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 7016 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.250998 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.234711 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.764594 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 6252 89.11% 89.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 8 0.11% 89.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 591 8.42% 97.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 125 1.78% 99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 23 0.33% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 8 0.11% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 5 0.07% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 2 0.03% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 7016 # Writes before turning the bus around for reads
-system.physmem.totQLat 1948128750 # Total ticks spent queuing
-system.physmem.totMemAccLat 5072310000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 833115000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11691.84 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 7018 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.245939 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.230597 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.737975 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 6255 89.13% 89.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 17 0.24% 89.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 574 8.18% 97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 144 2.05% 99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 20 0.28% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 4 0.06% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 7018 # Writes before turning the bus around for reads
+system.physmem.totQLat 1983100250 # Total ticks spent queuing
+system.physmem.totMemAccLat 5107450250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 833160000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11901.08 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30441.84 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 182.02 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 124.56 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 182.03 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 124.59 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30651.08 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 178.50 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 122.14 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 178.51 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 122.17 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.40 # Data bus utilization in percentage
-system.physmem.busUtilRead 1.42 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.97 # Data bus utilization in percentage for writes
+system.physmem.busUtil 2.35 # Data bus utilization in percentage
+system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.07 # Average write queue length when enqueuing
-system.physmem.readRowHits 144841 # Number of row buffer hits during reads
-system.physmem.writeRowHits 81248 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.93 # Row buffer hit rate for reads
+system.physmem.avgWrQLen 24.05 # Average write queue length when enqueuing
+system.physmem.readRowHits 144723 # Number of row buffer hits during reads
+system.physmem.writeRowHits 81251 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.85 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 71.24 # Row buffer hit rate for writes
-system.physmem.avgGap 208724.68 # Average gap between requests
-system.physmem.pageHitRate 80.55 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 199077480 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 108623625 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 642681000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 367791840 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 12184332255 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 24462392250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 41791303890 # Total energy per rank (pJ)
-system.physmem_0.averagePower 713.356895 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 40549753500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1956240000 # Time in different power states
+system.physmem.avgGap 212850.33 # Average gap between requests
+system.physmem.pageHitRate 80.51 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 199115280 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 108644250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 642735600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 367778880 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 12699594585 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 24706498500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 42626547975 # Total energy per rank (pJ)
+system.physmem_0.averagePower 713.484810 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 40950314500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1994980000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 16078529000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 16799112000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 213282720 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 116374500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 656908200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 371038320 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 12703202685 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 24007242750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 41894454615 # Total energy per rank (pJ)
-system.physmem_1.averagePower 715.117627 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 39789307500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1956240000 # Time in different power states
+system.physmem_1.actEnergy 214197480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 116873625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 656962800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 371031840 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 13192492680 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 24274131750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 42727871055 # Total energy per rank (pJ)
+system.physmem_1.averagePower 715.180760 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 40226086750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1994980000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 16838471250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 17523103250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 14678313 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9498021 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 389703 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9975544 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6390264 # Number of BTB hits
+system.cpu.branchPred.lookups 14679718 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9498983 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 392764 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 10434122 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6393495 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 64.059303 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1709596 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 85905 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.274873 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1709689 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 85822 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 20567455 # DTB read hits
-system.cpu.dtb.read_misses 96888 # DTB read misses
+system.cpu.dtb.read_hits 20566953 # DTB read hits
+system.cpu.dtb.read_misses 96874 # DTB read misses
system.cpu.dtb.read_acv 11 # DTB read access violations
-system.cpu.dtb.read_accesses 20664343 # DTB read accesses
-system.cpu.dtb.write_hits 14665775 # DTB write hits
-system.cpu.dtb.write_misses 9411 # DTB write misses
+system.cpu.dtb.read_accesses 20663827 # DTB read accesses
+system.cpu.dtb.write_hits 14666692 # DTB write hits
+system.cpu.dtb.write_misses 9419 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 14675186 # DTB write accesses
-system.cpu.dtb.data_hits 35233230 # DTB hits
-system.cpu.dtb.data_misses 106299 # DTB misses
+system.cpu.dtb.write_accesses 14676111 # DTB write accesses
+system.cpu.dtb.data_hits 35233645 # DTB hits
+system.cpu.dtb.data_misses 106293 # DTB misses
system.cpu.dtb.data_acv 11 # DTB access violations
-system.cpu.dtb.data_accesses 35339529 # DTB accesses
-system.cpu.itb.fetch_hits 25627333 # ITB hits
-system.cpu.itb.fetch_misses 5261 # ITB misses
+system.cpu.dtb.data_accesses 35339938 # DTB accesses
+system.cpu.itb.fetch_hits 25640132 # ITB hits
+system.cpu.itb.fetch_misses 5244 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 25632594 # ITB accesses
+system.cpu.itb.fetch_accesses 25645376 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -322,81 +321,81 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 117169323 # number of cpu cycles simulated
+system.cpu.numCycles 119489120 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88438073 # Number of instructions committed
system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1098705 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 1100288 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.324874 # CPI: cycles per instruction
-system.cpu.ipc 0.754789 # IPC: instructions per cycle
-system.cpu.tickCycles 91571156 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 25598167 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 200776 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4071.523211 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 34616515 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 204872 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 168.966550 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 644809250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4071.523211 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.994024 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.994024 # Average percentage of cache occupancy
+system.cpu.cpi 1.351105 # CPI: cycles per instruction
+system.cpu.ipc 0.740135 # IPC: instructions per cycle
+system.cpu.tickCycles 91601603 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 27887517 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 200784 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4070.582702 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 34615842 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 204880 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 168.956667 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 693853250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4070.582702 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.993795 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.993795 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 745 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3298 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 678 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 3372 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 70176892 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 70176892 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 20283193 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 20283193 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 14333322 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 14333322 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 34616515 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 34616515 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 34616515 # number of overall hits
-system.cpu.dcache.overall_hits::total 34616515 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 89440 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 89440 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 280055 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 280055 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 369495 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 369495 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 369495 # number of overall misses
-system.cpu.dcache.overall_misses::total 369495 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4407640500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4407640500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 19996177500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 19996177500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 24403818000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 24403818000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 24403818000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 24403818000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 20372633 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 20372633 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 70175650 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 70175650 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 20282569 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 20282569 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 14333273 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 14333273 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 34615842 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 34615842 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 34615842 # number of overall hits
+system.cpu.dcache.overall_hits::total 34615842 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 89439 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 89439 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 280104 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 280104 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 369543 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 369543 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 369543 # number of overall misses
+system.cpu.dcache.overall_misses::total 369543 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4793461000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4793461000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 21859170750 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 21859170750 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 26652631750 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 26652631750 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 26652631750 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 26652631750 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 20372008 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 20372008 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 34986010 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 34986010 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 34986010 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 34986010 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 34985385 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 34985385 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 34985385 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 34985385 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019164 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.019164 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.010561 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.010561 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.010561 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.010561 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49280.417039 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49280.417039 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71400.894467 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 71400.894467 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66046.409288 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66046.409288 # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.010563 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.010563 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.010563 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.010563 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53594.751730 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53594.751730 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78039.480871 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 78039.480871 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72123.221790 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72123.221790 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -405,32 +404,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 168546 # number of writebacks
-system.cpu.dcache.writebacks::total 168546 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28125 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 28125 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136498 # number of WriteReq MSHR hits
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-system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311669 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578290 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 889959 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9973376 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23898752 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 33872128 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 217227 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 217226 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 168547 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 143560 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 143560 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311813 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578307 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 890120 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9977984 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 33877312 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 529253 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 529334 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 529253 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 529334 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 529253 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 433172500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 529334 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 433214000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 235311991 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 235419242 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 343212750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 343262500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 35749 # Transaction distribution
-system.membus.trans_dist::ReadResp 35749 # Transaction distribution
-system.membus.trans_dist::Writeback 114048 # Transaction distribution
+system.membus.trans_dist::ReadReq 35759 # Transaction distribution
+system.membus.trans_dist::ReadResp 35759 # Transaction distribution
+system.membus.trans_dist::Writeback 114047 # Transaction distribution
system.membus.trans_dist::ReadExReq 130882 # Transaction distribution
system.membus.trans_dist::ReadExResp 130882 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447310 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 447310 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17963456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 17963456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447329 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 447329 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17964032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17964032 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 280679 # Request fanout histogram
+system.membus.snoop_fanout::samples 280688 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 280679 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 280688 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 280679 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1304618000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1602414250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 2.7 # Layer utilization (%)
+system.membus.snoop_fanout::total 280688 # Request fanout histogram
+system.membus.reqLayer0.occupancy 817068000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 879892750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 6d3efb0ae..c7130e3ac 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,109 +1,109 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.022282 # Number of seconds simulated
-sim_ticks 22281815500 # Number of ticks simulated
-final_tick 22281815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.022578 # Number of seconds simulated
+sim_ticks 22578120000 # Number of ticks simulated
+final_tick 22578120000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 227860 # Simulator instruction rate (inst/s)
-host_op_rate 227860 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 63789654 # Simulator tick rate (ticks/s)
-host_mem_usage 305428 # Number of bytes of host memory used
-host_seconds 349.30 # Real time elapsed on the host
+host_inst_rate 224564 # Simulator instruction rate (inst/s)
+host_op_rate 224564 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 63702871 # Simulator tick rate (ticks/s)
+host_mem_usage 305848 # Number of bytes of host memory used
+host_seconds 354.43 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 487168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10151488 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10638656 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 487168 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 487168 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7296384 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7296384 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 7612 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 158617 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 166229 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 114006 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 114006 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 21863928 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 455595192 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 477459119 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 21863928 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 21863928 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 327459134 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 327459134 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 327459134 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 21863928 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 455595192 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 804918253 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 166229 # Number of read requests accepted
-system.physmem.writeReqs 114006 # Number of write requests accepted
-system.physmem.readBursts 166229 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 114006 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytes_read::cpu.inst 487616 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10151104 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10638720 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 487616 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 487616 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 7619 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 158611 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 166230 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 21596838 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 449599169 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 471196007 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 21596838 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 21596838 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 323181558 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 323181558 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 323181558 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 21596838 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 449599169 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 794377566 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 166230 # Number of read requests accepted
+system.physmem.writeReqs 114013 # Number of write requests accepted
+system.physmem.readBursts 166230 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 114013 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10638144 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7294656 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10638656 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7296384 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10638720 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7296832 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10438 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10454 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10317 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10059 # Per bank write bursts
-system.physmem.perBankRdBursts::4 10417 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10393 # Per bank write bursts
+system.physmem.perBankRdBursts::0 10435 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10460 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10318 # Per bank write bursts
+system.physmem.perBankRdBursts::3 10058 # Per bank write bursts
+system.physmem.perBankRdBursts::4 10413 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10396 # Per bank write bursts
system.physmem.perBankRdBursts::6 9837 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10310 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10606 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10643 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10543 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10224 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10268 # Per bank write bursts
-system.physmem.perBankRdBursts::13 10616 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10478 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10618 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10308 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10587 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10644 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10547 # Per bank write bursts
+system.physmem.perBankRdBursts::11 10228 # Per bank write bursts
+system.physmem.perBankRdBursts::12 10270 # Per bank write bursts
+system.physmem.perBankRdBursts::13 10618 # Per bank write bursts
+system.physmem.perBankRdBursts::14 10481 # Per bank write bursts
+system.physmem.perBankRdBursts::15 10621 # Per bank write bursts
system.physmem.perBankWrBursts::0 7083 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7253 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7259 # Per bank write bursts
system.physmem.perBankWrBursts::2 7255 # Per bank write bursts
system.physmem.perBankWrBursts::3 6997 # Per bank write bursts
system.physmem.perBankWrBursts::4 7126 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7169 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6770 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7085 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7220 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6943 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7084 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7171 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6772 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7083 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7219 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6939 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7083 # Per bank write bursts
system.physmem.perBankWrBursts::11 6988 # Per bank write bursts
system.physmem.perBankWrBursts::12 6964 # Per bank write bursts
-system.physmem.perBankWrBursts::13 7287 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7283 # Per bank write bursts
+system.physmem.perBankWrBursts::13 7288 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7284 # Per bank write bursts
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 22281781500 # Total gap between requests
+system.physmem.totGap 22578086500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 166229 # Read request sizes (log2)
+system.physmem.readPktSize::6 166230 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 114006 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 51659 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 54099 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 45462 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 14988 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 114013 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 52462 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 43160 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 38431 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 32153 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
@@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 831 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 866 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 1404 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 2462 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4500 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5890 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6743 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7087 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 7519 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 7911 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8284 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8943 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 9706 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 8638 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 8945 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8834 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 8038 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 434 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 169 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 29 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 784 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 809 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2168 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3478 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4829 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 6154 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6617 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6971 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 7123 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 7222 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 7425 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 7835 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 7650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 8007 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 10134 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 8246 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 9963 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 7925 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 349 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 161 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 84 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
@@ -193,124 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 52189 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 343.580755 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 201.430431 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 344.457165 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 18353 35.17% 35.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 10742 20.58% 55.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5641 10.81% 66.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3092 5.92% 72.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2629 5.04% 77.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1694 3.25% 80.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1790 3.43% 84.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1288 2.47% 86.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6960 13.34% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 52189 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6966 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 23.861757 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 342.246517 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 6964 99.97% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 52260 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 343.127440 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 201.641716 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 343.309325 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 18423 35.25% 35.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 10477 20.05% 55.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5934 11.35% 66.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2978 5.70% 72.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2855 5.46% 77.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1509 2.89% 80.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2072 3.96% 84.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 924 1.77% 86.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7088 13.56% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 52260 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6982 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 23.804927 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 342.249057 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 6981 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6966 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6965 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.363676 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.332802 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.079402 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 6068 87.12% 87.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 30 0.43% 87.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 495 7.11% 94.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 185 2.66% 97.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 91 1.31% 98.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 46 0.66% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 21 0.30% 99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 10 0.14% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 10 0.14% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 5 0.07% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 3 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6965 # Writes before turning the bus around for reads
-system.physmem.totQLat 5436579750 # Total ticks spent queuing
-system.physmem.totMemAccLat 8553223500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.rdPerTurnAround::total 6982 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6982 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.325265 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.299310 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.979398 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 6150 88.08% 88.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 25 0.36% 88.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 468 6.70% 95.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 181 2.59% 97.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 78 1.12% 98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 46 0.66% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 19 0.27% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 10 0.14% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 4 0.06% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6982 # Writes before turning the bus around for reads
+system.physmem.totQLat 5742111500 # Total ticks spent queuing
+system.physmem.totMemAccLat 8858755250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 831105000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 32706.94 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 34545.04 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 51456.94 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 477.44 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 327.38 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 477.46 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 327.46 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 53295.04 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 471.17 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 323.10 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 471.20 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 323.18 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 6.29 # Data bus utilization in percentage
-system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing
-system.physmem.readRowHits 146012 # Number of row buffer hits during reads
-system.physmem.writeRowHits 81986 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 87.84 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes
-system.physmem.avgGap 79511.06 # Average gap between requests
-system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 190496880 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 103941750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 641043000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 367539120 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 6553751985 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 7617131250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 16928894145 # Total energy per rank (pJ)
-system.physmem_0.averagePower 759.936312 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 12590169250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 743860000 # Time in different power states
+system.physmem.busUtil 6.21 # Data bus utilization in percentage
+system.physmem.busUtilRead 3.68 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing
+system.physmem.readRowHits 146222 # Number of row buffer hits during reads
+system.physmem.writeRowHits 81709 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 87.97 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 71.67 # Row buffer hit rate for writes
+system.physmem.avgGap 80566.10 # Average gap between requests
+system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 190685880 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 104044875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 641035200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 367584480 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 6555814245 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 7792863750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 17126343870 # Total energy per rank (pJ)
+system.physmem_0.averagePower 758.721685 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 12883309000 # Time in different power states
+system.physmem_0.memoryStateTime::REF 753740000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 8942711000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 8935594000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 203779800 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 111189375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy 204104880 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 111366750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 654919200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 370694880 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 6762785805 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 7433764500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 16992123720 # Total energy per rank (pJ)
-system.physmem_1.averagePower 762.774895 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 12284853000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 743860000 # Time in different power states
+system.physmem_1.writeEnergy 370701360 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 6889050495 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 7500532500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 17204990625 # Total energy per rank (pJ)
+system.physmem_1.averagePower 762.206905 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 12395641000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 753740000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 9248437000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 9423231500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 16624924 # Number of BP lookups
-system.cpu.branchPred.condPredicted 10755300 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 362268 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 10924107 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7374828 # Number of BTB hits
+system.cpu.branchPred.lookups 16619938 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10751763 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 361573 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 10694449 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7373128 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 67.509665 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1991560 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2903 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 68.943505 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1990233 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3119 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 22639897 # DTB read hits
-system.cpu.dtb.read_misses 226363 # DTB read misses
-system.cpu.dtb.read_acv 23 # DTB read access violations
-system.cpu.dtb.read_accesses 22866260 # DTB read accesses
-system.cpu.dtb.write_hits 15870343 # DTB write hits
-system.cpu.dtb.write_misses 44837 # DTB write misses
+system.cpu.dtb.read_hits 22587975 # DTB read hits
+system.cpu.dtb.read_misses 226213 # DTB read misses
+system.cpu.dtb.read_acv 17 # DTB read access violations
+system.cpu.dtb.read_accesses 22814188 # DTB read accesses
+system.cpu.dtb.write_hits 15866557 # DTB write hits
+system.cpu.dtb.write_misses 44947 # DTB write misses
system.cpu.dtb.write_acv 1 # DTB write access violations
-system.cpu.dtb.write_accesses 15915180 # DTB write accesses
-system.cpu.dtb.data_hits 38510240 # DTB hits
-system.cpu.dtb.data_misses 271200 # DTB misses
-system.cpu.dtb.data_acv 24 # DTB access violations
-system.cpu.dtb.data_accesses 38781440 # DTB accesses
-system.cpu.itb.fetch_hits 13919462 # ITB hits
-system.cpu.itb.fetch_misses 31654 # ITB misses
+system.cpu.dtb.write_accesses 15911504 # DTB write accesses
+system.cpu.dtb.data_hits 38454532 # DTB hits
+system.cpu.dtb.data_misses 271160 # DTB misses
+system.cpu.dtb.data_acv 18 # DTB access violations
+system.cpu.dtb.data_accesses 38725692 # DTB accesses
+system.cpu.itb.fetch_hits 13913083 # ITB hits
+system.cpu.itb.fetch_misses 32600 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 13951116 # ITB accesses
+system.cpu.itb.fetch_accesses 13945683 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -324,240 +321,240 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 44563634 # number of cpu cycles simulated
+system.cpu.numCycles 45156244 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 15791560 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 106158478 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16624924 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9366388 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 27217966 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 963396 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 137 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 4946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 337279 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13919462 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 206375 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 43833697 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.421846 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.133787 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 15767330 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 106100961 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16619938 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9363361 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 27775290 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 962592 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 208 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 5030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 339291 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13913083 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 207051 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 44368516 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.391357 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.125574 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24095007 54.97% 54.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1538131 3.51% 58.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1406372 3.21% 61.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1524721 3.48% 65.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4235690 9.66% 74.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1846144 4.21% 79.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 685371 1.56% 80.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1070354 2.44% 83.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 7431907 16.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24640012 55.53% 55.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1537852 3.47% 59.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1401576 3.16% 62.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1522530 3.43% 65.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4244947 9.57% 75.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1845094 4.16% 79.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 677475 1.53% 80.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1069981 2.41% 83.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 7429049 16.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 43833697 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.373060 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.382177 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 15105656 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9282610 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18470395 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 592044 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 382992 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3741910 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 100605 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 104048931 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 315835 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 382992 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 15490766 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 6387964 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 95966 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18655378 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2820631 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102900646 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 4493 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 152365 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 320462 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 2296242 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 61929819 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 124171537 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 123841536 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 330000 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 44368516 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.368054 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.349641 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 15099347 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9823247 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18465046 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 597969 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 382907 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3741515 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 100209 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 104016227 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 314595 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 382907 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 15487504 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 6707215 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 96849 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18654699 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 3039342 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102867556 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4643 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 101006 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 348263 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 2491758 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 61906530 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 124122948 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 123794647 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 328300 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 9382938 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 5791 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 5849 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2464589 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 23265416 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16459353 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1262626 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 544604 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 91320451 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 5681 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 89124415 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 80151 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11242959 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 4725710 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1098 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 43833697 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.033240 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.247678 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 9359649 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 5745 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 5793 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 2522683 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 23265731 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16453437 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1244012 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 539260 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 91299347 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 5639 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 89055311 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 77552 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 11218941 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 4714239 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1056 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 44368516 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.007174 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.246117 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 17209661 39.26% 39.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 5800175 13.23% 52.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5098270 11.63% 64.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 4410681 10.06% 74.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4347575 9.92% 84.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2649961 6.05% 90.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1950790 4.45% 94.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1381860 3.15% 97.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 984724 2.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 17795444 40.11% 40.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 5774110 13.01% 53.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5077311 11.44% 64.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 4396727 9.91% 74.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4357066 9.82% 84.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2650893 5.97% 90.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1948119 4.39% 94.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1385813 3.12% 97.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 983033 2.22% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::total 44368516 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 244354 9.65% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1175209 46.41% 56.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1112799 43.94% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 243204 9.64% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 1 0.00% 9.64% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1172094 46.45% 56.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 1108166 43.91% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49663354 55.72% 55.72% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 44187 0.05% 55.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.77% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 122171 0.14% 55.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 55.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 121874 0.14% 56.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 39065 0.04% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 23057459 25.87% 81.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 16076160 18.04% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49651741 55.75% 55.75% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 44157 0.05% 55.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 121956 0.14% 55.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 121436 0.14% 56.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 39055 0.04% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.12% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 23004684 25.83% 81.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 16072139 18.05% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 89124415 # Type of FU issued
-system.cpu.iq.rate 1.999936 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2532362 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.028414 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 224079080 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 102152200 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87178162 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 615960 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 437940 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 301333 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 91348643 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 308134 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1658507 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 89055311 # Type of FU issued
+system.cpu.iq.rate 1.972159 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2523465 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.028336 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 224465346 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 102111433 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87163804 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 614809 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 433572 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 300747 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 91271228 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 307548 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2988778 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6943 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 21591 # Number of memory ordering violations
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3051 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 325532 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 382992 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1216204 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 4841557 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100851766 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 147146 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 23265416 # Number of dispatched load instructions
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-system.cpu.iew.iewLSQFullEvents 4819285 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 21591 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 151679 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 156559 # Number of branches that were predicted not taken incorrectly
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-system.cpu.iew.iewExecutedInsts 88344034 # Number of executed instructions
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+system.cpu.iew.iewUnblockCycles 4974138 # Number of cycles IEW is unblocking
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9525634 # number of nop insts executed
-system.cpu.iew.exec_refs 38782381 # number of memory reference insts executed
-system.cpu.iew.exec_branches 15172546 # Number of branches executed
-system.cpu.iew.exec_stores 15915482 # Number of stores executed
-system.cpu.iew.exec_rate 1.982424 # Inst execution rate
-system.cpu.iew.wb_sent 87895909 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 87479495 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 33899568 # num instructions producing a value
-system.cpu.iew.wb_consumers 44349597 # num instructions consuming a value
+system.cpu.iew.exec_nop 9524485 # number of nop insts executed
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+system.cpu.iew.wb_sent 87882002 # cumulative count of insts sent to commit
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.963024 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.764372 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.936931 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.764520 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 9308985 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9282281 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 263562 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 42463328 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.080399 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.884681 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::mean 2.054408 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.876009 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 20917493 49.26% 49.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 6333939 14.92% 64.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 2944595 6.93% 71.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 1757333 4.14% 75.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1653620 3.89% 79.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1138333 2.68% 81.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1205391 2.84% 84.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 793939 1.87% 86.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5718685 13.47% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 21467431 49.92% 49.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 6329802 14.72% 64.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 2918642 6.79% 71.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 1760390 4.09% 75.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1670777 3.89% 79.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1138707 2.65% 82.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1203989 2.80% 84.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 794665 1.85% 86.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5716148 13.29% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 42463328 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 43000551 # Number of insts commited each cycle
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -603,344 +600,344 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5718685 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5716148 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 133076958 # The number of ROB reads
-system.cpu.rob.rob_writes 196673244 # The number of ROB writes
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-system.cpu.idleCycles 729937 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 133590014 # The number of ROB reads
+system.cpu.rob.rob_writes 196617452 # The number of ROB writes
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+system.cpu.idleCycles 787728 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.559903 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.559903 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.786025 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.786025 # IPC: Total IPC of All Threads
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-system.cpu.int_regfile_writes 57936362 # number of integer regfile writes
-system.cpu.fp_regfile_reads 255891 # number of floating regfile reads
-system.cpu.fp_regfile_writes 241873 # number of floating regfile writes
-system.cpu.misc_regfile_reads 38152 # number of misc regfile reads
+system.cpu.cpi 0.567348 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.567348 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.762586 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.762586 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_writes 1 # number of misc regfile writes
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-system.cpu.dcache.tags.avg_refs 165.907907 # Average number of references to valid blocks.
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system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
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-system.cpu.dcache.blocked_cycles::no_mshrs 6293239 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 146230 # number of cycles access was blocked
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-system.cpu.dcache.writebacks::total 168920 # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_misses::total 62068 # number of ReadReq MSHR misses
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-system.cpu.dcache.WriteReq_mshr_misses::total 143408 # number of WriteReq MSHR misses
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 13368781676 # number of WriteReq MSHR miss cycles
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system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2266008500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2738617750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11494650500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11494650500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472609250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13760659000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 14233268250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472609250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13760659000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 14233268250 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448386 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.224621 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911980 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911980 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.551892 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.551892 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62079.239459 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81423.230327 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77268.226448 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87888.326057 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87888.326057 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::total 35450 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130781 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 130781 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 7620 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 158611 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 166231 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 7620 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 158611 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 166231 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 527900750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2422370000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2950270750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12290499750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12290499750 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 527900750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14712869750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 15240770500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 527900750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14712869750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 15240770500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448415 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.225710 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912033 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912033 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771987 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.553264 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771987 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.553264 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69278.313648 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87041.681639 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 83223.434415 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93977.716564 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93977.716564 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69278.313648 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92760.714894 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91684.285723 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69278.313648 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92760.714894 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91684.285723 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 157790 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 157789 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 168920 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191445 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579874 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 771319 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6126208 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23961408 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 30087616 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq 157060 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 157059 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 168921 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189993 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579837 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 769830 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6079744 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23960256 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 30040000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 470120 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 469376 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 470120 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 469376 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 470120 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 403980000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 469376 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 403609000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 144944965 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 321950247 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 143899236 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 325469999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 35442 # Transaction distribution
-system.membus.trans_dist::ReadResp 35442 # Transaction distribution
-system.membus.trans_dist::Writeback 114006 # Transaction distribution
-system.membus.trans_dist::ReadExReq 130787 # Transaction distribution
-system.membus.trans_dist::ReadExResp 130787 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446464 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 446464 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 17935040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 35449 # Transaction distribution
+system.membus.trans_dist::ReadResp 35449 # Transaction distribution
+system.membus.trans_dist::Writeback 114013 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130781 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130781 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446473 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 446473 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935552 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17935552 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 280235 # Request fanout histogram
+system.membus.snoop_fanout::samples 280243 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 280235 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 280243 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 280235 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1235714000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 5.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1525262750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 6.8 # Layer utilization (%)
+system.membus.snoop_fanout::total 280243 # Request fanout histogram
+system.membus.reqLayer0.occupancy 786749500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 3.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 865056500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 3.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 06edb9753..987ba828d 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.133635 # Number of seconds simulated
-sim_ticks 133634727000 # Number of ticks simulated
-final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.133634 # Number of seconds simulated
+sim_ticks 133634149500 # Number of ticks simulated
+final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1471745 # Simulator instruction rate (inst/s)
-host_op_rate 1471745 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2226337698 # Simulator tick rate (ticks/s)
-host_mem_usage 297712 # Number of bytes of host memory used
-host_seconds 60.02 # Real time elapsed on the host
+host_inst_rate 1329181 # Simulator instruction rate (inst/s)
+host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2010669405 # Simulator tick rate (ticks/s)
+host_mem_usage 301232 # Number of bytes of host memory used
+host_seconds 66.46 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -25,41 +25,17 @@ system.physmem.num_reads::cpu.data 158389 # Nu
system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory
system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 3239397 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 75855253 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 79094650 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 3239397 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 3239397 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 54587966 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 54587966 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 54587966 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 34272 # Transaction distribution
-system.membus.trans_dist::ReadResp 34272 # Transaction distribution
-system.membus.trans_dist::Writeback 113982 # Transaction distribution
-system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
-system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 279135 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 279135 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
+system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 267269454 # number of cpu cycles simulated
+system.cpu.numCycles 267268299 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 88340673 # Number of instructions committed
@@ -113,7 +89,7 @@ system.cpu.num_mem_refs 34987415 # nu
system.cpu.num_load_insts 20366786 # Number of load instructions
system.cpu.num_store_insts 14620629 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 267269454 # Number of busy cycles
+system.cpu.num_busy_cycles 267268299 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 13754477 # Number of branches fetched
@@ -152,13 +128,120 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 88438073 # Class of executed instruction
+system.cpu.dcache.tags.replacements 200248 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
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@@ -181,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n
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@@ -199,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864
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@@ -219,43 +302,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436
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@@ -284,17 +367,17 @@ system.cpu.l2cache.demand_misses::total 165153 # nu
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@@ -319,17 +402,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.588194 #
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52005.164908 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52005.164908 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.084046 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.084046 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52501.668150 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52501.668150 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -351,17 +434,17 @@ system.cpu.l2cache.demand_mshr_misses::total 165153
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 270916000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1100778000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1371694000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235279000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235279000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 270916000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6336057000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 6606973000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 270916000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6336057000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 6606973000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 274073000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1114207000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1388280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5300691500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5300691500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 274073000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6414898500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6688971500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 274073000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6414898500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6688971500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses
@@ -373,125 +456,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40052.631579 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40016.649702 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40023.751167 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.297981 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.297981 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 200248 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
-system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
-system.cpu.dcache.overall_misses::total 204344 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks
-system.cpu.dcache.writebacks::total 168375 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
@@ -521,5 +497,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 114654000 # La
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 34272 # Transaction distribution
+system.membus.trans_dist::ReadResp 34272 # Transaction distribution
+system.membus.trans_dist::Writeback 113982 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 279135 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 279135 # Request fanout histogram
+system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
+system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index b9814d1e2..20f3ef2c3 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -1,95 +1,95 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.057816 # Number of seconds simulated
-sim_ticks 57815555000 # Number of ticks simulated
-final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.058730 # Number of seconds simulated
+sim_ticks 58730125500 # Number of ticks simulated
+final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 131971 # Simulator instruction rate (inst/s)
-host_op_rate 168772 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 107593052 # Simulator tick rate (ticks/s)
-host_mem_usage 309228 # Number of bytes of host memory used
-host_seconds 537.35 # Real time elapsed on the host
+host_inst_rate 197162 # Simulator instruction rate (inst/s)
+host_op_rate 252141 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 163284235 # Simulator tick rate (ticks/s)
+host_mem_usage 321164 # Number of bytes of host memory used
+host_seconds 359.68 # Real time elapsed on the host
sim_insts 70915127 # Number of instructions simulated
sim_ops 90690083 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 324480 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7923328 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory
+system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory
system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 5070 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 123802 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory
system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 5612330 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 137044918 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 5612330 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 137044918 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128872 # Number of read requests accepted
+system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 128871 # Number of read requests accepted
system.physmem.writeReqs 83951 # Number of write requests accepted
-system.physmem.readBursts 128872 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 8247424 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5370880 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 8247808 # Total read bytes from the system interface side
+system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 8159 # Per bank write bursts
-system.physmem.perBankRdBursts::1 8375 # Per bank write bursts
-system.physmem.perBankRdBursts::2 8229 # Per bank write bursts
+system.physmem.perBankRdBursts::1 8376 # Per bank write bursts
+system.physmem.perBankRdBursts::2 8228 # Per bank write bursts
system.physmem.perBankRdBursts::3 8171 # Per bank write bursts
-system.physmem.perBankRdBursts::4 8320 # Per bank write bursts
+system.physmem.perBankRdBursts::4 8319 # Per bank write bursts
system.physmem.perBankRdBursts::5 8450 # Per bank write bursts
system.physmem.perBankRdBursts::6 8088 # Per bank write bursts
-system.physmem.perBankRdBursts::7 7970 # Per bank write bursts
+system.physmem.perBankRdBursts::7 7969 # Per bank write bursts
system.physmem.perBankRdBursts::8 8071 # Per bank write bursts
system.physmem.perBankRdBursts::9 7640 # Per bank write bursts
-system.physmem.perBankRdBursts::10 7820 # Per bank write bursts
-system.physmem.perBankRdBursts::11 7830 # Per bank write bursts
+system.physmem.perBankRdBursts::10 7818 # Per bank write bursts
+system.physmem.perBankRdBursts::11 7832 # Per bank write bursts
system.physmem.perBankRdBursts::12 7881 # Per bank write bursts
system.physmem.perBankRdBursts::13 7879 # Per bank write bursts
system.physmem.perBankRdBursts::14 7977 # Per bank write bursts
-system.physmem.perBankRdBursts::15 8006 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5183 # Per bank write bursts
+system.physmem.perBankRdBursts::15 8007 # Per bank write bursts
+system.physmem.perBankWrBursts::0 5180 # Per bank write bursts
system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
-system.physmem.perBankWrBursts::6 5194 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5048 # Per bank write bursts
+system.physmem.perBankWrBursts::6 5197 # Per bank write bursts
+system.physmem.perBankWrBursts::7 5050 # Per bank write bursts
system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5086 # Per bank write bursts
-system.physmem.perBankWrBursts::10 5252 # Per bank write bursts
+system.physmem.perBankWrBursts::9 5087 # Per bank write bursts
+system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
system.physmem.perBankWrBursts::11 5143 # Per bank write bursts
system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
-system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
+system.physmem.perBankWrBursts::15 5227 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 57815523000 # Total gap between requests
+system.physmem.totGap 58730091000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 128872 # Read request sizes (log2)
+system.physmem.readPktSize::6 128871 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -98,8 +98,8 @@ system.physmem.writePktSize::4 0 # Wr
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 83951 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4315 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5151 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5168 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5177 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5178 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5292 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 5260 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5248 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5669 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5229 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5157 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
@@ -193,100 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 38442 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 354.194267 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 215.182491 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 335.610229 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 12218 31.78% 31.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 8019 20.86% 52.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4166 10.84% 63.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2872 7.47% 70.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2487 6.47% 77.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1677 4.36% 81.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1283 3.34% 85.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1207 3.14% 88.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4513 11.74% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 38442 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 24.976343 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 360.782218 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.273027 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.256397 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.767804 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 4530 87.84% 87.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 6 0.12% 87.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 497 9.64% 97.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 105 2.04% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 11 0.21% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 3 0.06% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 2 0.04% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads
-system.physmem.totQLat 1505377000 # Total ticks spent queuing
-system.physmem.totMemAccLat 3921614500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 644330000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11681.72 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads
+system.physmem.totQLat 1533027250 # Total ticks spent queuing
+system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30431.72 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 142.65 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 92.90 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 142.66 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 92.93 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 1.84 # Data bus utilization in percentage
-system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes
+system.physmem.busUtil 1.81 # Data bus utilization in percentage
+system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing
-system.physmem.readRowHits 112203 # Number of row buffer hits during reads
-system.physmem.writeRowHits 62134 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes
-system.physmem.avgGap 271660.13 # Average gap between requests
-system.physmem.pageHitRate 81.92 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 150995880 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 82388625 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 512779800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 11724732990 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 24403046250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 40922317065 # Total energy per rank (pJ)
-system.physmem_0.averagePower 707.837327 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 40469303500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1930500000 # Time in different power states
+system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing
+system.physmem.readRowHits 112070 # Number of row buffer hits during reads
+system.physmem.writeRowHits 62147 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes
+system.physmem.avgGap 275958.74 # Average gap between requests
+system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ)
+system.physmem_0.averagePower 708.329716 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 15413376500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 139625640 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 76184625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 492086400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 271486080 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 11316053250 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 24761537250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 40833031245 # Total energy per rank (pJ)
-system.physmem_1.averagePower 706.292941 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 41066657000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1930500000 # Time in different power states
+system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ)
+system.physmem_1.averagePower 706.358131 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 14816189000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 14822198 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9914609 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 394622 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9489453 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6747157 # Number of BTB hits
+system.cpu.branchPred.lookups 14827059 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 71.101643 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1719210 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@@ -406,89 +404,89 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 115631110 # number of cpu cycles simulated
+system.cpu.numCycles 117460251 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70915127 # Number of instructions committed
system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1144126 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.630556 # CPI: cycles per instruction
-system.cpu.ipc 0.613288 # IPC: instructions per cycle
-system.cpu.tickCycles 96933125 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 18697985 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 156428 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4068.581764 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42664902 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4068.581764 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy
+system.cpu.cpi 1.656350 # CPI: cycles per instruction
+system.cpu.ipc 0.603737 # IPC: instructions per cycle
+system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 156434 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 749 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 22989229 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 19643835 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 42633064 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 42633064 # number of overall hits
-system.cpu.dcache.overall_hits::total 42633064 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 56065 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 206066 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 262131 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 262131 # number of overall misses
-system.cpu.dcache.overall_misses::total 262131 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2147242437 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 15196521000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 17343763437 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 17343763437 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23045294 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits
+system.cpu.dcache.overall_hits::total 42634623 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses
+system.cpu.dcache.overall_misses::total 262226 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 42895195 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 42895195 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010381 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.006111 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.006111 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38299.160564 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73745.892093 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -497,32 +495,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks
-system.cpu.dcache.writebacks::total 128441 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2577 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99030 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 99030 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 101607 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 101607 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 101607 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 101607 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53488 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 53488 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107036 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107036 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 160524 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 160524 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 160524 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1987609313 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1987609313 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7609976000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7609976000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9597585313 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9597585313 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks
+system.cpu.dcache.writebacks::total 128445 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
@@ -531,68 +529,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742
system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37159.910877 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71097.350424 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40441.693080 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40441.693080 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78502.165200 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78502.165200 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 42682 # number of replacements
-system.cpu.icache.tags.tagsinuse 1858.929385 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 25083355 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 44724 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 560.847755 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 42774 # number of replacements
+system.cpu.icache.tags.tagsinuse 1856.910000 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 25093452 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 44816 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 559.921724 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1858.929385 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.907680 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.907680 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 1856.910000 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.906694 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.906694 # Average percentage of cache occupancy
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@@ -737,107 +735,105 @@ system.cpu.l2cache.demand_mshr_hits::total 73 #
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-system.membus.reqLayer0.occupancy 929408000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1213401000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 2.1 # Layer utilization (%)
+system.membus.snoop_fanout::total 212822 # Request fanout histogram
+system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 6394c9beb..c55c80533 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,118 +1,118 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.033020 # Number of seconds simulated
-sim_ticks 33019504000 # Number of ticks simulated
-final_tick 33019504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.033359 # Number of seconds simulated
+sim_ticks 33359312000 # Number of ticks simulated
+final_tick 33359312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 123822 # Simulator instruction rate (inst/s)
-host_op_rate 158353 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 57659893 # Simulator tick rate (ticks/s)
-host_mem_usage 322352 # Number of bytes of host memory used
-host_seconds 572.66 # Real time elapsed on the host
+host_inst_rate 125450 # Simulator instruction rate (inst/s)
+host_op_rate 160435 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59019201 # Simulator tick rate (ticks/s)
+host_mem_usage 322444 # Number of bytes of host memory used
+host_seconds 565.23 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 90682584 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 588736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 2517376 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 6201600 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9307712 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 588736 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 588736 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6262016 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6262016 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 9199 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 39334 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 96900 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 145433 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 97844 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 97844 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 17829947 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 76239062 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 187816268 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 281885276 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 17829947 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 17829947 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 189645974 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 189645974 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 189645974 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 17829947 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 76239062 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 187816268 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 471531250 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 145433 # Number of read requests accepted
-system.physmem.writeReqs 97844 # Number of write requests accepted
-system.physmem.readBursts 145433 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 97844 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 9300480 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6260352 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 9307712 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6262016 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 593600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 2515776 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 6204544 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9313920 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 593600 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 593600 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6264768 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6264768 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 9275 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 39309 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 96946 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 145530 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 97887 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 97887 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 17794132 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 75414505 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 185991366 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 279200003 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 17794132 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 17794132 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 187796679 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 187796679 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 187796679 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 17794132 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 75414505 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 185991366 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 466996681 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 145530 # Number of read requests accepted
+system.physmem.writeReqs 97887 # Number of write requests accepted
+system.physmem.readBursts 145530 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 97887 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 9306560 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6263296 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 9313920 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6264768 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 9146 # Per bank write bursts
-system.physmem.perBankRdBursts::1 9381 # Per bank write bursts
-system.physmem.perBankRdBursts::2 9349 # Per bank write bursts
-system.physmem.perBankRdBursts::3 9489 # Per bank write bursts
-system.physmem.perBankRdBursts::4 9691 # Per bank write bursts
-system.physmem.perBankRdBursts::5 9742 # Per bank write bursts
-system.physmem.perBankRdBursts::6 9065 # Per bank write bursts
-system.physmem.perBankRdBursts::7 9033 # Per bank write bursts
-system.physmem.perBankRdBursts::8 9160 # Per bank write bursts
-system.physmem.perBankRdBursts::9 8585 # Per bank write bursts
-system.physmem.perBankRdBursts::10 8818 # Per bank write bursts
-system.physmem.perBankRdBursts::11 8754 # Per bank write bursts
-system.physmem.perBankRdBursts::12 8666 # Per bank write bursts
-system.physmem.perBankRdBursts::13 8713 # Per bank write bursts
-system.physmem.perBankRdBursts::14 8726 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9002 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5993 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6194 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6159 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6198 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6133 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6325 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6074 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6046 # Per bank write bursts
-system.physmem.perBankWrBursts::8 6012 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6139 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6243 # Per bank write bursts
-system.physmem.perBankWrBursts::11 5934 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6049 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6103 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6164 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6052 # Per bank write bursts
+system.physmem.perBankRdBursts::0 9160 # Per bank write bursts
+system.physmem.perBankRdBursts::1 9419 # Per bank write bursts
+system.physmem.perBankRdBursts::2 9305 # Per bank write bursts
+system.physmem.perBankRdBursts::3 9483 # Per bank write bursts
+system.physmem.perBankRdBursts::4 9789 # Per bank write bursts
+system.physmem.perBankRdBursts::5 9711 # Per bank write bursts
+system.physmem.perBankRdBursts::6 9074 # Per bank write bursts
+system.physmem.perBankRdBursts::7 9074 # Per bank write bursts
+system.physmem.perBankRdBursts::8 9205 # Per bank write bursts
+system.physmem.perBankRdBursts::9 8628 # Per bank write bursts
+system.physmem.perBankRdBursts::10 8849 # Per bank write bursts
+system.physmem.perBankRdBursts::11 8741 # Per bank write bursts
+system.physmem.perBankRdBursts::12 8642 # Per bank write bursts
+system.physmem.perBankRdBursts::13 8695 # Per bank write bursts
+system.physmem.perBankRdBursts::14 8691 # Per bank write bursts
+system.physmem.perBankRdBursts::15 8949 # Per bank write bursts
+system.physmem.perBankWrBursts::0 5976 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6255 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6149 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6169 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6151 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6334 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6086 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6007 # Per bank write bursts
+system.physmem.perBankWrBursts::8 5979 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6153 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6241 # Per bank write bursts
+system.physmem.perBankWrBursts::11 5938 # Per bank write bursts
+system.physmem.perBankWrBursts::12 6061 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6105 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6219 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6041 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 33019298500 # Total gap between requests
+system.physmem.totGap 33359040500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 145433 # Read request sizes (log2)
+system.physmem.readPktSize::6 145530 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 97844 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 47136 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 46826 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 17078 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 9801 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 6398 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 5373 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 4750 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 4278 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3551 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 97887 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 42093 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 51689 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 18360 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 9225 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 6081 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 5319 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 4669 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 4300 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3562 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
@@ -148,33 +148,33 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1117 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1152 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 1935 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 2597 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3403 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4356 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5168 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5608 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5930 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6190 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 6581 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 7181 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7838 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 8277 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 7722 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6437 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 72 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1144 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 1920 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 2607 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 3444 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4432 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5283 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5659 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5932 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 6165 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6447 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 6873 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 7427 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 8222 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 9030 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 8085 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 6411 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 253 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 112 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
@@ -197,102 +197,104 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 88783 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 175.237151 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 110.501041 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 239.251674 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 52191 58.78% 58.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 22671 25.54% 84.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4463 5.03% 89.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 1678 1.89% 91.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 979 1.10% 92.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 876 0.99% 93.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 737 0.83% 94.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 796 0.90% 95.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4392 4.95% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 88783 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5909 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 24.589101 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 21.077809 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 187.247746 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511 5908 99.98% 99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 88927 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 175.072858 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 110.491943 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 238.713124 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 52339 58.86% 58.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 22656 25.48% 84.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4441 4.99% 89.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1741 1.96% 91.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1037 1.17% 92.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 849 0.95% 93.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 689 0.77% 94.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 765 0.86% 95.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4410 4.96% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 88927 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 24.598207 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 21.088924 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 187.219466 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5909 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5909 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.554070 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.510446 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.278697 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 4738 80.18% 80.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 25 0.42% 80.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 725 12.27% 92.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 165 2.79% 95.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 107 1.81% 97.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 76 1.29% 98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 36 0.61% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 24 0.41% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 8 0.14% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5909 # Writes before turning the bus around for reads
-system.physmem.totQLat 7598607995 # Total ticks spent queuing
-system.physmem.totMemAccLat 10323357995 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 726600000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 52288.80 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.556251 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.512708 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.281856 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 4715 79.77% 79.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 33 0.56% 80.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 741 12.54% 92.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 193 3.27% 96.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 104 1.76% 97.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 53 0.90% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 34 0.58% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 17 0.29% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 11 0.19% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 4 0.07% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 2 0.03% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 3 0.05% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads
+system.physmem.totQLat 7478329771 # Total ticks spent queuing
+system.physmem.totMemAccLat 10204861021 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 727075000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 51427.50 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 71038.80 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 281.67 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 189.60 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 281.89 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 189.65 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 70177.50 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 278.98 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 187.75 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 279.20 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 187.80 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.68 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.20 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 1.48 # Data bus utilization in percentage for writes
+system.physmem.busUtil 3.65 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing
-system.physmem.readRowHits 118226 # Number of row buffer hits during reads
-system.physmem.writeRowHits 36119 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 36.91 # Row buffer hit rate for writes
-system.physmem.avgGap 135727.17 # Average gap between requests
-system.physmem.pageHitRate 63.47 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 342362160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 186804750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 583720800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 318193920 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 11787255720 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 9468687000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 24843318750 # Total energy per rank (pJ)
-system.physmem_0.averagePower 752.509165 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 15653624306 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1102400000 # Time in different power states
+system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing
+system.physmem.readRowHits 118188 # Number of row buffer hits during reads
+system.physmem.writeRowHits 36158 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.28 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 36.94 # Row buffer hit rate for writes
+system.physmem.avgGap 137044.83 # Average gap between requests
+system.physmem.pageHitRate 63.44 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 343556640 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 187456500 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 584859600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 318226320 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 2178671040 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 11869125390 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 9602419500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 25084314990 # Total energy per rank (pJ)
+system.physmem_0.averagePower 752.005565 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 15876395968 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1113840000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 16257963444 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 16366332782 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 328376160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 179173500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 549010800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 315414000 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 11313288180 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 9884473500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 24726030540 # Total energy per rank (pJ)
-system.physmem_1.averagePower 748.955517 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 16351310453 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1102400000 # Time in different power states
+system.physmem_1.actEnergy 328413960 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 179194125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 548948400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 315725040 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 2178671040 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 11416289175 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 9999644250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 24966885990 # Total energy per rank (pJ)
+system.physmem_1.averagePower 748.485148 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 16542747198 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1113840000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 15560341797 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 15699981552 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 17204705 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11516912 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 648025 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9345879 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7673903 # Number of BTB hits
+system.cpu.branchPred.lookups 17207670 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11518844 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 648137 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9345275 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7675164 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 82.110019 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1872530 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 101564 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 82.128819 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1873048 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 101561 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -411,234 +413,234 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 66039009 # number of cpu cycles simulated
+system.cpu.numCycles 66718625 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 4981802 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 88178088 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 17204705 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9546433 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 59635234 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1322107 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 4931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 10977 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 22758925 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 68935 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 65294039 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.709071 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.292735 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 4981358 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 88194612 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 17207670 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9548212 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 60206161 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1322349 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 5969 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 13195 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 22764676 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 68972 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 65867882 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.694526 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.296864 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 19515211 29.89% 29.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 8274054 12.67% 42.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 9196195 14.08% 56.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 28308579 43.36% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 20086614 30.50% 30.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 8263984 12.55% 43.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 9201027 13.97% 57.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 28316257 42.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 65294039 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.260523 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.335242 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8590503 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 19016582 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 31530881 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 5663983 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 492090 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3178633 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 170869 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 101389113 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3042046 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 492090 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13367671 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 5222790 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 763292 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 32193949 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 13254247 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 99181436 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 981589 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 3720885 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 53337 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 4029509 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 5185175 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 103906436 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 457606733 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 115387380 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 65867882 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.257914 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.321889 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8560400 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 19609685 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 31575881 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 5629864 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 492052 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3179520 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171002 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 101414286 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3048471 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 492052 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13316863 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 5341740 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 787564 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 32235527 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 13694136 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 99203918 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 983561 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 3871797 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 66642 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 4317748 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 5384160 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 103925780 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 457714134 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 115415425 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 10277210 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 18665 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12765420 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 24319642 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 21987038 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1312197 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2209009 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 98145273 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 34526 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 94858951 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 691771 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 7393055 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 20168064 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 65294039 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.452796 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.148580 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 10296554 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 18650 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12695794 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 24322207 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 21994092 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1403605 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2365005 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 98166864 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 94891849 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 694587 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 7414208 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 20250811 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 65867882 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.440639 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.150059 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 17159256 26.28% 26.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 17193875 26.33% 52.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 17194261 26.33% 78.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 11711028 17.94% 96.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 2034625 3.12% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 994 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 17597825 26.72% 26.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 17436284 26.47% 53.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 17101122 25.96% 79.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 11678255 17.73% 96.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2053424 3.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 972 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 65294039 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 65867882 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 6670808 22.11% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 41 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 11293243 37.42% 59.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 12213472 40.47% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6717330 22.42% 22.42% # attempts to use FU when none available
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+system.cpu.iq.fu_full::IntDiv 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 11201861 37.39% 59.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 12041280 40.19% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49494148 52.18% 52.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 89879 0.09% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 24035201 25.34% 77.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21239685 22.39% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49497025 52.16% 52.16% # Type of FU issued
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+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 24063293 25.36% 77.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21241620 22.39% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 94858951 # Type of FU issued
-system.cpu.iq.rate 1.436408 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 30177564 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.318131 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 285881069 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 105584154 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 93463006 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 94891849 # Type of FU issued
+system.cpu.iq.rate 1.422269 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 29960509 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.315733 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 286306469 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 105626883 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 93465742 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 125036397 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 124852240 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1353483 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 1363033 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1453380 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11797 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1431300 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1455945 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 2039 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11790 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1438354 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 120407 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 169543 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 142055 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 176720 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 492090 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 617243 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 370435 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 98189662 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 492052 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 623106 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 467581 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 98211247 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 24319642 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 21987038 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 18606 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1603 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 365951 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11797 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 302833 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 221503 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 524336 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 93942350 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 23727911 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 916601 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 24322207 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 21994092 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1655 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 463043 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11790 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 303168 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 221686 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 524854 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 93974313 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 23756309 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 917536 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9863 # number of nop insts executed
-system.cpu.iew.exec_refs 44710370 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14251746 # Number of branches executed
-system.cpu.iew.exec_stores 20982459 # Number of stores executed
-system.cpu.iew.exec_rate 1.422528 # Inst execution rate
-system.cpu.iew.wb_sent 93584307 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 93463063 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 44927637 # num instructions producing a value
-system.cpu.iew.wb_consumers 76497349 # num instructions consuming a value
+system.cpu.iew.exec_nop 9861 # number of nop insts executed
+system.cpu.iew.exec_refs 44740784 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14252664 # Number of branches executed
+system.cpu.iew.exec_stores 20984475 # Number of stores executed
+system.cpu.iew.exec_rate 1.408517 # Inst execution rate
+system.cpu.iew.wb_sent 93587501 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 93465799 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 44986533 # num instructions producing a value
+system.cpu.iew.wb_consumers 76576760 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.415271 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.587310 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.400895 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.587470 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 6519180 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 6538748 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 479062 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 64238392 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.411744 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.175817 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 479015 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 64808930 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.399315 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.164562 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 30786432 47.93% 47.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 16709618 26.01% 73.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4274980 6.65% 80.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4124415 6.42% 87.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1949899 3.04% 90.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1296449 2.02% 92.07% # Number of insts commited each cycle
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -684,381 +686,381 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
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-system.cpu.l2cache.ReadExReq_mshr_misses::total 8240 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 9199 # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.demand_mshr_misses::total 48521 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 9199 # number of overall MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::total 161120 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 569300762 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2303617903 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872918665 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 11396158527 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39006 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39006 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 539005297 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 539005297 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 569300762 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2842623200 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 3411923962 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 569300762 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2842623200 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 14808082489 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092170 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.060976 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8270 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 8270 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 9275 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 39309 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 48584 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 9275 # number of overall MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112789 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 161373 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 645635507 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2465712994 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3111348501 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10913543372 # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10913543372 # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 83006 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 83006 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 614828776 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 614828776 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 645635507 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3080541770 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 3726177277 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 645635507 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3080541770 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10913543372 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 14639720649 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092096 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.061050 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055463 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055463 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.059964 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055667 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055667 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080951 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.060062 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080951 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.199118 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61887.244483 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74114.210894 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71321.930066 # average ReadReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 101210.121999 # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6501 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6501 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65413.264199 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65413.264199 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70318.500484 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91907.165398 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.199496 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69610.297251 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79439.189214 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77177.866275 # average ReadReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913 # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96760.706913 # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13834.333333 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13834.333333 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74344.471100 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74344.471100 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69610.297251 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78367.340049 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76695.563910 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69610.297251 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78367.340049 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90719.765072 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 660616 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 660616 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 264417 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq 169278 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 660352 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 660352 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 262833 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq 151427 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646767 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1236023 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 1882790 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20696064 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48013376 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 68709440 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 169293 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 1242889 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5.136197 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.342998 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq 148563 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 148563 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646637 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234037 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1880674 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20692032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47899136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 68591168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 151438 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 1223186 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.123797 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.329350 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 1073611 86.38% 86.38% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 169278 13.62% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 1071759 87.62% 87.62% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 151427 12.38% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 1242889 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 801222500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 1223186 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 798712500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 486660171 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 486658187 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 734282302 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 734620345 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 137181 # Transaction distribution
-system.membus.trans_dist::ReadResp 137181 # Transaction distribution
-system.membus.trans_dist::Writeback 97844 # Transaction distribution
+system.membus.trans_dist::ReadReq 137260 # Transaction distribution
+system.membus.trans_dist::ReadResp 137260 # Transaction distribution
+system.membus.trans_dist::Writeback 97887 # Transaction distribution
system.membus.trans_dist::UpgradeReq 6 # Transaction distribution
system.membus.trans_dist::UpgradeResp 6 # Transaction distribution
-system.membus.trans_dist::ReadExReq 8252 # Transaction distribution
-system.membus.trans_dist::ReadExResp 8252 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388722 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 388722 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15569728 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 15569728 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq 8270 # Transaction distribution
+system.membus.trans_dist::ReadExResp 8270 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388959 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 388959 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15578688 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 15578688 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 243283 # Request fanout histogram
+system.membus.snoop_fanout::samples 243423 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 243283 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 243423 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 243283 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1077095188 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 3.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1335208239 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 4.0 # Layer utilization (%)
+system.membus.snoop_fanout::total 243423 # Request fanout histogram
+system.membus.reqLayer0.occupancy 692237323 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 758965490 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 2.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 23c0d1c87..93e5e3e06 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu
sim_ticks 48960011000 # Number of ticks simulated
final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1376675 # Simulator instruction rate (inst/s)
-host_op_rate 1760576 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 950486092 # Simulator tick rate (ticks/s)
-host_mem_usage 308184 # Number of bytes of host memory used
-host_seconds 51.51 # Real time elapsed on the host
+host_inst_rate 1566427 # Simulator instruction rate (inst/s)
+host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1081494789 # Simulator tick rate (ticks/s)
+host_mem_usage 308080 # Number of bytes of host memory used
+host_seconds 45.27 # Real time elapsed on the host
sim_insts 70913181 # Number of instructions simulated
sim_ops 90688136 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556
system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 120930618 # Request fanout histogram
-system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram
+system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram
-system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram
+system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 4 # Request fanout histogram
-system.membus.snoop_fanout::max_value 5 # Request fanout histogram
+system.membus.snoop_fanout::min_value 2 # Request fanout histogram
+system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 120930618 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 938385651..6d597c67f 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.127294 # Number of seconds simulated
-sim_ticks 127293983000 # Number of ticks simulated
-final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.127293 # Number of seconds simulated
+sim_ticks 127293405500 # Number of ticks simulated
+final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 894668 # Simulator instruction rate (inst/s)
-host_op_rate 1142240 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1618302823 # Simulator tick rate (ticks/s)
-host_mem_usage 317432 # Number of bytes of host memory used
-host_seconds 78.66 # Real time elapsed on the host
+host_inst_rate 802256 # Simulator instruction rate (inst/s)
+host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1451138855 # Simulator tick rate (ticks/s)
+host_mem_usage 317568 # Number of bytes of host memory used
+host_seconds 87.72 # Real time elapsed on the host
sim_insts 70373628 # Number of instructions simulated
sim_ops 89847362 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 123820 # Nu
system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory
system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2007071 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 62253375 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 64260445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2007071 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2007071 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 42187194 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 42187194 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 42187194 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 254587966 # number of cpu cycles simulated
+system.cpu.numCycles 254586811 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70373628 # Number of instructions committed
@@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu
system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 254587965.998000 # Number of busy cycles
+system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741485 # Number of branches fetched
@@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690083 # Class of executed instruction
system.cpu.dcache.tags.replacements 155902 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor
+system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@@ -230,8 +230,8 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits
@@ -240,28 +240,28 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits
-system.cpu.dcache.overall_hits::total 42576328 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits
+system.cpu.dcache.overall_hits::total 42576331 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses
-system.cpu.dcache.overall_misses::total 177384 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles
+system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses
+system.cpu.dcache.overall_misses::total 177381 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
@@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003220
system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -304,12 +304,12 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks
system.cpu.dcache.writebacks::total 128239 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
@@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140
system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
@@ -340,26 +340,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194
system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 16890 # number of replacements
-system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 1733.672975 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1733.675052 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.846521 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.846521 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672975 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
@@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n
system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
system.cpu.icache.overall_misses::total 18908 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 414091500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 414091500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 414091500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 414091500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 414091500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 414091500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses
@@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242
system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 21900.333192 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 21900.333192 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21900.333192 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -418,43 +418,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908
system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 94693 # number of replacements
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system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id
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system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses
@@ -483,17 +483,17 @@ system.cpu.l2cache.demand_misses::total 127812 # nu
system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses
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@@ -518,17 +518,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.714409 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -550,17 +550,17 @@ system.cpu.l2cache.demand_mshr_misses::total 127812
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses
@@ -572,17 +572,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
@@ -597,19 +597,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 307145 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
@@ -627,19 +625,19 @@ system.membus.pkt_count::total 339533 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 214631 # Request fanout histogram
+system.membus.snoop_fanout::samples 214640 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 214631 # Request fanout histogram
-system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
+system.membus.snoop_fanout::total 214640 # Request fanout histogram
+system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 3c1945f38..718e317fa 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.202242 # Number of seconds simulated
-sim_ticks 202242260000 # Number of ticks simulated
-final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 202242028500 # Number of ticks simulated
+final_tick 202242028500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1318449 # Simulator instruction rate (inst/s)
-host_op_rate 1335520 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1983988186 # Simulator tick rate (ticks/s)
-host_mem_usage 297988 # Number of bytes of host memory used
-host_seconds 101.94 # Real time elapsed on the host
+host_inst_rate 1201078 # Simulator instruction rate (inst/s)
+host_op_rate 1216630 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1807368744 # Simulator tick rate (ticks/s)
+host_mem_usage 300888 # Number of bytes of host memory used
+host_seconds 111.90 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -25,44 +25,20 @@ system.physmem.num_reads::cpu.data 122291 # Nu
system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory
system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2924651 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 38699251 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 41623902 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2924651 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2924651 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 26223758 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 26223758 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 26223758 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 30277 # Transaction distribution
-system.membus.trans_dist::ReadResp 30277 # Transaction distribution
-system.membus.trans_dist::Writeback 82868 # Transaction distribution
-system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
-system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 214401 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 214401 # Request fanout histogram
-system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
+system.physmem.bw_read::cpu.inst 2924654 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 38699295 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 41623950 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2924654 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2924654 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 26223788 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 26223788 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 26223788 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2924654 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 38699295 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 67847737 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 404484520 # number of cpu cycles simulated
+system.cpu.numCycles 404484057 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 134398962 # Number of instructions committed
@@ -81,7 +57,7 @@ system.cpu.num_mem_refs 58160248 # nu
system.cpu.num_load_insts 37275867 # Number of load instructions
system.cpu.num_store_insts 20884381 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 404484519.998000 # Number of busy cycles
+system.cpu.num_busy_cycles 404484056.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 12719095 # Number of branches fetched
@@ -120,13 +96,140 @@ system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 136293798 # Class of executed instruction
+system.cpu.dcache.tags.replacements 146582 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4087.648320 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 769041000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648320 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits
+system.cpu.dcache.overall_hits::total 57944941 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
+system.cpu.dcache.overall_misses::total 150663 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475000000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 1475000000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619674000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5619674000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7094674000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7094674000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7094674000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7094674000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32418.294908 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32418.294908 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.240881 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.240881 # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 47089.690236 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 47089.690236 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks
+system.cpu.dcache.writebacks::total 123970 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1406751500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1406751500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5461928000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5461928000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 382500 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 382500 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6868679500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6868679500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6868679500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6868679500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30918.294908 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30918.294908 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51937.240881 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51937.240881 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25500 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25500 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 184976 # number of replacements
-system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 2004.815289 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor
+system.cpu.icache.tags.warmup_cycle 143972077000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815289 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
@@ -150,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n
system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses
system.cpu.icache.overall_misses::total 187024 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819681000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 2819681000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 2819681000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 2819681000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 2819681000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 2819681000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819561500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 2819561500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 2819561500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 2819561500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 2819561500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 2819561500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses
@@ -168,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390
system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15076.573060 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15076.573060 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15076.573060 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15076.573060 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15075.934105 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15075.934105 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15075.934105 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency
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@@ -188,34 +291,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024
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-system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks
-system.cpu.dcache.writebacks::total 123970 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
@@ -510,5 +486,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 280536000 # La
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 30277 # Transaction distribution
+system.membus.trans_dist::ReadResp 30277 # Transaction distribution
+system.membus.trans_dist::Writeback 82868 # Transaction distribution
+system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
+system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 214401 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 214401 # Request fanout histogram
+system.membus.reqLayer0.occupancy 558284500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.membus.respLayer1.occupancy 657665500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------