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authorNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
commit9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch)
tree64b85031cb791a21af6059778384d358d992b817 /tests/long/se/50.vortex
parentdbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff)
downloadgem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/50.vortex')
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini57
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout8
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt27
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini57
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt27
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini21
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini68
-rwxr-xr-xtests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout12
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt210
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini37
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/o3-timing/simout10
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt27
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini34
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini87
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/simple-timing/simout10
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt226
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini17
-rwxr-xr-xtests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini64
-rwxr-xr-xtests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout10
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt250
27 files changed, 682 insertions, 639 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index 00b189ec1..81c2390c7 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
@@ -57,17 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -76,11 +64,11 @@ memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
@@ -88,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -95,21 +101,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -126,21 +127,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -163,21 +159,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -204,7 +195,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 2318eb90a..41b47fff5 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 12:19:26
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:34:49
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index 130fea357..8052f41c2 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.043266 # Nu
sim_ticks 43266024500 # Number of ticks simulated
final_tick 43266024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 113775 # Simulator instruction rate (inst/s)
-host_op_rate 113775 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 55722813 # Simulator tick rate (ticks/s)
-host_mem_usage 252752 # Number of bytes of host memory used
-host_seconds 776.45 # Real time elapsed on the host
+host_inst_rate 92573 # Simulator instruction rate (inst/s)
+host_op_rate 92573 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 45339086 # Simulator tick rate (ticks/s)
+host_mem_usage 308556 # Number of bytes of host memory used
+host_seconds 954.28 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 454720 # Number of bytes read from this memory
@@ -192,6 +192,15 @@ system.physmem.writeRowHits 41713 # Nu
system.physmem.readRowHitRate 91.81 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 36.59 # Row buffer hit rate for writes
system.physmem.avgGap 154790.12 # Average gap between requests
+system.cpu.branchPred.lookups 18742312 # Number of BP lookups
+system.cpu.branchPred.condPredicted 12317439 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 4774431 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 15498318 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 4661486 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 30.077367 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1660962 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 4583 # Nu
system.cpu.numCycles 86532050 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 18742312 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 12317439 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 4774431 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 15498318 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 4661486 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 1660962 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 30.077367 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 8071751 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10670561 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74169472 # Number of Reads from Int. Register File
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 06d858804..9f30fe52b 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -56,7 +53,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -116,6 +103,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -125,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -132,21 +138,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -426,21 +427,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -463,21 +459,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -504,7 +495,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
index 8fd1a4d9e..86a8209ba 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 12:32:34
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:35:07
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index c5e407e29..ee0778484 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.024415 # Nu
sim_ticks 24414646000 # Number of ticks simulated
final_tick 24414646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 171645 # Simulator instruction rate (inst/s)
-host_op_rate 171645 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52651835 # Simulator tick rate (ticks/s)
-host_mem_usage 254848 # Number of bytes of host memory used
-host_seconds 463.70 # Real time elapsed on the host
+host_inst_rate 131517 # Simulator instruction rate (inst/s)
+host_op_rate 131517 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 40342582 # Simulator tick rate (ticks/s)
+host_mem_usage 309584 # Number of bytes of host memory used
+host_seconds 605.18 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 490368 # Number of bytes read from this memory
@@ -192,6 +192,15 @@ system.physmem.writeRowHits 40821 # Nu
system.physmem.readRowHitRate 91.56 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 35.80 # Row buffer hit rate for writes
system.physmem.avgGap 87091.78 # Average gap between requests
+system.cpu.branchPred.lookups 16536427 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10675204 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 418905 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11705282 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7341882 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 62.722812 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1987114 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 42052 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 4583 # Nu
system.cpu.numCycles 48829295 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 16536427 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 10675204 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 418905 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11705282 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7341882 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1987114 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 42052 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 15791672 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 105370615 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16536427 # Number of branches that fetch encountered
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 06c6ef199..565b787c0 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,17 +44,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -99,14 +105,15 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
index dd92eb188..dcabfa4e7 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:30:37
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:34:02
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 4ae9b05ab..e11282e38 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu
sim_ticks 44221003000 # Number of ticks simulated
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3187268 # Simulator instruction rate (inst/s)
-host_op_rate 3187266 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1595460185 # Simulator tick rate (ticks/s)
-host_mem_usage 214012 # Number of bytes of host memory used
-host_seconds 27.72 # Real time elapsed on the host
+host_inst_rate 2426632 # Simulator instruction rate (inst/s)
+host_op_rate 2426631 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1214706702 # Simulator tick rate (ticks/s)
+host_mem_usage 272072 # Number of bytes of host memory used
+host_seconds 36.40 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index e15c6aa9f..3b759a9fa 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -120,23 +120,20 @@ size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -158,12 +155,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -181,13 +178,14 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
index d2ae983de..e6bb386fa 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 10:09:02
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:15:43
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 134581343000 because target called exit()
+Exiting @ tick 133634727000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 43727f4ad..a53da63fa 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu
sim_ticks 133634727000 # Number of ticks simulated
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 783809 # Simulator instruction rate (inst/s)
-host_op_rate 783809 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1185683886 # Simulator tick rate (ticks/s)
-host_mem_usage 225136 # Number of bytes of host memory used
-host_seconds 112.71 # Real time elapsed on the host
+host_inst_rate 996502 # Simulator instruction rate (inst/s)
+host_op_rate 996501 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1507427540 # Simulator tick rate (ticks/s)
+host_mem_usage 280652 # Number of bytes of host memory used
+host_seconds 88.65 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
@@ -167,106 +167,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 200248 # number of replacements
-system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use
-system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
-system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
-system.cpu.dcache.overall_misses::total 204344 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks
-system.cpu.dcache.writebacks::total 168375 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 131235 # number of replacements
system.cpu.l2cache.tagsinuse 30728.810101 # Cycle average of tags in use
system.cpu.l2cache.total_refs 142024 # Total number of references to valid blocks.
@@ -405,5 +305,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 200248 # number of replacements
+system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use
+system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
+system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
+system.cpu.dcache.overall_misses::total 204344 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks
+system.cpu.dcache.writebacks::total 168375 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index be7e2dd7e..0d9336fbc 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -522,7 +527,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index ef0c59dbf..b7ae68a85 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 00:36:17
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:59:12
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 26292466000 because target called exit()
+Exiting @ tick 26275145500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 145d86740..57be29288 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.026275 # Nu
sim_ticks 26275145500 # Number of ticks simulated
final_tick 26275145500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 119366 # Simulator instruction rate (inst/s)
-host_op_rate 169395 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44231565 # Simulator tick rate (ticks/s)
-host_mem_usage 271872 # Number of bytes of host memory used
-host_seconds 594.04 # Real time elapsed on the host
+host_inst_rate 87619 # Simulator instruction rate (inst/s)
+host_op_rate 124343 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32467681 # Simulator tick rate (ticks/s)
+host_mem_usage 316828 # Number of bytes of host memory used
+host_seconds 809.27 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 100626876 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory
@@ -192,6 +192,15 @@ system.physmem.writeRowHits 27176 # Nu
system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 32.37 # Row buffer hit rate for writes
system.physmem.avgGap 123527.37 # Average gap between requests
+system.cpu.branchPred.lookups 16626972 # Number of BP lookups
+system.cpu.branchPred.condPredicted 12763144 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 604576 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 10780847 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7773827 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 72.107757 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1825491 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 113784 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -238,14 +247,6 @@ system.cpu.workload.num_syscalls 1946 # Nu
system.cpu.numCycles 52550292 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 16626972 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12763144 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 604576 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10780847 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7773827 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1825491 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 113784 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12554350 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 85230964 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16626972 # Number of branches that fetch encountered
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 04247a7b5..d64046cb9 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -68,7 +71,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@@ -76,6 +79,23 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -84,7 +104,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@@ -100,7 +120,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -124,7 +144,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
index 4a0327c7e..c3ccf1541 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 14:04:14
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:10:40
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 420bb3f6b..0248ad642 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu
sim_ticks 53932157000 # Number of ticks simulated
final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1829500 # Simulator instruction rate (inst/s)
-host_op_rate 2596230 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1391402909 # Simulator tick rate (ticks/s)
-host_mem_usage 226332 # Number of bytes of host memory used
-host_seconds 38.76 # Real time elapsed on the host
+host_inst_rate 1242714 # Simulator instruction rate (inst/s)
+host_op_rate 1763527 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 945130731 # Simulator tick rate (ticks/s)
+host_mem_usage 286616 # Number of bytes of host memory used
+host_seconds 57.06 # Real time elapsed on the host
sim_insts 70913181 # Number of instructions simulated
sim_ops 100632428 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index 4b2d5473a..358ede026 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -91,7 +89,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -101,23 +99,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -126,6 +119,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -134,7 +144,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -142,25 +152,20 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -169,10 +174,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -187,7 +192,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -211,7 +216,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
index b57985d9c..b9e94a32f 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:06:20
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:11:48
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 133513136000 because target called exit()
+Exiting @ tick 132689045000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 9156fbcd7..ddc9fbf9d 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu
sim_ticks 132689045000 # Number of ticks simulated
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 796611 # Simulator instruction rate (inst/s)
-host_op_rate 1129615 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1502004709 # Simulator tick rate (ticks/s)
-host_mem_usage 239164 # Number of bytes of host memory used
-host_seconds 88.34 # Real time elapsed on the host
+host_inst_rate 652363 # Simulator instruction rate (inst/s)
+host_op_rate 925068 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1230026759 # Simulator tick rate (ticks/s)
+host_mem_usage 295072 # Number of bytes of host memory used
+host_seconds 107.88 # Real time elapsed on the host
sim_insts 70373628 # Number of instructions simulated
sim_ops 99791654 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
@@ -177,114 +177,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 155902 # number of replacements
-system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use
-system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits
-system.cpu.dcache.overall_hits::total 46830236 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses
-system.cpu.dcache.overall_misses::total 159998 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks
-system.cpu.dcache.writebacks::total 128239 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 94693 # number of replacements
system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use
system.cpu.l2cache.total_refs 74295 # Total number of references to valid blocks.
@@ -423,5 +315,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 155902 # number of replacements
+system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use
+system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits
+system.cpu.dcache.overall_hits::total 46830236 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses
+system.cpu.dcache.overall_misses::total 159998 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks
+system.cpu.dcache.writebacks::total 128239 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index dd4ef298a..1bc84354f 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,17 +44,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -105,8 +111,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
index 0a5ffdd78..806d3e418 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:18:28
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:08:27
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 932598cf9..4cce8cf2a 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu
sim_ticks 68148672000 # Number of ticks simulated
final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2819750 # Simulator instruction rate (inst/s)
-host_op_rate 2856259 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1429788311 # Simulator tick rate (ticks/s)
-host_mem_usage 230172 # Number of bytes of host memory used
-host_seconds 47.66 # Real time elapsed on the host
+host_inst_rate 2091817 # Simulator instruction rate (inst/s)
+host_op_rate 2118902 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1060681468 # Simulator tick rate (ticks/s)
+host_mem_usage 281256 # Number of bytes of host memory used
+host_seconds 64.25 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index a3a928813..6398f17b7 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -120,23 +120,20 @@ size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -163,7 +160,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -186,8 +183,9 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
index 3a91ca093..1ed94a2b4 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:19:26
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:01:47
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 204097178000 because target called exit()
+Exiting @ tick 202242260000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index ea44c1e9f..97e5107ce 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.202242 # Nu
sim_ticks 202242260000 # Number of ticks simulated
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1258181 # Simulator instruction rate (inst/s)
-host_op_rate 1274472 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1893298806 # Simulator tick rate (ticks/s)
-host_mem_usage 233128 # Number of bytes of host memory used
-host_seconds 106.82 # Real time elapsed on the host
+host_inst_rate 1033030 # Simulator instruction rate (inst/s)
+host_op_rate 1046406 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1554493166 # Simulator tick rate (ticks/s)
+host_mem_usage 289840 # Number of bytes of host memory used
+host_seconds 130.10 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory
@@ -135,126 +135,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 146582 # number of replacements
-system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use
-system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits
-system.cpu.dcache.overall_hits::total 57944941 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
-system.cpu.dcache.overall_misses::total 150663 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475111000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619675000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7094786000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7094786000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32420.734522 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.250390 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks
-system.cpu.dcache.writebacks::total 123970 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 98540 # number of replacements
system.cpu.l2cache.tagsinuse 30850.759699 # Cycle average of tags in use
system.cpu.l2cache.total_refs 226933 # Total number of references to valid blocks.
@@ -393,5 +273,125 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 146582 # number of replacements
+system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use
+system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits
+system.cpu.dcache.overall_hits::total 57944941 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
+system.cpu.dcache.overall_misses::total 150663 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475111000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619675000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7094786000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7094786000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32420.734522 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.250390 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks
+system.cpu.dcache.writebacks::total 123970 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------