diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
| commit | d2b57a7473768e8aff3707916b40b264cab6821c (patch) | |
| tree | f4e64db0a8bb23dd26a1c8f1ec5b887be346f625 /tests/long/se/50.vortex | |
| parent | 7c55464aac2bcab15699e563f18a7d3d565d949a (diff) | |
| download | gem5-d2b57a7473768e8aff3707916b40b264cab6821c.tar.xz | |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
Diffstat (limited to 'tests/long/se/50.vortex')
3 files changed, 1251 insertions, 1251 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 52b1e9eb7..361b9fcbc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.047910 # Number of seconds simulated -sim_ticks 47910283500 # Number of ticks simulated -final_tick 47910283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.047911 # Number of seconds simulated +sim_ticks 47910588500 # Number of ticks simulated +final_tick 47910588500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137428 # Simulator instruction rate (inst/s) -host_op_rate 137428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74532010 # Simulator tick rate (ticks/s) -host_mem_usage 227148 # Number of bytes of host memory used -host_seconds 642.82 # Real time elapsed on the host +host_inst_rate 102205 # Simulator instruction rate (inst/s) +host_op_rate 102205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55429613 # Simulator tick rate (ticks/s) +host_mem_usage 227308 # Number of bytes of host memory used +host_seconds 864.35 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 515328 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 160515 # Nu system.physmem.num_reads::total 168567 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10756104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 214420773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 225176877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10756104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10756104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 154922899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 154922899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 154922899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10756104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 214420773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380099775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10756036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 214419408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 225175443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10756036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10756036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 154921913 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 154921913 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 154921913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10756036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 214419408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380097356 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 95820568 # number of cpu cycles simulated +system.cpu.numCycles 95821178 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 18829757 # Number of BP lookups @@ -97,12 +97,12 @@ system.cpu.execution_unit.executions 44775821 # Nu system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78582823 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78582835 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 467369 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25529650 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70290918 # Number of cycles cpu stages are processed. -system.cpu.activity 73.356816 # Percentage of cycles cpu is active +system.cpu.timesIdled 467389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25530263 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70290915 # Number of cycles cpu stages are processed. +system.cpu.activity 73.356346 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,34 +114,34 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.084671 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.084678 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.084671 # CPI: Total CPI of All Threads -system.cpu.ipc 0.921939 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.084678 # CPI: Total CPI of All Threads +system.cpu.ipc 0.921933 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.921939 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 42393437 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53427131 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 55.757477 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 53162471 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42658097 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 44.518727 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 52693934 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43126634 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.007700 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 73699390 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22121178 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.086043 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 49718373 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46102195 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 48.113047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.921933 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 42394050 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53427128 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 55.757119 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 53163082 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42658096 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 44.518442 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 52694545 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43126633 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.007413 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 73699998 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22121180 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.085899 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 49718969 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46102209 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 48.112755 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 85335 # number of replacements -system.cpu.icache.tagsinuse 1885.674809 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1885.674638 # Cycle average of tags in use system.cpu.icache.total_refs 12357256 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 87381 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 141.418111 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1885.674809 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1885.674638 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.920740 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.920740 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 12357256 # number of ReadReq hits @@ -156,12 +156,12 @@ system.cpu.icache.demand_misses::cpu.inst 118639 # n system.cpu.icache.demand_misses::total 118639 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 118639 # number of overall misses system.cpu.icache.overall_misses::total 118639 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081821000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2081821000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2081821000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2081821000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2081821000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2081821000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081863500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2081863500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2081863500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2081863500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2081863500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2081863500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 12475895 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 12475895 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 12475895 # number of demand (read+write) accesses @@ -174,12 +174,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.009509 system.cpu.icache.demand_miss_rate::total 0.009509 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009509 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009509 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.526530 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17547.526530 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17547.526530 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17547.526530 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.884760 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17547.884760 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17547.884760 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17547.884760 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 1176500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,32 +200,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 87381 system.cpu.icache.demand_mshr_misses::total 87381 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 87381 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 87381 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364843500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1364843500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364843500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1364843500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364843500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1364843500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364888000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1364888000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364888000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1364888000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364888000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1364888000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.007004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.007004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.453886 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.453886 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.963150 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.963150 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.238674 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4073.238819 # Cycle average of tags in use system.cpu.dcache.total_refs 34125947 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 166.999990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 499859000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.238674 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4073.238819 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994443 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994443 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20180530 # number of ReadReq hits @@ -244,14 +244,14 @@ system.cpu.dcache.demand_misses::cpu.data 764068 # n system.cpu.dcache.demand_misses::total 764068 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 764068 # number of overall misses system.cpu.dcache.overall_misses::total 764068 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4228645500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 42086848500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 42086848500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46315494000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46315494000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46315494000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46315494000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4228645000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 42089863000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 42089863000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46318508000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46318508000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46318508000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46318508000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -268,20 +268,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.021899 system.cpu.dcache.demand_miss_rate::total 0.021899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.021899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.021899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.891872 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.891872 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63008.037158 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63008.037158 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60616.979117 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60616.979117 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.886669 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.886669 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63012.550153 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63012.550153 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60620.923792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60620.923792 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6945858000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6946123500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 124169 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 55938.744775 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 55940.882990 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 165805 # number of writebacks @@ -304,12 +304,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 204347 system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1936845000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 1936845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7868977000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7868977000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9805822000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9805822000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9805822000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9805822000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7870166500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7870166500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9807011500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9807011500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9807011500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9807011500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -320,24 +320,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31873.302944 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31873.302944 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54805.523053 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54805.523053 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47986.131433 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 47986.131433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47986.131433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 47986.131433 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54813.807633 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54813.807633 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 136141 # number of replacements -system.cpu.l2cache.tagsinuse 28773.047265 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 28773.050902 # Cycle average of tags in use system.cpu.l2cache.total_refs 146499 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 167004 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.877219 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25287.688081 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1723.908362 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1761.450821 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 25287.699561 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1723.905670 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1761.445671 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.771719 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052609 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.053755 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.878084 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 79329 # number of ReadReq hits @@ -367,14 +367,14 @@ system.cpu.l2cache.overall_misses::total 168567 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 427362500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1541002500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1968365000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6838998500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6838998500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6840080000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6840080000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 427362500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8380001000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8807363500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8381082500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8808445000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 427362500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8380001000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8807363500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8381082500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8808445000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 87381 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 147958 # number of ReadReq accesses(hits+misses) @@ -402,14 +402,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.577822 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53075.322901 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52295.873350 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52463.152003 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52186.973475 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52186.973475 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52195.226177 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52195.226177 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52206.965081 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52248.444239 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52213.702769 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52254.860085 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52206.965081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52248.444239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52213.702769 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52254.860085 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,14 +434,14 @@ system.cpu.l2cache.overall_mshr_misses::total 168567 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329154000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1181438500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1510592500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5254733000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5254733000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5255819000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5255819000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329154000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6436171500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6765325500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6437257500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6766411500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329154000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6436171500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6765325500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6437257500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6766411500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486439 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253579 # mshr miss rate for ReadReq accesses @@ -456,14 +456,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.577822 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40878.539493 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40093.613194 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40262.067219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40097.773335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40097.773335 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40106.060375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40106.060375 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 7baadddcc..e1fb122e9 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.021620 # Number of seconds simulated -sim_ticks 21619648000 # Number of ticks simulated -final_tick 21619648000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21619627000 # Number of ticks simulated +final_tick 21619627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236725 # Simulator instruction rate (inst/s) -host_op_rate 236725 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64301983 # Simulator tick rate (ticks/s) -host_mem_usage 228176 # Number of bytes of host memory used -host_seconds 336.22 # Real time elapsed on the host +host_inst_rate 209503 # Simulator instruction rate (inst/s) +host_op_rate 209503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56907639 # Simulator tick rate (ticks/s) +host_mem_usage 228332 # Number of bytes of host memory used +host_seconds 379.91 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 559360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10295744 # Number of bytes read from this memory -system.physmem.bytes_read::total 10855104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 559360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 559360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7426560 # Number of bytes written to this memory -system.physmem.bytes_written::total 7426560 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160871 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169611 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116040 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116040 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25872762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476221630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 502094391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25872762 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25872762 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 343509756 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 343509756 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 343509756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25872762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476221630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845604147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 559680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10295552 # Number of bytes read from this memory +system.physmem.bytes_read::total 10855232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 559680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 559680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7426432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7426432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160868 # Number of read requests responded to by this memory +system.physmem.num_reads::total 169613 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116038 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116038 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25887588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 476213211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 502100799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25887588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25887588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 343504169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 343504169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 343504169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25887588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 476213211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845604968 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22479620 # DTB read hits -system.cpu.dtb.read_misses 218266 # DTB read misses -system.cpu.dtb.read_acv 51 # DTB read access violations -system.cpu.dtb.read_accesses 22697886 # DTB read accesses -system.cpu.dtb.write_hits 15794697 # DTB write hits -system.cpu.dtb.write_misses 42457 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 15837154 # DTB write accesses -system.cpu.dtb.data_hits 38274317 # DTB hits -system.cpu.dtb.data_misses 260723 # DTB misses +system.cpu.dtb.read_hits 22478221 # DTB read hits +system.cpu.dtb.read_misses 218727 # DTB read misses +system.cpu.dtb.read_acv 49 # DTB read access violations +system.cpu.dtb.read_accesses 22696948 # DTB read accesses +system.cpu.dtb.write_hits 15797623 # DTB write hits +system.cpu.dtb.write_misses 42281 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 15839904 # DTB write accesses +system.cpu.dtb.data_hits 38275844 # DTB hits +system.cpu.dtb.data_misses 261008 # DTB misses system.cpu.dtb.data_acv 51 # DTB access violations -system.cpu.dtb.data_accesses 38535040 # DTB accesses -system.cpu.itb.fetch_hits 14126097 # ITB hits -system.cpu.itb.fetch_misses 39352 # ITB misses +system.cpu.dtb.data_accesses 38536852 # DTB accesses +system.cpu.itb.fetch_hits 14126153 # ITB hits +system.cpu.itb.fetch_misses 38209 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14165449 # ITB accesses +system.cpu.itb.fetch_accesses 14164362 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,146 +67,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 43239299 # number of cpu cycles simulated +system.cpu.numCycles 43239256 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16709943 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10781072 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 476192 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12038225 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7471491 # Number of BTB hits +system.cpu.BPredUnit.lookups 16713940 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10785641 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 474517 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12148042 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7471828 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1995310 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44665 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15444845 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106679218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16709943 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9466801 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19799027 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2146422 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5702055 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 320776 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14126097 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 222277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42829816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.490770 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.154588 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1996046 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44341 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15442173 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106653150 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16713940 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9467874 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19795691 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2142333 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5738431 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8227 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 318072 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14126153 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 221095 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 42854841 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.488707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.154001 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23030789 53.77% 53.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1545838 3.61% 57.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1407824 3.29% 60.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1518177 3.54% 64.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4200095 9.81% 74.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1866083 4.36% 78.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 683567 1.60% 79.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1088540 2.54% 82.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7488903 17.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23059150 53.81% 53.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1544639 3.60% 57.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1408806 3.29% 60.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1522467 3.55% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4195710 9.79% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1864977 4.35% 78.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 685640 1.60% 79.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1085683 2.53% 82.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7487769 17.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42829816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.386453 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.467182 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16586159 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5216387 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18831807 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 747368 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1448095 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3802176 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109343 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104798684 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 306113 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1448095 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17060162 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2943499 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 82970 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19071081 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2224009 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103374463 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 294 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 47714 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2072135 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62309566 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124647358 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124190382 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 456976 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 42854841 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.386546 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.466582 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16604436 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5227614 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18845700 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 731163 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1445928 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3801623 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109086 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104782719 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304838 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1445928 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17078558 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2955442 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 82947 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19068517 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2223449 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103359605 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 254 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 47854 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2072460 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62291613 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124619411 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124164571 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 454840 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9762685 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5585 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5583 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4545963 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23367723 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16390642 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1133008 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 393146 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91432081 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5446 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89033358 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 121532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11257440 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4905922 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 863 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42829816 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.078770 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.113525 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9744732 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5573 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5571 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4558890 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23363714 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16388828 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1131841 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 391237 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91420984 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5434 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89018152 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 120887 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11240273 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4901766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 851 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 42854841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.077202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.113927 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 14329925 33.46% 33.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7119620 16.62% 50.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5526453 12.90% 62.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4793299 11.19% 74.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4689695 10.95% 85.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2671983 6.24% 91.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1950910 4.56% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1326668 3.10% 99.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 421263 0.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 14370838 33.53% 33.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7100087 16.57% 50.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5540527 12.93% 63.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4772141 11.14% 74.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4704722 10.98% 85.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2673915 6.24% 91.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1941470 4.53% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1325823 3.09% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 425318 0.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42829816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42854841 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 128939 6.83% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 795203 42.12% 48.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 964007 51.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 128315 6.76% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 799448 42.10% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 971123 51.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49729867 55.86% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43817 0.05% 55.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49717774 55.85% 55.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43792 0.05% 55.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121200 0.14% 56.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 120893 0.14% 56.04% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 122187 0.14% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121944 0.14% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38928 0.04% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.22% # Type of FU issued @@ -228,84 +228,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.22% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22972171 25.80% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16005027 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22969813 25.80% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16004865 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89033358 # Type of FU issued -system.cpu.iq.rate 2.059084 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1888149 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222297193 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102291434 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86992301 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 609020 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 419648 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 296730 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90616918 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 304589 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1450786 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89018152 # Type of FU issued +system.cpu.iq.rate 2.058735 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1898886 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021331 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222303440 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102266391 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86984314 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 607478 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 416601 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 296142 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90613228 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 303810 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1449481 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3091085 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5211 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17173 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1777265 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3087076 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5237 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1775451 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2461 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 40 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2459 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1448095 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1762662 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 92194 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100976081 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 242299 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23367723 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16390642 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 53221 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 430 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17173 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250537 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 173902 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 424439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88065648 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22701440 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 967710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1445928 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1740049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88499 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100965460 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 244137 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23363714 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16388828 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5434 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 53254 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 431 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17226 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 250564 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 172705 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423269 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88055069 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22700407 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 963083 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9538554 # number of nop insts executed -system.cpu.iew.exec_refs 38538948 # number of memory reference insts executed -system.cpu.iew.exec_branches 15139399 # Number of branches executed -system.cpu.iew.exec_stores 15837508 # Number of stores executed -system.cpu.iew.exec_rate 2.036704 # Inst execution rate -system.cpu.iew.wb_sent 87702246 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87289031 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33442850 # num instructions producing a value -system.cpu.iew.wb_consumers 43872911 # num instructions consuming a value +system.cpu.iew.exec_nop 9539042 # number of nop insts executed +system.cpu.iew.exec_refs 38540674 # number of memory reference insts executed +system.cpu.iew.exec_branches 15139519 # Number of branches executed +system.cpu.iew.exec_stores 15840267 # Number of stores executed +system.cpu.iew.exec_rate 2.036461 # Inst execution rate +system.cpu.iew.wb_sent 87694134 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87280456 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33430607 # num instructions producing a value +system.cpu.iew.wb_consumers 43860363 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.018743 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762266 # average fanout of values written-back +system.cpu.iew.wb_rate 2.018547 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762205 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9533571 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9526459 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369490 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 41381721 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.134775 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.804212 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 368198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 41408913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.133373 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.803824 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18296264 44.21% 44.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7146737 17.27% 61.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3523583 8.51% 70.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2099457 5.07% 75.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2039541 4.93% 80.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1177840 2.85% 82.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1135730 2.74% 85.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 713898 1.73% 87.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5248671 12.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18342699 44.30% 44.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7125223 17.21% 61.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3513214 8.48% 69.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2087650 5.04% 75.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2070192 5.00% 80.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1179714 2.85% 82.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1132729 2.74% 85.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 709577 1.71% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5247915 12.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 41381721 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 41408913 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5248671 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5247915 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132689951 # The number of ROB reads -system.cpu.rob.rob_writes 197200056 # The number of ROB writes -system.cpu.timesIdled 24548 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 409483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132710787 # The number of ROB reads +system.cpu.rob.rob_writes 197183581 # The number of ROB writes +system.cpu.timesIdled 23387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 384415 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.543264 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.543264 # CPI: Total CPI of All Threads -system.cpu.ipc 1.840727 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.840727 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116607964 # number of integer regfile reads -system.cpu.int_regfile_writes 57862089 # number of integer regfile writes -system.cpu.fp_regfile_reads 251339 # number of floating regfile reads -system.cpu.fp_regfile_writes 241385 # number of floating regfile writes -system.cpu.misc_regfile_reads 38087 # number of misc regfile reads +system.cpu.cpi 0.543263 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.543263 # CPI: Total CPI of All Threads +system.cpu.ipc 1.840729 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.840729 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116590843 # number of integer regfile reads +system.cpu.int_regfile_writes 57851456 # number of integer regfile writes +system.cpu.fp_regfile_reads 250950 # number of floating regfile reads +system.cpu.fp_regfile_writes 240941 # number of floating regfile writes +system.cpu.misc_regfile_reads 38077 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 92930 # number of replacements -system.cpu.icache.tagsinuse 1930.212243 # Cycle average of tags in use -system.cpu.icache.total_refs 14026666 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 94978 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.683316 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18067713000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1930.212243 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942486 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942486 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14026666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14026666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14026666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14026666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14026666 # number of overall hits -system.cpu.icache.overall_hits::total 14026666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 99431 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 99431 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 99431 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 99431 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 99431 # number of overall misses -system.cpu.icache.overall_misses::total 99431 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1030437000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1030437000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1030437000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1030437000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1030437000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1030437000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14126097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14126097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14126097 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14126097 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14126097 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14126097 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007039 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007039 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007039 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007039 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007039 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10363.337390 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10363.337390 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10363.337390 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10363.337390 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10363.337390 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10363.337390 # average overall miss latency +system.cpu.icache.replacements 92836 # number of replacements +system.cpu.icache.tagsinuse 1929.378925 # Cycle average of tags in use +system.cpu.icache.total_refs 14026889 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 94884 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.831974 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18060721000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1929.378925 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942080 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942080 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14026889 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14026889 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14026889 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14026889 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14026889 # number of overall hits +system.cpu.icache.overall_hits::total 14026889 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 99264 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 99264 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 99264 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 99264 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 99264 # number of overall misses +system.cpu.icache.overall_misses::total 99264 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1029034500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1029034500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1029034500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1029034500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1029034500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1029034500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14126153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14126153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14126153 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14126153 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14126153 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14126153 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007027 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007027 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007027 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007027 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007027 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007027 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10366.643496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10366.643496 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10366.643496 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10366.643496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10366.643496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10366.643496 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,286 +388,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4452 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4452 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4452 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4452 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4452 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4452 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94979 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 94979 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 94979 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 94979 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 94979 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 94979 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 637690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 637690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 637690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 637690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 637690000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 637690000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006724 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006724 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006724 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 637176500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 637176500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 637176500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006717 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006717 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006717 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6715.250040 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6715.250040 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6715.250040 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6715.250040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6715.250040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6715.250040 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201568 # number of replacements -system.cpu.dcache.tagsinuse 4075.950137 # Cycle average of tags in use -system.cpu.dcache.total_refs 34352337 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205664 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.031357 # Average number of references to valid blocks. +system.cpu.dcache.replacements 201660 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54515031500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21026189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21026189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 78 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 78 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35639645 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35639645 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35639645 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35639645 # 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average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44381.773475 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42337.464305 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42337.464305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42337.464305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42337.464305 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 96000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6058.823529 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5647.058824 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 166337 # number of writebacks -system.cpu.dcache.writebacks::total 166337 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 189183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 189183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 892539 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 892539 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1081722 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1081722 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1081722 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 281019000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5571700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5852719500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480451 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 116038 # number of writebacks +system.cpu.l2cache.writebacks::total 116038 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8745 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29899 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 38644 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130969 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130969 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 169613 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8745 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160868 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 169613 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 281196000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 941994500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1223190500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4649150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4649150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 281196000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5591145000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5872341000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 281196000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5591145000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5872341000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.479743 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.245814 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.564161 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782203 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.564161 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32153.203661 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31498.980274 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31646.921087 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35350.722734 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35350.722734 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32153.203661 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34634.586097 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34506.721262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32153.203661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34634.586097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34506.721262 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913102 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913102 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.781839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.564171 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.564171 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32155.060034 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31505.886484 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31652.792154 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35498.098787 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35498.098787 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32155.060034 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34756.104384 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34621.998314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32155.060034 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34756.104384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34621.998314 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6fb730a89..bc1c3c499 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024460 # Number of seconds simulated -sim_ticks 24460150500 # Number of ticks simulated -final_tick 24460150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024450 # Number of seconds simulated +sim_ticks 24450292500 # Number of ticks simulated +final_tick 24450292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167024 # Simulator instruction rate (inst/s) -host_op_rate 237012 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57603012 # Simulator tick rate (ticks/s) -host_mem_usage 242500 # Number of bytes of host memory used -host_seconds 424.63 # Real time elapsed on the host -sim_insts 70923824 # Number of instructions simulated -sim_ops 100643071 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8028736 # Number of bytes read from this memory -system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417152 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125449 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84643 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84643 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13367702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 328237392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 341605094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13367702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13367702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 221468466 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 221468466 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 221468466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13367702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 328237392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 563073559 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 166577 # Simulator instruction rate (inst/s) +host_op_rate 236377 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57425524 # Simulator tick rate (ticks/s) +host_mem_usage 242552 # Number of bytes of host memory used +host_seconds 425.77 # Real time elapsed on the host +sim_insts 70924074 # Number of instructions simulated +sim_ops 100643321 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 328512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8029568 # Number of bytes read from this memory +system.physmem.bytes_read::total 8358080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 328512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 328512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417984 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125462 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130595 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84656 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84656 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13435913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 328403760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 341839673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13435913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13435913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 221591787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 221591787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 221591787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13435913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 328403760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 563431460 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +77,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 48920302 # number of cpu cycles simulated +system.cpu.numCycles 48900586 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16960531 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12985874 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 661473 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11570513 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7976664 # Number of BTB hits +system.cpu.BPredUnit.lookups 16947895 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12979317 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 657239 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11568375 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7965689 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1883015 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 115088 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12843999 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87580035 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16960531 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9859679 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21787094 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2782746 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10982319 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 606 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12079139 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 221673 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47647021 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.336366 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1878366 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114401 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12822432 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87522774 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16947895 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9844055 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21770954 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2772902 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11003856 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 471 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12059223 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 218909 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47624951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336628 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25881368 54.32% 54.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2178299 4.57% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2007274 4.21% 63.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2021463 4.24% 67.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1548956 3.25% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1412983 2.97% 73.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 995678 2.09% 75.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1240946 2.60% 78.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10360054 21.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25875265 54.33% 54.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2171829 4.56% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2001256 4.20% 63.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2024856 4.25% 67.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1547627 3.25% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1411228 2.96% 73.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 995461 2.09% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1239299 2.60% 78.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10358130 21.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47647021 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346697 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.790259 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15031484 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9298191 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19969978 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1421734 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1925634 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3462876 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109476 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120212842 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 378015 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1925634 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16795731 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2963104 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 805180 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19544890 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5612482 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117675747 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 47624951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346579 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.789810 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15015037 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9311189 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19956662 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1421851 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1920212 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3461414 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109087 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 120161085 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 377153 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1920212 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16781785 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2961677 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 806772 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19529075 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5625430 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117632333 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12709 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4780104 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 263 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117787272 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541948309 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 541940540 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99158584 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18628688 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37002 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 36987 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13169886 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30082364 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22781735 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3607820 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4315548 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113341575 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51734 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108469975 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 351751 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12575588 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30093615 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14709 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47647021 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.276532 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995144 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 12238 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4786667 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 232 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117758479 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541753123 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541746251 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6872 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99158984 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18599495 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37350 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37333 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13184553 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30073818 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22775187 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3642294 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4290989 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113312109 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51967 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108452712 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 348423 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12547190 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29979206 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14892 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47624951 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.277225 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.996410 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11903537 24.98% 24.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8354851 17.53% 42.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7454693 15.65% 58.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7158692 15.02% 73.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5519097 11.58% 84.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3907609 8.20% 92.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1895733 3.98% 96.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881641 1.85% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571168 1.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11905380 25.00% 25.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8338489 17.51% 42.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7455711 15.66% 58.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7146400 15.01% 73.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5525482 11.60% 84.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3896676 8.18% 92.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1895621 3.98% 96.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 884969 1.86% 98.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 576223 1.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47647021 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47624951 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112989 4.45% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1419251 55.85% 60.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1008989 39.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113237 4.46% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1413224 55.65% 60.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1012935 39.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57363382 52.88% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91507 0.08% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57358153 52.89% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91504 0.08% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 228 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 207 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued @@ -239,158 +239,158 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29217041 26.94% 79.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21797810 20.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29210718 26.93% 79.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21792123 20.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108469975 # Type of FU issued -system.cpu.iq.rate 2.217279 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2541231 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023428 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 267479180 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125995514 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106424512 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 773 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1272 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 111010818 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 388 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2214998 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108452712 # Type of FU issued +system.cpu.iq.rate 2.217820 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2539396 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023415 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 267417480 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125938241 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106420258 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 714 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1140 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 175 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110991749 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 359 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2211393 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2772017 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7458 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29087 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2222758 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2763421 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7106 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29349 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2216160 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1925634 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 929341 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37355 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113473181 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 343640 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30082364 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22781735 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 35157 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2560 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3541 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29087 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 428613 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 264355 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 692968 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107247329 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28841677 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1222646 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1920212 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 926920 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38130 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113444221 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 341894 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30073818 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22775187 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35362 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2649 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29349 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 424803 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 263892 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 688695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107241565 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28837233 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1211147 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 79872 # number of nop insts executed -system.cpu.iew.exec_refs 50315882 # number of memory reference insts executed -system.cpu.iew.exec_branches 14663606 # Number of branches executed -system.cpu.iew.exec_stores 21474205 # Number of stores executed -system.cpu.iew.exec_rate 2.192287 # Inst execution rate -system.cpu.iew.wb_sent 106761196 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106424699 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53424049 # num instructions producing a value -system.cpu.iew.wb_consumers 103788661 # num instructions consuming a value +system.cpu.iew.exec_nop 80145 # number of nop insts executed +system.cpu.iew.exec_refs 50314250 # number of memory reference insts executed +system.cpu.iew.exec_branches 14661458 # Number of branches executed +system.cpu.iew.exec_stores 21477017 # Number of stores executed +system.cpu.iew.exec_rate 2.193053 # Inst execution rate +system.cpu.iew.wb_sent 106757510 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106420433 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53411369 # num instructions producing a value +system.cpu.iew.wb_consumers 103767535 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.175471 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514739 # average fanout of values written-back +system.cpu.iew.wb_rate 2.176261 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514721 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12825262 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37025 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 616891 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45721388 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.201347 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.733819 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12796121 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37075 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612942 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45704740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.202154 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.735561 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16264410 35.57% 35.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11914734 26.06% 61.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3626051 7.93% 69.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2926022 6.40% 75.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880797 4.11% 80.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1911030 4.18% 84.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 689200 1.51% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 582969 1.28% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5926175 12.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16269057 35.60% 35.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11908776 26.06% 61.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3615674 7.91% 69.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2919531 6.39% 75.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1872792 4.10% 80.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1908851 4.18% 84.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 687748 1.50% 85.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 590243 1.29% 87.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5932068 12.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45721388 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929376 # Number of instructions committed -system.cpu.commit.committedOps 100648623 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45704740 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929626 # Number of instructions committed +system.cpu.commit.committedOps 100648873 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869324 # Number of memory references committed -system.cpu.commit.loads 27310347 # Number of loads committed +system.cpu.commit.refs 47869424 # Number of memory references committed +system.cpu.commit.loads 27310397 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13671866 # Number of branches committed +system.cpu.commit.branches 13671916 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91485735 # Number of committed integer instructions. +system.cpu.commit.int_insts 91485935 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5926175 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5932068 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153243799 # The number of ROB reads -system.cpu.rob.rob_writes 228884039 # The number of ROB writes -system.cpu.timesIdled 52429 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1273281 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70923824 # Number of Instructions Simulated -system.cpu.committedOps 100643071 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70923824 # Number of Instructions Simulated -system.cpu.cpi 0.689758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.689758 # CPI: Total CPI of All Threads -system.cpu.ipc 1.449783 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.449783 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516242048 # number of integer regfile reads -system.cpu.int_regfile_writes 104369908 # number of integer regfile writes -system.cpu.fp_regfile_reads 886 # number of floating regfile reads -system.cpu.fp_regfile_writes 750 # number of floating regfile writes -system.cpu.misc_regfile_reads 146091713 # number of misc regfile reads -system.cpu.misc_regfile_writes 38318 # number of misc regfile writes -system.cpu.icache.replacements 30244 # number of replacements -system.cpu.icache.tagsinuse 1815.033473 # Cycle average of tags in use -system.cpu.icache.total_refs 12045499 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 32282 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 373.133604 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 153192367 # The number of ROB reads +system.cpu.rob.rob_writes 228820850 # The number of ROB writes +system.cpu.timesIdled 52344 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1275635 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924074 # Number of Instructions Simulated +system.cpu.committedOps 100643321 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924074 # Number of Instructions Simulated +system.cpu.cpi 0.689478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.689478 # CPI: Total CPI of All Threads +system.cpu.ipc 1.450373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.450373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516213591 # number of integer regfile reads +system.cpu.int_regfile_writes 104366681 # number of integer regfile writes +system.cpu.fp_regfile_reads 794 # number of floating regfile reads +system.cpu.fp_regfile_writes 662 # number of floating regfile writes +system.cpu.misc_regfile_reads 146023696 # number of misc regfile reads +system.cpu.misc_regfile_writes 38418 # number of misc regfile writes +system.cpu.icache.replacements 30034 # number of replacements +system.cpu.icache.tagsinuse 1814.104659 # Cycle average of tags in use +system.cpu.icache.total_refs 12025772 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32074 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 374.938330 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1815.033473 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.886247 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.886247 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12045501 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12045501 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12045501 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12045501 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12045501 # number of overall hits -system.cpu.icache.overall_hits::total 12045501 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33638 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33638 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33638 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33638 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33638 # number of overall misses -system.cpu.icache.overall_misses::total 33638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 406685000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 406685000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 406685000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 406685000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 406685000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 406685000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12079139 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12079139 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12079139 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12079139 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12079139 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12079139 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002785 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002785 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002785 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002785 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002785 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002785 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12090.046971 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12090.046971 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12090.046971 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12090.046971 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1814.104659 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885793 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885793 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12025773 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12025773 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12025773 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12025773 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12025773 # number of overall hits +system.cpu.icache.overall_hits::total 12025773 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33450 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33450 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33450 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33450 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33450 # number of overall misses +system.cpu.icache.overall_misses::total 33450 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 407167500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 407167500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 407167500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 407167500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 407167500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 407167500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12059223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12059223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12059223 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12059223 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12059223 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12059223 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002774 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002774 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002774 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002774 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002774 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002774 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12172.421525 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12172.421525 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12172.421525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12172.421525 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +399,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1313 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1313 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1313 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1313 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1313 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1313 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32325 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 32325 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 32325 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 32325 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 32325 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 32325 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 274223500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 274223500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 274223500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 274223500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 274223500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 274223500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8483.325599 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8483.325599 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1320 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1320 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1320 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1320 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1320 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1320 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32130 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32130 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32130 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32130 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32130 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32130 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275291000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 275291000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275291000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 275291000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275291000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 275291000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002664 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002664 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002664 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8568.036103 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8568.036103 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158501 # number of replacements -system.cpu.dcache.tagsinuse 4071.855185 # Cycle average of tags in use -system.cpu.dcache.total_refs 44605412 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162597 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.331089 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158627 # number of replacements +system.cpu.dcache.tagsinuse 4071.845451 # Cycle average of tags in use +system.cpu.dcache.total_refs 44602467 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162723 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 274.100570 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 272454000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4071.855185 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26278291 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26278291 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18287500 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18287500 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20317 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20317 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19158 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19158 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44565791 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44565791 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44565791 # number of overall hits -system.cpu.dcache.overall_hits::total 44565791 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 106674 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 106674 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1562401 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1562401 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1669075 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1669075 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1669075 # number of overall misses -system.cpu.dcache.overall_misses::total 1669075 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2574319000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2574319000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 63349260500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 63349260500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 629500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 629500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 65923579500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 65923579500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 65923579500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 65923579500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26384965 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26384965 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4071.845451 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994103 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994103 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26277362 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26277362 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18285328 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18285328 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20388 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20388 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19208 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19208 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44562690 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44562690 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44562690 # number of overall hits +system.cpu.dcache.overall_hits::total 44562690 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 106921 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 106921 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1564573 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1564573 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1671494 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1671494 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1671494 # number of overall misses +system.cpu.dcache.overall_misses::total 1671494 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2586655500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2586655500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63403235500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63403235500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 586000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 586000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 65989891000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 65989891000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 65989891000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 65989891000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26384283 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26384283 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20360 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20360 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19158 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19158 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46234866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46234866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46234866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46234866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004043 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078711 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078711 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002112 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002112 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036100 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036100 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036100 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036100 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24132.581510 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24132.581510 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40546.095721 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40546.095721 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14639.534884 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14639.534884 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39497.074427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39497.074427 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20429 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20429 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19208 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19208 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46234184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46234184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46234184 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46234184 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004052 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004052 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078820 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078820 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002007 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002007 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24192.212007 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24192.212007 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40524.306312 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40524.306312 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14292.682927 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14292.682927 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39479.585927 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39479.585927 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 202500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 210000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19090.909091 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128059 # number of writebacks -system.cpu.dcache.writebacks::total 128059 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51068 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51068 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1455366 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1455366 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1506434 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1506434 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1506434 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1506434 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55606 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55606 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107035 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107035 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162641 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162641 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162641 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162641 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 982100000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 982100000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3836030000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3836030000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4818130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4818130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4818130000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4818130000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17661.763119 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17661.763119 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35839.024618 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35839.024618 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 128131 # number of writebacks +system.cpu.dcache.writebacks::total 128131 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51186 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51186 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457528 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1457528 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1508714 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1508714 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1508714 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1508714 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55735 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55735 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107045 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107045 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162780 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162780 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162780 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162780 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 988383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 988383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3842536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3842536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4830919500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4830919500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4830919500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4830919500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003521 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003521 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17733.623396 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17733.623396 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35896.454762 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35896.454762 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 97988 # number of replacements -system.cpu.l2cache.tagsinuse 28616.670846 # Cycle average of tags in use -system.cpu.l2cache.total_refs 87010 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128775 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.675675 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 98022 # number of replacements +system.cpu.l2cache.tagsinuse 28617.589348 # Cycle average of tags in use +system.cpu.l2cache.total_refs 86966 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 128812 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.675139 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25808.135877 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1157.314936 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1651.220033 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.787602 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035318 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.050391 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.873311 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27137 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32372 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 59509 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128059 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128059 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 7 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits +system.cpu.l2cache.occ_blocks::writebacks 25792.429972 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1163.052716 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1662.106660 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.787122 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.035494 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.050723 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32078.024547 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32769.426807 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32643.950643 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31173.913043 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31173.913043 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31728.020447 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31728.020447 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32078.024547 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31920.186989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31926.390750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32078.024547 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31920.186989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31926.390750 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |