diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se/50.vortex | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se/50.vortex')
4 files changed, 2859 insertions, 2839 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 6234d30e2..58628a22b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060001 # Number of seconds simulated -sim_ticks 60000593000 # Number of ticks simulated -final_tick 60000593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060094 # Number of seconds simulated +sim_ticks 60093931000 # Number of ticks simulated +final_tick 60093931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 262235 # Simulator instruction rate (inst/s) -host_op_rate 262235 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177912819 # Simulator tick rate (ticks/s) -host_mem_usage 257844 # Number of bytes of host memory used -host_seconds 337.25 # Real time elapsed on the host +host_inst_rate 276952 # Simulator instruction rate (inst/s) +host_op_rate 276952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188189933 # Simulator tick rate (ticks/s) +host_mem_usage 264524 # Number of bytes of host memory used +host_seconds 319.33 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 433344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10150272 # Number of bytes read from this memory -system.physmem.bytes_read::total 10583616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 433344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 433344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7325952 # Number of bytes written to this memory -system.physmem.bytes_written::total 7325952 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158598 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165369 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114468 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114468 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7222329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169169528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 176391857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7222329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7222329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122097993 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122097993 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122097993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7222329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169169528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 298489850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165369 # Number of read requests accepted -system.physmem.writeReqs 114468 # Number of write requests accepted -system.physmem.readBursts 165369 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114468 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10583232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7324288 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10583616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7325952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 438272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10168832 # Number of bytes read from this memory +system.physmem.bytes_read::total 10607104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7376000 # Number of bytes written to this memory +system.physmem.bytes_written::total 7376000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158888 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165736 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115250 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115250 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7293116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169215623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 176508739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7293116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7293116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122741180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122741180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122741180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7293116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169215623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 299249919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165736 # Number of read requests accepted +system.physmem.writeReqs 115250 # Number of write requests accepted +system.physmem.readBursts 165736 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115250 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10606464 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue +system.physmem.bytesWritten 7374720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10607104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7376000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10322 # Per bank write bursts -system.physmem.perBankRdBursts::1 10363 # Per bank write bursts -system.physmem.perBankRdBursts::2 10206 # Per bank write bursts -system.physmem.perBankRdBursts::3 10055 # Per bank write bursts -system.physmem.perBankRdBursts::4 10347 # Per bank write bursts -system.physmem.perBankRdBursts::5 10343 # Per bank write bursts -system.physmem.perBankRdBursts::6 9774 # Per bank write bursts -system.physmem.perBankRdBursts::7 10209 # Per bank write bursts -system.physmem.perBankRdBursts::8 10543 # Per bank write bursts -system.physmem.perBankRdBursts::9 10609 # Per bank write bursts -system.physmem.perBankRdBursts::10 10499 # Per bank write bursts -system.physmem.perBankRdBursts::11 10227 # Per bank write bursts -system.physmem.perBankRdBursts::12 10274 # Per bank write bursts -system.physmem.perBankRdBursts::13 10565 # Per bank write bursts -system.physmem.perBankRdBursts::14 10463 # Per bank write bursts -system.physmem.perBankRdBursts::15 10564 # Per bank write bursts -system.physmem.perBankWrBursts::0 7163 # Per bank write bursts -system.physmem.perBankWrBursts::1 7274 # Per bank write bursts -system.physmem.perBankWrBursts::2 7296 # Per bank write bursts -system.physmem.perBankWrBursts::3 7001 # Per bank write bursts -system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7187 # Per bank write bursts -system.physmem.perBankWrBursts::6 6833 # Per bank write bursts -system.physmem.perBankWrBursts::7 7100 # Per bank write bursts -system.physmem.perBankWrBursts::8 7227 # Per bank write bursts -system.physmem.perBankWrBursts::9 7003 # Per bank write bursts -system.physmem.perBankWrBursts::10 7117 # Per bank write bursts -system.physmem.perBankWrBursts::11 7031 # Per bank write bursts -system.physmem.perBankWrBursts::12 6992 # Per bank write bursts -system.physmem.perBankWrBursts::13 7301 # Per bank write bursts -system.physmem.perBankWrBursts::14 7308 # Per bank write bursts -system.physmem.perBankWrBursts::15 7482 # Per bank write bursts +system.physmem.perBankRdBursts::0 10345 # Per bank write bursts +system.physmem.perBankRdBursts::1 10388 # Per bank write bursts +system.physmem.perBankRdBursts::2 10224 # Per bank write bursts +system.physmem.perBankRdBursts::3 10067 # Per bank write bursts +system.physmem.perBankRdBursts::4 10353 # Per bank write bursts +system.physmem.perBankRdBursts::5 10360 # Per bank write bursts +system.physmem.perBankRdBursts::6 9794 # Per bank write bursts +system.physmem.perBankRdBursts::7 10229 # Per bank write bursts +system.physmem.perBankRdBursts::8 10568 # Per bank write bursts +system.physmem.perBankRdBursts::9 10626 # Per bank write bursts +system.physmem.perBankRdBursts::10 10567 # Per bank write bursts +system.physmem.perBankRdBursts::11 10241 # Per bank write bursts +system.physmem.perBankRdBursts::12 10307 # Per bank write bursts +system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::14 10494 # Per bank write bursts +system.physmem.perBankRdBursts::15 10573 # Per bank write bursts +system.physmem.perBankWrBursts::0 7166 # Per bank write bursts +system.physmem.perBankWrBursts::1 7280 # Per bank write bursts +system.physmem.perBankWrBursts::2 7303 # Per bank write bursts +system.physmem.perBankWrBursts::3 7011 # Per bank write bursts +system.physmem.perBankWrBursts::4 7144 # Per bank write bursts +system.physmem.perBankWrBursts::5 7304 # Per bank write bursts +system.physmem.perBankWrBursts::6 6890 # Per bank write bursts +system.physmem.perBankWrBursts::7 7170 # Per bank write bursts +system.physmem.perBankWrBursts::8 7244 # Per bank write bursts +system.physmem.perBankWrBursts::9 7072 # Per bank write bursts +system.physmem.perBankWrBursts::10 7215 # Per bank write bursts +system.physmem.perBankWrBursts::11 7126 # Per bank write bursts +system.physmem.perBankWrBursts::12 7072 # Per bank write bursts +system.physmem.perBankWrBursts::13 7397 # Per bank write bursts +system.physmem.perBankWrBursts::14 7353 # Per bank write bursts +system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60000569500 # Total gap between requests +system.physmem.totGap 60093907500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165369 # Read request sizes (log2) +system.physmem.readPktSize::6 165736 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114468 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115250 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7195 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,126 +194,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.137094 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.166991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.705237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19617 35.84% 35.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11794 21.55% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5683 10.38% 67.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3657 6.68% 74.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2805 5.12% 79.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2027 3.70% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1612 2.95% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1505 2.75% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6036 11.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54736 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.474162 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.252876 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7042 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 47112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.637629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.425229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.616158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14360 30.48% 30.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9586 20.35% 50.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5012 10.64% 61.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3327 7.06% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2470 5.24% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1960 4.16% 77.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1618 3.43% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1472 3.12% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7307 15.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 47112 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.226489 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.911576 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 310.890099 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7133 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7044 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.246735 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.230854 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.753728 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6287 89.25% 89.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 12 0.17% 89.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 574 8.15% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 138 1.96% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 18 0.26% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 7 0.10% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7044 # Writes before turning the bus around for reads -system.physmem.totQLat 1985984500 # Total ticks spent queuing -system.physmem.totMemAccLat 5086540750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12009.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.149965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.141117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.557028 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6628 92.89% 92.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 11 0.15% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 441 6.18% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 47 0.66% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.10% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads +system.physmem.totQLat 1892978500 # Total ticks spent queuing +system.physmem.totMemAccLat 5000341000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 828630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11422.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30759.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 176.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 176.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30172.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 176.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 176.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.33 # Data bus utilization in percentage +system.physmem.busUtil 2.34 # Data bus utilization in percentage system.physmem.busUtilRead 1.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 143816 # Number of row buffer hits during reads -system.physmem.writeRowHits 81240 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.97 # Row buffer hit rate for writes -system.physmem.avgGap 214412.57 # Average gap between requests -system.physmem.pageHitRate 80.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 198964080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108561750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 636386400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 369061920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3918454800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12421358775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25100061000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42752848725 # Total energy per rank (pJ) -system.physmem_0.averagePower 712.626862 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41606215000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2003300000 # Time in different power states +system.physmem.avgWrQLen 23.81 # Average write queue length when enqueuing +system.physmem.readRowHits 144145 # Number of row buffer hits during reads +system.physmem.writeRowHits 89685 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.82 # Row buffer hit rate for writes +system.physmem.avgGap 213867.98 # Average gap between requests +system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 171128160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 93373500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 637486200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 370921680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12045269070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 25486025250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42728761380 # Total energy per rank (pJ) +system.physmem_0.averagePower 711.117850 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 42256937250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2006420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16383815000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15823407750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214545240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 117063375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 652945800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 372211200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3918454800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13100937570 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24503939250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42880097235 # Total energy per rank (pJ) -system.physmem_1.averagePower 714.747907 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40611255500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2003300000 # Time in different power states +system.physmem_1.actEnergy 184781520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 100823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654677400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 375431760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 12738285900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24878115750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42856673100 # Total energy per rank (pJ) +system.physmem_1.averagePower 713.246634 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41240527500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2006420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17379160000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16840206000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14695118 # Number of BP lookups -system.cpu.branchPred.condPredicted 9500860 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 385258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10182600 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6367092 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14696108 # Number of BP lookups +system.cpu.branchPred.condPredicted 9501028 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386035 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10214286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6368013 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.529138 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712185 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84621 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37568 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 62.344181 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1712199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84611 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37560 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 31792 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5776 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 5768 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 7597 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20578668 # DTB read hits -system.cpu.dtb.read_misses 95435 # DTB read misses +system.cpu.dtb.read_hits 20579333 # DTB read hits +system.cpu.dtb.read_misses 95423 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674103 # DTB read accesses -system.cpu.dtb.write_hits 14665915 # DTB write hits -system.cpu.dtb.write_misses 8842 # DTB write misses +system.cpu.dtb.read_accesses 20674756 # DTB read accesses +system.cpu.dtb.write_hits 14666035 # DTB write hits +system.cpu.dtb.write_misses 8840 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674757 # DTB write accesses -system.cpu.dtb.data_hits 35244583 # DTB hits -system.cpu.dtb.data_misses 104277 # DTB misses +system.cpu.dtb.write_accesses 14674875 # DTB write accesses +system.cpu.dtb.data_hits 35245368 # DTB hits +system.cpu.dtb.data_misses 104263 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35348860 # DTB accesses -system.cpu.itb.fetch_hits 25646396 # ITB hits -system.cpu.itb.fetch_misses 5177 # ITB misses +system.cpu.dtb.data_accesses 35349631 # DTB accesses +system.cpu.itb.fetch_hits 25649355 # ITB hits +system.cpu.itb.fetch_misses 5175 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25651573 # ITB accesses +system.cpu.itb.fetch_accesses 25654530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -327,16 +325,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120001186 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120187862 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1084586 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1085816 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.356895 # CPI: cycles per instruction -system.cpu.ipc 0.736977 # IPC: instructions per cycle +system.cpu.cpi 1.359006 # CPI: cycles per instruction +system.cpu.ipc 0.735832 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction @@ -372,58 +370,58 @@ system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 91986001 # Number of cycles that the object actually ticked -system.cpu.idleCycles 28015185 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200807 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.707874 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34647558 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204903 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.092488 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 690770500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.707874 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993825 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy +system.cpu.tickCycles 91997493 # Number of cycles that the object actually ticked +system.cpu.idleCycles 28190369 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 200806 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.595144 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34648172 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204902 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.096309 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 696470500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.595144 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993798 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993798 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 661 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3387 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3399 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70183301 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70183301 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314289 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314289 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333269 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333269 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34647558 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34647558 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34647558 # number of overall hits -system.cpu.dcache.overall_hits::total 34647558 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280108 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280108 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341641 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341641 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341641 # number of overall misses -system.cpu.dcache.overall_misses::total 341641 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2738549500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2738549500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21709876500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21709876500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24448426000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24448426000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24448426000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24448426000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20375822 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20375822 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70184522 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70184522 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20314904 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20314904 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333268 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333268 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34648172 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34648172 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34648172 # number of overall hits +system.cpu.dcache.overall_hits::total 34648172 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61529 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61529 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 341638 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 341638 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 341638 # number of overall misses +system.cpu.dcache.overall_misses::total 341638 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2787384000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2787384000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21745232000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21745232000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24532616000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24532616000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24532616000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24532616000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20376433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20376433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989199 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989199 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989199 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34989810 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34989810 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34989810 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34989810 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses @@ -432,46 +430,46 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009764 system.cpu.dcache.demand_miss_rate::total 0.009764 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009764 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009764 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44505.379227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44505.379227 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77505.378283 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77505.378283 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71561.744638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71561.744638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71561.744638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71561.744638 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45301.955176 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45301.955176 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77631.322092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77631.322092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71808.803470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71808.803470 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168446 # number of writebacks -system.cpu.dcache.writebacks::total 168446 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136541 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136541 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136738 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136738 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136738 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 136738 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61336 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61336 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168116 # number of writebacks +system.cpu.dcache.writebacks::total 168116 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 194 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136542 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136542 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 136736 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 136736 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 136736 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 136736 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61335 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61335 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204903 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204903 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204903 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204903 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2673829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2673829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10980283500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10980283500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13654113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13654113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13654113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13654113000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204902 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204902 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204902 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204902 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2722762000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2722762000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994246500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994246500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13717008500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13717008500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13717008500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13717008500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -480,332 +478,338 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43593.150841 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43593.150841 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76481.945712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76481.945712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66636.959927 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66636.959927 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66636.959927 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66636.959927 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 153927 # number of replacements -system.cpu.icache.tags.tagsinuse 1931.746995 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25490420 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 155975 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.426318 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42594058500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1931.746995 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943236 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943236 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44391.652401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44391.652401 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76579.203438 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76579.203438 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66944.239197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66944.239197 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 153916 # number of replacements +system.cpu.icache.tags.tagsinuse 1931.382130 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25493390 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155964 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 163.456887 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42683279500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1931.382130 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1033 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 801 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51448767 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51448767 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25490420 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25490420 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25490420 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25490420 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25490420 # number of overall hits -system.cpu.icache.overall_hits::total 25490420 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 155976 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 155976 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 155976 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 155976 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 155976 # number of overall misses -system.cpu.icache.overall_misses::total 155976 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2495053500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2495053500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2495053500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2495053500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2495053500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2495053500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25646396 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25646396 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25646396 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25646396 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25646396 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25646396 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006082 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006082 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006082 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006082 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15996.393676 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15996.393676 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15996.393676 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15996.393676 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15996.393676 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15996.393676 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51454674 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51454674 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25493390 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25493390 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25493390 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25493390 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25493390 # number of overall hits +system.cpu.icache.overall_hits::total 25493390 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 155965 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 155965 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 155965 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 155965 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 155965 # number of overall misses +system.cpu.icache.overall_misses::total 155965 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2518921000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2518921000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2518921000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2518921000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2518921000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2518921000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25649355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25649355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25649355 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25649355 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25649355 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25649355 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006081 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006081 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006081 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006081 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006081 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006081 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16150.553009 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16150.553009 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16150.553009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16150.553009 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 153927 # number of writebacks -system.cpu.icache.writebacks::total 153927 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155976 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 155976 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 155976 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 155976 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 155976 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 155976 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2339078500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2339078500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2339078500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2339078500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2339078500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2339078500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14996.400087 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14996.400087 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14996.400087 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14996.400087 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14996.400087 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14996.400087 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 133391 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30427.789253 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 406173 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 165503 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.454173 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26336.336681 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2098.353555 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1993.099017 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.803721 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064037 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.060825 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.928582 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1064 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 124 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979980 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 6033974 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 6033974 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168446 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168446 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 153927 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 153927 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12684 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12684 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149204 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 149204 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33621 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 33621 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 149204 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46305 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 195509 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 149204 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46305 # number of overall hits -system.cpu.l2cache.overall_hits::total 195509 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130883 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130883 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6772 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6772 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27715 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27715 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6772 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158598 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165370 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6772 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158598 # number of overall misses -system.cpu.l2cache.overall_misses::total 165370 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10631688000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10631688000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 538317500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 538317500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2228543000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2228543000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 538317500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12860231000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13398548500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 538317500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12860231000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13398548500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168446 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168446 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 153927 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 153927 # number of WritebackClean accesses(hits+misses) +system.cpu.icache.writebacks::writebacks 153916 # number of writebacks +system.cpu.icache.writebacks::total 153916 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155965 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 155965 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 155965 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 155965 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 155965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 155965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2362957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2362957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2362957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2362957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2362957000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2362957000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15150.559420 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15150.559420 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 135276 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31728.322423 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 547427 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 168044 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.257641 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 13928082000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 716.089195 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1994.899360 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29017.333867 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.021853 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060879 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.885539 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.968272 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 968 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9499 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22051 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 103 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 5892756 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 5892756 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 168116 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168116 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 153916 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 153916 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12659 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12659 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149116 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 149116 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33355 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 33355 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 149116 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46014 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 195130 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 149116 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46014 # number of overall hits +system.cpu.l2cache.overall_hits::total 195130 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 130908 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130908 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6849 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 6849 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27980 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 27980 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 6849 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158888 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 165737 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 6849 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158888 # number of overall misses +system.cpu.l2cache.overall_misses::total 165737 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10645913500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10645913500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 563137000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 563137000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2280269500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2280269500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 563137000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12926183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13489320000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 563137000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12926183000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13489320000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 168116 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168116 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 153916 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 153916 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143567 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 155976 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 155976 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61336 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 61336 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 155976 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204903 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 360879 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 155976 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204903 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 360879 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911651 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911651 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043417 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043417 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.451855 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.451855 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043417 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.774015 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.458242 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043417 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.774015 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.458242 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81230.473018 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81230.473018 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79491.656822 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79491.656822 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80409.272957 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80409.272957 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79491.656822 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81086.968310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81021.639354 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79491.656822 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81086.968310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81021.639354 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 155965 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 155965 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61335 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 61335 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 155965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204902 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 360867 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 155965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204902 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 360867 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911825 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911825 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043914 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043914 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456183 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456183 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043914 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775434 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.459274 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043914 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775434 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.459274 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81323.628044 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81323.628044 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82221.784202 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82221.784202 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81496.408149 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81496.408149 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82221.784202 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81354.054428 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81389.912934 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82221.784202 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81354.054428 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81389.912934 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 114468 # number of writebacks -system.cpu.l2cache.writebacks::total 114468 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 115 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 115 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130883 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130883 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6772 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6772 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27715 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27715 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6772 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158598 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165370 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6772 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158598 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165370 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9322858000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9322858000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 470607500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 470607500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1951393000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1951393000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 470607500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11274251000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11744858500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 470607500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11274251000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11744858500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 115251 # number of writebacks +system.cpu.l2cache.writebacks::total 115251 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 117 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6849 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6849 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27980 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27980 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6849 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158888 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165737 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6849 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158888 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165737 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9336833500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9336833500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 494657000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 494657000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2000469500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2000469500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 494657000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11337303000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11831960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 494657000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11337303000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11831960000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911651 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911651 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043417 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043417 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451855 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451855 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043417 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774015 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.458242 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043417 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774015 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.458242 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71230.473018 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71230.473018 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69493.133491 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69493.133491 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70409.272957 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70409.272957 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69493.133491 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71086.968310 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71021.699825 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69493.133491 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71086.968310 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71021.699825 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715613 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354734 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043914 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456183 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456183 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459274 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459274 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71323.628044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71323.628044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72223.244269 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72223.244269 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71496.408149 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71496.408149 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 715589 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 354722 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4027 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 282914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51284 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 217299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 153916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52715 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 155976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61336 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610613 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076491 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19833728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23894336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43728064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133391 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7325952 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 494270 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008147 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.089894 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 155965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61335 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610610 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1076455 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19832320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43705472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135276 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7376064 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 496143 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008584 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.092253 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 490243 99.19% 99.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4027 0.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 491884 99.14% 99.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 494270 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 680179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 496143 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 679826500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233962999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 233946499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307359989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307357491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34486 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114468 # Transaction distribution -system.membus.trans_dist::CleanEvict 15010 # Transaction distribution -system.membus.trans_dist::ReadExReq 130883 # Transaction distribution -system.membus.trans_dist::ReadExResp 130883 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34486 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460216 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460216 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17909568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17909568 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 296869 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 131133 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34828 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115250 # Transaction distribution +system.membus.trans_dist::CleanEvict 15883 # Transaction distribution +system.membus.trans_dist::ReadExReq 130908 # Transaction distribution +system.membus.trans_dist::ReadExResp 130908 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34828 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462605 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17983104 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 294847 # Request fanout histogram +system.membus.snoop_fanout::samples 165736 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294847 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165736 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294847 # Request fanout histogram -system.membus.reqLayer0.occupancy 819183500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 165736 # Request fanout histogram +system.membus.reqLayer0.occupancy 829286500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 873079500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 875094750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 4fef80875..4f7e5b26f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022275 # Number of seconds simulated -sim_ticks 22275010500 # Number of ticks simulated -final_tick 22275010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022294 # Number of seconds simulated +sim_ticks 22293541500 # Number of ticks simulated +final_tick 22293541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202670 # Simulator instruction rate (inst/s) -host_op_rate 202670 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56720302 # Simulator tick rate (ticks/s) -host_mem_usage 259380 # Number of bytes of host memory used -host_seconds 392.72 # Real time elapsed on the host +host_inst_rate 223643 # Simulator instruction rate (inst/s) +host_op_rate 223643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62642230 # Simulator tick rate (ticks/s) +host_mem_usage 265292 # Number of bytes of host memory used +host_seconds 355.89 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory -system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 409984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 409984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7322816 # Number of bytes written to this memory -system.physmem.bytes_written::total 7322816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158644 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165050 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114419 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114419 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18405558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455811951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 474217509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18405558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18405558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 328745793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 328745793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 328745793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18405558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455811951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 802963303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165050 # Number of read requests accepted -system.physmem.writeReqs 114419 # Number of write requests accepted -system.physmem.readBursts 165050 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114419 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10562816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7320960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10563200 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7322816 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 413888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10171008 # Number of bytes read from this memory +system.physmem.bytes_read::total 10584896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 413888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 413888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7372800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7372800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158922 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165389 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115200 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18565377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 456231147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 474796523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18565377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18565377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 330714615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 330714615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 330714615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18565377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 456231147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 805511139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165389 # Number of read requests accepted +system.physmem.writeReqs 115200 # Number of write requests accepted +system.physmem.readBursts 165389 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115200 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10584320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7371392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10584896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7372800 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10290 # Per bank write bursts -system.physmem.perBankRdBursts::1 10331 # Per bank write bursts -system.physmem.perBankRdBursts::2 10206 # Per bank write bursts -system.physmem.perBankRdBursts::3 10021 # Per bank write bursts -system.physmem.perBankRdBursts::4 10343 # Per bank write bursts -system.physmem.perBankRdBursts::5 10313 # Per bank write bursts -system.physmem.perBankRdBursts::6 9783 # Per bank write bursts -system.physmem.perBankRdBursts::7 10190 # Per bank write bursts -system.physmem.perBankRdBursts::8 10528 # Per bank write bursts -system.physmem.perBankRdBursts::9 10599 # Per bank write bursts -system.physmem.perBankRdBursts::10 10456 # Per bank write bursts -system.physmem.perBankRdBursts::11 10208 # Per bank write bursts -system.physmem.perBankRdBursts::12 10247 # Per bank write bursts -system.physmem.perBankRdBursts::13 10535 # Per bank write bursts -system.physmem.perBankRdBursts::14 10446 # Per bank write bursts -system.physmem.perBankRdBursts::15 10548 # Per bank write bursts -system.physmem.perBankWrBursts::0 7163 # Per bank write bursts -system.physmem.perBankWrBursts::1 7268 # Per bank write bursts -system.physmem.perBankWrBursts::2 7294 # Per bank write bursts -system.physmem.perBankWrBursts::3 7001 # Per bank write bursts -system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7177 # Per bank write bursts -system.physmem.perBankWrBursts::6 6836 # Per bank write bursts -system.physmem.perBankWrBursts::7 7101 # Per bank write bursts -system.physmem.perBankWrBursts::8 7221 # Per bank write bursts -system.physmem.perBankWrBursts::9 7003 # Per bank write bursts -system.physmem.perBankWrBursts::10 7101 # Per bank write bursts -system.physmem.perBankWrBursts::11 7022 # Per bank write bursts -system.physmem.perBankWrBursts::12 6991 # Per bank write bursts -system.physmem.perBankWrBursts::13 7296 # Per bank write bursts -system.physmem.perBankWrBursts::14 7307 # Per bank write bursts -system.physmem.perBankWrBursts::15 7482 # Per bank write bursts +system.physmem.perBankRdBursts::0 10310 # Per bank write bursts +system.physmem.perBankRdBursts::1 10350 # Per bank write bursts +system.physmem.perBankRdBursts::2 10221 # Per bank write bursts +system.physmem.perBankRdBursts::3 10037 # Per bank write bursts +system.physmem.perBankRdBursts::4 10349 # Per bank write bursts +system.physmem.perBankRdBursts::5 10325 # Per bank write bursts +system.physmem.perBankRdBursts::6 9802 # Per bank write bursts +system.physmem.perBankRdBursts::7 10210 # Per bank write bursts +system.physmem.perBankRdBursts::8 10556 # Per bank write bursts +system.physmem.perBankRdBursts::9 10619 # Per bank write bursts +system.physmem.perBankRdBursts::10 10516 # Per bank write bursts +system.physmem.perBankRdBursts::11 10224 # Per bank write bursts +system.physmem.perBankRdBursts::12 10277 # Per bank write bursts +system.physmem.perBankRdBursts::13 10556 # Per bank write bursts +system.physmem.perBankRdBursts::14 10475 # Per bank write bursts +system.physmem.perBankRdBursts::15 10553 # Per bank write bursts +system.physmem.perBankWrBursts::0 7167 # Per bank write bursts +system.physmem.perBankWrBursts::1 7278 # Per bank write bursts +system.physmem.perBankWrBursts::2 7300 # Per bank write bursts +system.physmem.perBankWrBursts::3 7008 # Per bank write bursts +system.physmem.perBankWrBursts::4 7143 # Per bank write bursts +system.physmem.perBankWrBursts::5 7301 # Per bank write bursts +system.physmem.perBankWrBursts::6 6892 # Per bank write bursts +system.physmem.perBankWrBursts::7 7161 # Per bank write bursts +system.physmem.perBankWrBursts::8 7241 # Per bank write bursts +system.physmem.perBankWrBursts::9 7068 # Per bank write bursts +system.physmem.perBankWrBursts::10 7202 # Per bank write bursts +system.physmem.perBankWrBursts::11 7125 # Per bank write bursts +system.physmem.perBankWrBursts::12 7069 # Per bank write bursts +system.physmem.perBankWrBursts::13 7390 # Per bank write bursts +system.physmem.perBankWrBursts::14 7350 # Per bank write bursts +system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22274979500 # Total gap between requests +system.physmem.totGap 22293510500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165050 # Read request sizes (log2) +system.physmem.readPktSize::6 165389 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114419 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115200 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,33 +145,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,127 +194,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.896604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 200.837447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.790414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18483 35.34% 35.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10568 20.20% 55.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5879 11.24% 66.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2936 5.61% 72.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2943 5.63% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1490 2.85% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2026 3.87% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 952 1.82% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7027 13.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52304 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.609728 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 338.236069 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6988 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6990 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.364807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.334911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.053834 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6086 87.07% 87.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.50% 87.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 455 6.51% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 219 3.13% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 100 1.43% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 53 0.76% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 22 0.31% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.16% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.10% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6990 # Writes before turning the bus around for reads -system.physmem.totQLat 5740232250 # Total ticks spent queuing -system.physmem.totMemAccLat 8834807250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 825220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34780.01 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 44806 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 400.727760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 239.628821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 367.162466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13215 29.49% 29.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8315 18.56% 48.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5340 11.92% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2750 6.14% 66.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2605 5.81% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1593 3.56% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1654 3.69% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1106 2.47% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8228 18.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 44806 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.298957 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.933264 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 317.077516 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7097 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7098 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.226824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.209944 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.780993 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6477 91.25% 91.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 22 0.31% 91.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 336 4.73% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 168 2.37% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 66 0.93% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 27 0.38% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7098 # Writes before turning the bus around for reads +system.physmem.totQLat 5599085250 # Total ticks spent queuing +system.physmem.totMemAccLat 8699960250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33855.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53530.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 474.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 328.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 474.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 328.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52605.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 474.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 330.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 474.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 330.71 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.27 # Data bus utilization in percentage -system.physmem.busUtilRead 3.70 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.57 # Data bus utilization in percentage for writes +system.physmem.busUtil 6.29 # Data bus utilization in percentage +system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.58 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing -system.physmem.readRowHits 145488 # Number of row buffer hits during reads -system.physmem.writeRowHits 81629 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.34 # Row buffer hit rate for writes -system.physmem.avgGap 79704.65 # Average gap between requests -system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190428840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 103904625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 635177400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368951760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6564184695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7603330500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16920459420 # Total energy per rank (pJ) -system.physmem_0.averagePower 759.821975 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12566232250 # Time in different power states -system.physmem_0.memoryStateTime::REF 743600000 # Time in different power states +system.physmem.avgWrQLen 24.72 # Average write queue length when enqueuing +system.physmem.readRowHits 145830 # Number of row buffer hits during reads +system.physmem.writeRowHits 89913 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes +system.physmem.avgGap 79452.55 # Average gap between requests +system.physmem.pageHitRate 84.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 163424520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 89170125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 636441000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 370882800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6110627715 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8015176500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16841729940 # Total energy per rank (pJ) +system.physmem_0.averagePower 755.495604 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 13256940500 # Time in different power states +system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8959159250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8290987000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204618960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111647250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 651565200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371861280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6822625545 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7376602500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 16993402335 # Total energy per rank (pJ) -system.physmem_1.averagePower 763.098971 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12188749750 # Time in different power states -system.physmem_1.memoryStateTime::REF 743600000 # Time in different power states +system.physmem_1.actEnergy 175218120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 95605125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 653343600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 375366960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6480752940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7690505250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 16926799275 # Total energy per rank (pJ) +system.physmem_1.averagePower 759.311692 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12714890500 # Time in different power states +system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9336732250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8833037000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16474744 # Number of BP lookups -system.cpu.branchPred.condPredicted 10670267 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 324432 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8918177 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7235165 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16464676 # Number of BP lookups +system.cpu.branchPred.condPredicted 10658312 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 322373 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8884191 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7232535 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.128296 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1973322 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3328 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 39379 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31470 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7909 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2657 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 81.409044 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1975403 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3321 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 39323 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31540 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7783 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2655 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22508484 # DTB read hits -system.cpu.dtb.read_misses 226837 # DTB read misses +system.cpu.dtb.read_hits 22505585 # DTB read hits +system.cpu.dtb.read_misses 226699 # DTB read misses system.cpu.dtb.read_acv 16 # DTB read access violations -system.cpu.dtb.read_accesses 22735321 # DTB read accesses -system.cpu.dtb.write_hits 15806842 # DTB write hits -system.cpu.dtb.write_misses 44564 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15851406 # DTB write accesses -system.cpu.dtb.data_hits 38315326 # DTB hits -system.cpu.dtb.data_misses 271401 # DTB misses -system.cpu.dtb.data_acv 20 # DTB access violations -system.cpu.dtb.data_accesses 38586727 # DTB accesses -system.cpu.itb.fetch_hits 13727245 # ITB hits -system.cpu.itb.fetch_misses 29559 # ITB misses +system.cpu.dtb.read_accesses 22732284 # DTB read accesses +system.cpu.dtb.write_hits 15808846 # DTB write hits +system.cpu.dtb.write_misses 44546 # DTB write misses +system.cpu.dtb.write_acv 6 # DTB write access violations +system.cpu.dtb.write_accesses 15853392 # DTB write accesses +system.cpu.dtb.data_hits 38314431 # DTB hits +system.cpu.dtb.data_misses 271245 # DTB misses +system.cpu.dtb.data_acv 22 # DTB access violations +system.cpu.dtb.data_accesses 38585676 # DTB accesses +system.cpu.itb.fetch_hits 13724143 # ITB hits +system.cpu.itb.fetch_misses 29345 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13756804 # ITB accesses +system.cpu.itb.fetch_accesses 13753488 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -328,142 +326,142 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44550025 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44587088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15536362 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105039044 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16474744 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9239957 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27563903 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 886514 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 244 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4722 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 331564 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 78 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13727245 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187963 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15537600 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105003279 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16464676 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9239478 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27573681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 883330 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4700 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 330450 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13724143 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187041 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43880130 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.393772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.128235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43888428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.392505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.127693 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24375049 55.55% 55.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1515026 3.45% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1375639 3.13% 62.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1503768 3.43% 65.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4189647 9.55% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1825739 4.16% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 668569 1.52% 80.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050805 2.39% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7375888 16.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24387762 55.57% 55.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1515251 3.45% 59.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1377134 3.14% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1500310 3.42% 65.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4190997 9.55% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1825571 4.16% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 669926 1.53% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050385 2.39% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7371092 16.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43880130 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369803 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.357777 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14899233 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9760394 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18283223 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 591754 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 345526 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3700749 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 99293 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103056970 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 314917 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 345526 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15243567 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4452634 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97322 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18515033 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5226048 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102057831 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7235 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 94720 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 348136 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4717245 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61355857 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123078605 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122759511 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319093 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43888428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369270 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.355015 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14897050 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9776190 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18280655 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 589828 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 344705 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3701787 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98635 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103032848 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312916 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 344705 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15240775 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4552016 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97125 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18511621 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5142186 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102032260 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5895 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 92509 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 354670 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4626637 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61342957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123044735 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122725402 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8808976 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5695 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5747 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2360993 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23135657 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16359365 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1252776 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 502701 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90727911 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5569 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88607473 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70141 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11141723 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4452155 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 986 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43880130 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.019307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.245631 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8796076 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5684 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5736 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2358572 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23134576 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16358313 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1246652 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 504576 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90719727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88603709 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 68043 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11133526 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4439018 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 973 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43888428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.018840 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.245634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17424086 39.71% 39.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5721163 13.04% 52.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5107482 11.64% 64.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4378378 9.98% 74.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4320360 9.85% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2636536 6.01% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1944467 4.43% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1375974 3.14% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 971684 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17434377 39.72% 39.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5720394 13.03% 52.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5103914 11.63% 64.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4383916 9.99% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4317842 9.84% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2637316 6.01% 90.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1940633 4.42% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1378295 3.14% 97.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 971741 2.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43880130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43888428 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243434 9.65% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1167545 46.27% 55.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1112329 44.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 241284 9.57% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1166228 46.24% 55.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1114848 44.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49382948 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43980 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49379489 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44005 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121151 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121171 0.14% 55.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120663 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120707 0.14% 56.05% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39093 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39092 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -485,82 +483,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22902831 25.85% 81.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15996653 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22899221 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15999870 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88607473 # Type of FU issued -system.cpu.iq.rate 1.988943 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2523308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028477 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223077288 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101475255 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86832445 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611237 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420100 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299852 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90825011 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305770 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1671661 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88603709 # Type of FU issued +system.cpu.iq.rate 1.987206 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2522360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223074890 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101458980 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86835527 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611359 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420488 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299878 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90820238 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305831 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1672227 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2859019 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5476 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20375 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1745988 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2857938 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5878 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20874 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1744936 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3024 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 205293 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3021 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 200758 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 345526 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1271875 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2754338 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100226384 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125320 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23135657 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16359365 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5569 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3722 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2752972 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20375 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 115768 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 151556 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 267324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87911556 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22736014 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 695917 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 344705 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1315985 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2729229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100214269 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 118431 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23134576 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16358313 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5556 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3898 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2727794 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20874 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 113179 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 152389 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 265568 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87909421 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22732927 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 694288 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9492904 # number of nop insts executed -system.cpu.iew.exec_refs 38587764 # number of memory reference insts executed -system.cpu.iew.exec_branches 15119893 # Number of branches executed -system.cpu.iew.exec_stores 15851750 # Number of stores executed -system.cpu.iew.exec_rate 1.973322 # Inst execution rate -system.cpu.iew.wb_sent 87534383 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87132297 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33840523 # num instructions producing a value -system.cpu.iew.wb_consumers 44256350 # num instructions consuming a value -system.cpu.iew.wb_rate 1.955830 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764648 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8655398 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9488986 # number of nop insts executed +system.cpu.iew.exec_refs 38586655 # number of memory reference insts executed +system.cpu.iew.exec_branches 15119960 # Number of branches executed +system.cpu.iew.exec_stores 15853728 # Number of stores executed +system.cpu.iew.exec_rate 1.971634 # Inst execution rate +system.cpu.iew.wb_sent 87537444 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87135405 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33842966 # num instructions producing a value +system.cpu.iew.wb_consumers 44247648 # num instructions consuming a value +system.cpu.iew.wb_rate 1.954274 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764853 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8653815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 226701 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42610108 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.073233 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.886041 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 225413 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42617548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.072871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.885939 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21149437 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6275459 14.73% 64.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2900348 6.81% 71.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1740796 4.09% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1682035 3.95% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1127009 2.64% 81.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1202859 2.82% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795530 1.87% 86.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5736635 13.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21149374 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6281932 14.74% 64.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2908445 6.82% 71.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1738602 4.08% 75.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1681485 3.95% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1121192 2.63% 81.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1200701 2.82% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 796598 1.87% 86.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5739219 13.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42610108 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42617548 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -606,465 +604,471 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5736635 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132552201 # The number of ROB reads -system.cpu.rob.rob_writes 195265380 # The number of ROB writes -system.cpu.timesIdled 45343 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 669895 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5739219 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 132555474 # The number of ROB reads +system.cpu.rob.rob_writes 195263120 # The number of ROB writes +system.cpu.timesIdled 45271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 698660 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.559732 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.559732 # CPI: Total CPI of All Threads -system.cpu.ipc 1.786570 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.786570 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116366061 # number of integer regfile reads -system.cpu.int_regfile_writes 57668563 # number of integer regfile writes -system.cpu.fp_regfile_reads 255567 # number of floating regfile reads -system.cpu.fp_regfile_writes 240367 # number of floating regfile writes -system.cpu.misc_regfile_reads 38271 # number of misc regfile reads +system.cpu.cpi 0.560197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.560197 # CPI: Total CPI of All Threads +system.cpu.ipc 1.785085 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.785085 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116363135 # number of integer regfile reads +system.cpu.int_regfile_writes 57669565 # number of integer regfile writes +system.cpu.fp_regfile_reads 255561 # number of floating regfile reads +system.cpu.fp_regfile_writes 240404 # number of floating regfile writes +system.cpu.misc_regfile_reads 38263 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 201418 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.642288 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33984828 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205514 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.365026 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 229821500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.642288 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993809 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 201400 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.443451 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33984025 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205496 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.375603 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 232048500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.443451 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993761 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2776 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1341 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70818146 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70818146 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20423642 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20423642 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561123 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561123 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33984765 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33984765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33984765 # number of overall hits -system.cpu.dcache.overall_hits::total 33984765 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269234 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269234 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052254 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052254 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321488 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321488 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321488 # number of overall misses -system.cpu.dcache.overall_misses::total 1321488 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17321162000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17321162000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89091667377 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89091667377 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106412829377 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106412829377 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106412829377 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106412829377 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20692876 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20692876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70817108 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70817108 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20422994 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20422994 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13560978 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13560978 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33983972 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33983972 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33983972 # number of overall hits +system.cpu.dcache.overall_hits::total 33983972 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269382 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269382 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052399 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052399 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1321781 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321781 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321781 # number of overall misses +system.cpu.dcache.overall_misses::total 1321781 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18043068500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18043068500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88421559159 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88421559159 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106464627659 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106464627659 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106464627659 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106464627659 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20692376 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20692376 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35306253 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35306253 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35306253 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35306253 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013011 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013011 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072006 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072006 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037429 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037429 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037429 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64334.972552 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64334.972552 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84667.454224 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84667.454224 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80525.006188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80525.006188 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6873080 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 89218 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35305753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35305753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35305753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35305753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013018 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072016 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072016 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037438 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037438 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037438 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037438 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66979.488236 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66979.488236 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84019.045209 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84019.045209 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80546.344409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80546.344409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6874865 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 86609 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.036921 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168806 # number of writebacks -system.cpu.dcache.writebacks::total 168806 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207108 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908866 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908866 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115974 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115974 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115974 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115974 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62126 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62126 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143388 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143388 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205514 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205514 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205514 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205514 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3205966000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3205966000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14246299714 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14246299714 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17452265714 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17452265714 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17452265714 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17452265714 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.378182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 139.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 168502 # number of writebacks +system.cpu.dcache.writebacks::total 168502 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207279 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207279 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 909006 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 909006 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1116285 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1116285 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1116285 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1116285 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62103 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62103 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143393 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143393 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205496 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205496 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205496 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205496 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3336459000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3336459000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14128429272 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14128429272 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17464888272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17464888272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17464888272 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17464888272 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003001 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003001 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005821 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005821 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51604.255867 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51604.255867 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99354.895207 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99354.895207 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 90292 # number of replacements -system.cpu.icache.tags.tagsinuse 1916.963164 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13622372 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 92340 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.524063 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18757985500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1916.963164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936017 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936017 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005820 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005820 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53724.602676 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53724.602676 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98529.421046 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98529.421046 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 90436 # number of replacements +system.cpu.icache.tags.tagsinuse 1916.490065 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13619166 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 92484 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.259699 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18779712500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1916.490065 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935786 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935786 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 384 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1460 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 389 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27546828 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27546828 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 13622372 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13622372 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13622372 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13622372 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13622372 # number of overall hits -system.cpu.icache.overall_hits::total 13622372 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 104872 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 104872 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 104872 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 104872 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 104872 # number of overall misses -system.cpu.icache.overall_misses::total 104872 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1921920999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1921920999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1921920999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1921920999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1921920999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1921920999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13727244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13727244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13727244 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13727244 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13727244 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13727244 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007640 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007640 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007640 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007640 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007640 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007640 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18326.350208 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18326.350208 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18326.350208 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18326.350208 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18326.350208 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18326.350208 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27540768 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27540768 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 13619166 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13619166 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13619166 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13619166 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13619166 # number of overall hits +system.cpu.icache.overall_hits::total 13619166 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 104976 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 104976 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 104976 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 104976 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 104976 # number of overall misses +system.cpu.icache.overall_misses::total 104976 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1956506499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1956506499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1956506499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1956506499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1956506499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1956506499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13724142 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13724142 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13724142 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13724142 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13724142 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13724142 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007649 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007649 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007649 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007649 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007649 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007649 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18637.655264 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18637.655264 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18637.655264 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18637.655264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18637.655264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18637.655264 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1136 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 75.733333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 90292 # number of writebacks -system.cpu.icache.writebacks::total 90292 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12531 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12531 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12531 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12531 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12531 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12531 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 92341 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 92341 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 92341 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 92341 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 92341 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 92341 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1570228500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1570228500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1570228500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1570228500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1570228500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1570228500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006727 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006727 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006727 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006727 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006727 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006727 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17004.672897 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17004.672897 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17004.672897 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 133082 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30595.837110 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 280630 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 165175 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.698986 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26800.034004 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1869.508141 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1926.294965 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.817872 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.058786 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.933711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32093 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3131 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28315 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 361 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979401 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5025086 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5025086 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168806 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168806 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 90292 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 90292 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12611 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12611 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 85934 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 85934 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 34259 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 34259 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 85934 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46870 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132804 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 85934 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46870 # number of overall hits -system.cpu.l2cache.overall_hits::total 132804 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130780 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130780 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6407 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6407 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27864 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27864 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6407 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158644 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165051 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6407 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158644 # number of overall misses -system.cpu.l2cache.overall_misses::total 165051 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13894688000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13894688000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 524890500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 524890500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2748099000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2748099000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 524890500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 16642787000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17167677500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 524890500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 16642787000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17167677500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168806 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168806 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 90292 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 90292 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143391 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143391 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 92341 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 92341 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62123 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 62123 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 92341 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205514 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 297855 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 92341 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205514 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 297855 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912052 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912052 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069384 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.069384 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.448530 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.448530 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069384 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771938 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.554132 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069384 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771938 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.554132 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106244.746903 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106244.746903 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81924.535664 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81924.535664 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98625.430663 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98625.430663 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81924.535664 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104906.501349 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 104014.380404 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81924.535664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104906.501349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 104014.380404 # average overall miss latency +system.cpu.icache.writebacks::writebacks 90436 # number of writebacks +system.cpu.icache.writebacks::total 90436 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12491 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12491 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12491 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12491 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12491 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12491 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 92485 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 92485 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 92485 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 92485 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 92485 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 92485 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1595124000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1595124000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1595124000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1595124000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1595124000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1595124000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006739 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006739 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006739 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006739 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006739 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006739 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17247.380656 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17247.380656 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17247.380656 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17247.380656 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17247.380656 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17247.380656 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 134874 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31863.975507 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 422062 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 167642 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.517639 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 4859656000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 722.364840 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1777.470792 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29364.139876 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.022045 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.054244 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.896122 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.972411 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2938 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 29364 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 202 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4886178 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4886178 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 168502 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168502 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 90436 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 90436 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12584 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12584 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 86017 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 86017 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33990 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 33990 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 86017 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46574 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132591 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 86017 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46574 # number of overall hits +system.cpu.l2cache.overall_hits::total 132591 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 130811 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130811 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6468 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 6468 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28111 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 28111 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 6468 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158922 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 165390 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 6468 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158922 # number of overall misses +system.cpu.l2cache.overall_misses::total 165390 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13777150000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13777150000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 548837500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 548837500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2881866500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2881866500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 548837500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 16659016500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17207854000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 548837500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 16659016500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17207854000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 168502 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168502 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 90436 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 90436 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143395 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143395 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 92485 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 92485 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62101 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 62101 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 92485 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205496 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 297981 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 92485 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205496 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 297981 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912242 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912242 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069936 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.069936 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452666 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452666 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069936 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773358 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.555035 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069936 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773358 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.555035 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105321.035693 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105321.035693 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84854.282622 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84854.282622 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102517.395326 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102517.395326 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84854.282622 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104825.112319 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 104044.101820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84854.282622 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104825.112319 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104044.101820 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 114419 # number of writebacks -system.cpu.l2cache.writebacks::total 114419 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130780 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130780 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6407 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6407 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27864 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27864 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6407 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158644 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165051 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6407 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158644 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165051 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12586888000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12586888000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 460830500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 460830500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2469459000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2469459000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 460830500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15056347000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15517177500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 460830500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15056347000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15517177500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 115201 # number of writebacks +system.cpu.l2cache.writebacks::total 115201 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 112 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 112 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130811 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130811 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6468 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6468 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165390 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6468 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158922 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165390 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12469040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12469040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 484167500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 484167500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2600756500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2600756500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 484167500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15069796500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15553964000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 484167500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15069796500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15553964000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912052 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912052 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069384 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448530 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448530 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.554132 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.554132 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96244.746903 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96244.746903 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71926.096457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71926.096457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88625.430663 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88625.430663 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 589565 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 291710 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912242 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912242 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069936 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452666 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452666 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555035 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95321.035693 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95321.035693 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74855.828695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74855.828695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92517.395326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92517.395326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 589817 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 291836 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4045 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4239 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 154463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283225 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 90292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 92341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62123 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 274973 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887419 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11688448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23956480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35644928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133082 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7322816 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 430937 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009387 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.096428 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 154585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 90436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52571 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 92485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275405 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887797 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11706880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23935872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35642752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134874 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7372864 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 432855 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009793 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098475 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 426892 99.06% 99.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4045 0.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 428616 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4239 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 430937 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 553880500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432855 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 553846500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 138521976 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 138734483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308281978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308248491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34270 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114419 # Transaction distribution -system.membus.trans_dist::CleanEvict 14728 # Transaction distribution -system.membus.trans_dist::ReadExReq 130780 # Transaction distribution -system.membus.trans_dist::ReadExResp 130780 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34270 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 459247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 459247 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17886016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17886016 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 130746 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34578 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115200 # Transaction distribution +system.membus.trans_dist::CleanEvict 15546 # Transaction distribution +system.membus.trans_dist::ReadExReq 130811 # Transaction distribution +system.membus.trans_dist::ReadExResp 130811 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34578 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 461524 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17957696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 294197 # Request fanout histogram +system.membus.snoop_fanout::samples 165389 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294197 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165389 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294197 # Request fanout histogram -system.membus.reqLayer0.occupancy 776999500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 165389 # Request fanout histogram +system.membus.reqLayer0.occupancy 780841500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 852713250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 854544750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 50bae5738..7abf225fd 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058768 # Number of seconds simulated -sim_ticks 58768125500 # Number of ticks simulated -final_tick 58768125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058750 # Number of seconds simulated +sim_ticks 58750410500 # Number of ticks simulated +final_tick 58750410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140139 # Simulator instruction rate (inst/s) -host_op_rate 179217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116134728 # Simulator tick rate (ticks/s) -host_mem_usage 275656 # Number of bytes of host memory used -host_seconds 506.03 # Real time elapsed on the host +host_inst_rate 179920 # Simulator instruction rate (inst/s) +host_op_rate 230092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149057017 # Simulator tick rate (ticks/s) +host_mem_usage 281832 # Number of bytes of host memory used +host_seconds 394.15 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 285632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory -system.physmem.bytes_read::total 8210304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 285632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 285632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5517568 # Number of bytes written to this memory -system.physmem.bytes_written::total 5517568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128286 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86212 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86212 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4860322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 134846431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139706753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4860322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4860322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 93887085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 93887085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 93887085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4860322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 134846431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 233593838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128286 # Number of read requests accepted -system.physmem.writeReqs 86212 # Number of write requests accepted -system.physmem.readBursts 128286 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 86212 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8209920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5515840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8210304 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5517568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory +system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory +system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 4873770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 135124571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139998341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4873770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4873770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94285775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94285775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94285775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4873770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 135124571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 234284116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128515 # Number of read requests accepted +system.physmem.writeReqs 86552 # Number of write requests accepted +system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 5537600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8065 # Per bank write bursts -system.physmem.perBankRdBursts::1 8314 # Per bank write bursts -system.physmem.perBankRdBursts::2 8239 # Per bank write bursts -system.physmem.perBankRdBursts::3 8142 # Per bank write bursts -system.physmem.perBankRdBursts::4 8284 # Per bank write bursts -system.physmem.perBankRdBursts::5 8404 # Per bank write bursts -system.physmem.perBankRdBursts::6 8054 # Per bank write bursts -system.physmem.perBankRdBursts::7 7915 # Per bank write bursts -system.physmem.perBankRdBursts::8 8035 # Per bank write bursts -system.physmem.perBankRdBursts::9 7585 # Per bank write bursts -system.physmem.perBankRdBursts::10 7763 # Per bank write bursts -system.physmem.perBankRdBursts::11 7814 # Per bank write bursts -system.physmem.perBankRdBursts::12 7871 # Per bank write bursts -system.physmem.perBankRdBursts::13 7866 # Per bank write bursts -system.physmem.perBankRdBursts::14 7967 # Per bank write bursts -system.physmem.perBankRdBursts::15 7962 # Per bank write bursts -system.physmem.perBankWrBursts::0 5395 # Per bank write bursts -system.physmem.perBankWrBursts::1 5541 # Per bank write bursts -system.physmem.perBankWrBursts::2 5468 # Per bank write bursts -system.physmem.perBankWrBursts::3 5336 # Per bank write bursts -system.physmem.perBankWrBursts::4 5363 # Per bank write bursts -system.physmem.perBankWrBursts::5 5561 # Per bank write bursts -system.physmem.perBankWrBursts::6 5259 # Per bank write bursts -system.physmem.perBankWrBursts::7 5180 # Per bank write bursts -system.physmem.perBankWrBursts::8 5154 # Per bank write bursts -system.physmem.perBankWrBursts::9 5103 # Per bank write bursts -system.physmem.perBankWrBursts::10 5293 # Per bank write bursts -system.physmem.perBankWrBursts::11 5270 # Per bank write bursts -system.physmem.perBankWrBursts::12 5531 # Per bank write bursts +system.physmem.perBankRdBursts::0 8086 # Per bank write bursts +system.physmem.perBankRdBursts::1 8335 # Per bank write bursts +system.physmem.perBankRdBursts::2 8257 # Per bank write bursts +system.physmem.perBankRdBursts::3 8155 # Per bank write bursts +system.physmem.perBankRdBursts::4 8301 # Per bank write bursts +system.physmem.perBankRdBursts::5 8413 # Per bank write bursts +system.physmem.perBankRdBursts::6 8070 # Per bank write bursts +system.physmem.perBankRdBursts::7 7917 # Per bank write bursts +system.physmem.perBankRdBursts::8 8053 # Per bank write bursts +system.physmem.perBankRdBursts::9 7612 # Per bank write bursts +system.physmem.perBankRdBursts::10 7771 # Per bank write bursts +system.physmem.perBankRdBursts::11 7825 # Per bank write bursts +system.physmem.perBankRdBursts::12 7888 # Per bank write bursts +system.physmem.perBankRdBursts::13 7870 # Per bank write bursts +system.physmem.perBankRdBursts::14 7981 # Per bank write bursts +system.physmem.perBankRdBursts::15 7974 # Per bank write bursts +system.physmem.perBankWrBursts::0 5399 # Per bank write bursts +system.physmem.perBankWrBursts::1 5549 # Per bank write bursts +system.physmem.perBankWrBursts::2 5476 # Per bank write bursts +system.physmem.perBankWrBursts::3 5348 # Per bank write bursts +system.physmem.perBankWrBursts::4 5387 # Per bank write bursts +system.physmem.perBankWrBursts::5 5588 # Per bank write bursts +system.physmem.perBankWrBursts::6 5325 # Per bank write bursts +system.physmem.perBankWrBursts::7 5260 # Per bank write bursts +system.physmem.perBankWrBursts::8 5187 # Per bank write bursts +system.physmem.perBankWrBursts::9 5136 # Per bank write bursts +system.physmem.perBankWrBursts::10 5306 # Per bank write bursts +system.physmem.perBankWrBursts::11 5279 # Per bank write bursts +system.physmem.perBankWrBursts::12 5541 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts -system.physmem.perBankWrBursts::14 5703 # Per bank write bursts -system.physmem.perBankWrBursts::15 5431 # Per bank write bursts +system.physmem.perBankWrBursts::14 5706 # Per bank write bursts +system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58768094000 # Total gap between requests +system.physmem.totGap 58750379000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128286 # Read request sizes (log2) +system.physmem.readPktSize::6 128515 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 86212 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86552 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12249 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,106 +194,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38803 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.665026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 214.783131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.990632 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12260 31.60% 31.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8290 21.36% 52.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4146 10.68% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2807 7.23% 70.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2540 6.55% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1701 4.38% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1262 3.25% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1176 3.03% 88.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4621 11.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38803 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.212911 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.385643 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5295 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 32968 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 417.384130 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 256.722785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 362.908382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8749 26.54% 26.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6430 19.50% 46.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3309 10.04% 56.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2430 7.37% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2267 6.88% 70.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1599 4.85% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1281 3.89% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1267 3.84% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5636 17.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32968 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5346 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.036289 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.665302 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.416280 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5344 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.269398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.253066 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.759205 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4663 88.03% 88.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.13% 88.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 496 9.36% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 106 2.00% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16 0.30% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8 0.15% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5297 # Writes before turning the bus around for reads -system.physmem.totQLat 1679255750 # Total ticks spent queuing -system.physmem.totMemAccLat 4084505750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 641400000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13090.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5346 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.184998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.174634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.600598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4870 91.10% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 4 0.07% 91.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 438 8.19% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 27 0.51% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5346 # Writes before turning the bus around for reads +system.physmem.totQLat 1552277750 # Total ticks spent queuing +system.physmem.totMemAccLat 3961802750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12079.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31840.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 139.70 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 93.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 139.71 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 93.89 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30829.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 139.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 94.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 140.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 94.29 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.82 # Data bus utilization in percentage +system.physmem.busUtil 1.83 # Data bus utilization in percentage system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing -system.physmem.readRowHits 111800 # Number of row buffer hits during reads -system.physmem.writeRowHits 63851 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.06 # Row buffer hit rate for writes -system.physmem.avgGap 273979.68 # Average gap between requests -system.physmem.pageHitRate 81.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153014400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83490000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 509886000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 279190800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11659704255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25030042500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41553430275 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.134890 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41510709500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1962220000 # Time in different power states +system.physmem.avgWrQLen 23.56 # Average write queue length when enqueuing +system.physmem.readRowHits 112029 # Number of row buffer hits during reads +system.physmem.writeRowHits 70027 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.91 # Row buffer hit rate for writes +system.physmem.avgGap 273172.45 # Average gap between requests +system.physmem.pageHitRate 84.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 130599000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 71259375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 511009200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 280655280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11237331690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 25391203500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41459143245 # Total energy per rank (pJ) +system.physmem_0.averagePower 705.717335 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 42124223000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1961700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15290173000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14661610750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140215320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76506375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 490152000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 279145440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11133864720 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 25491305250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41449291425 # Total energy per rank (pJ) -system.physmem_1.averagePower 705.362708 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 42280803500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1962220000 # Time in different power states +system.physmem_1.actEnergy 118555920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 64688250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 491072400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 279819360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10919729115 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 25669800000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41380750245 # Total energy per rank (pJ) +system.physmem_1.averagePower 704.382975 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 42589738750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1961700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14520166000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14196261750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14827521 # Number of BP lookups -system.cpu.branchPred.condPredicted 9922528 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 342114 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9663077 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6571727 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14827613 # Number of BP lookups +system.cpu.branchPred.condPredicted 9922572 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 342024 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9662819 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6571830 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.008637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719937 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 68.011519 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720035 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 176106 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 158425 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 17681 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 24889 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 175655 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 158613 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -323,7 +321,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -353,7 +351,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,7 +381,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,16 +412,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117536251 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117500821 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1179302 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1179078 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.657421 # CPI: cycles per instruction -system.cpu.ipc 0.603347 # IPC: instructions per cycle +system.cpu.cpi 1.656921 # CPI: cycles per instruction +system.cpu.ipc 0.603529 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -459,474 +457,480 @@ system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 97988256 # Number of cycles that the object actually ticked -system.cpu.idleCycles 19547995 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 156444 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.129500 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637241 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160540 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.586402 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 821026500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.129500 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993196 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993196 # Average percentage of cache occupancy +system.cpu.tickCycles 97998947 # Number of cycles that the object actually ticked +system.cpu.idleCycles 19501874 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 156451 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.791520 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42637484 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.576336 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 830343500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.791520 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993113 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993113 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2952 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1054 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2998 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86035236 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86035236 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22879875 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22879875 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642158 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83370 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83370 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86035297 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86035297 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22880319 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22880319 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642152 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642152 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83175 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83175 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522033 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522033 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605403 # number of overall hits -system.cpu.dcache.overall_hits::total 42605403 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 47768 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 47768 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207743 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207743 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44596 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44596 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 255511 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 255511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 300107 # number of overall misses -system.cpu.dcache.overall_misses::total 300107 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1443300500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1443300500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16810663000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16810663000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18253963500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18253963500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18253963500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18253963500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927643 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927643 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42522471 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42522471 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42605646 # number of overall hits +system.cpu.dcache.overall_hits::total 42605646 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 47369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 47369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207749 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207749 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44773 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44773 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 255118 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 255118 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 299891 # number of overall misses +system.cpu.dcache.overall_misses::total 299891 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1548941500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1548941500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16628210000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16628210000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18177151500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18177151500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18177151500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18177151500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22927688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22927688 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 127966 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 127966 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127948 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777544 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777544 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905510 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905510 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002083 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002083 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42777589 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42777589 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42905537 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42905537 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002066 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348499 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348499 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005973 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005973 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006995 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006995 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30214.798610 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30214.798610 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80920.478668 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80920.478668 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71441.008411 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71441.008411 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60824.850803 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60824.850803 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349931 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.349931 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005964 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005964 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006990 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006990 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32699.476451 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32699.476451 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80039.903923 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80039.903923 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71249.976481 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71249.976481 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60612.527552 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 128383 # number of writebacks -system.cpu.dcache.writebacks::total 128383 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 18246 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 18246 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100706 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100706 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 118952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 118952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 118952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 118952 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29522 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29522 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks +system.cpu.dcache.writebacks::total 128145 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17840 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 17840 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100712 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100712 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 118552 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 118552 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 118552 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 118552 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136559 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136559 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160540 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160540 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 576668000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 576668000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488003000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488003000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1709526500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1709526500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9064671000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9064671000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10774197500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10774197500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 586674000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 586674000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401236500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401236500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788829000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788829000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8987910500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10776739500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10776739500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187401 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187401 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187428 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187428 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19533.500440 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19533.500440 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79299.709446 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79299.709446 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71286.706142 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71286.706142 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66379.154798 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66379.154798 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67112.230597 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67112.230597 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 43538 # number of replacements -system.cpu.icache.tags.tagsinuse 1854.967198 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25047260 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 45580 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 549.523036 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19867.723255 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19867.723255 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78489.087885 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78489.087885 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74593.594929 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74593.594929 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65813.676171 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65813.676171 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67125.137810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67125.137810 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 43545 # number of replacements +system.cpu.icache.tags.tagsinuse 1854.190293 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25047618 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 549.446509 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1854.967198 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.905746 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.905746 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1854.190293 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.905366 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.905366 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 907 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1012 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 913 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50231262 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50231262 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25047260 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25047260 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25047260 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25047260 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25047260 # number of overall hits -system.cpu.icache.overall_hits::total 25047260 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 45581 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 45581 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 45581 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 45581 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 45581 # number of overall misses -system.cpu.icache.overall_misses::total 45581 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 906370500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 906370500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 906370500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 906370500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 906370500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 906370500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25092841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25092841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25092841 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25092841 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25092841 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25092841 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001816 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001816 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001816 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001816 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001816 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001816 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19884.831399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19884.831399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19884.831399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19884.831399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19884.831399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19884.831399 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50231999 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50231999 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25047618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25047618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25047618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25047618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25047618 # number of overall hits +system.cpu.icache.overall_hits::total 25047618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses +system.cpu.icache.overall_misses::total 45588 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 918433000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 918433000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 918433000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 918433000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 918433000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 918433000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25093206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25093206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25093206 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25093206 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25093206 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25093206 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20146.376239 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20146.376239 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20146.376239 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20146.376239 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 43538 # number of writebacks -system.cpu.icache.writebacks::total 43538 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45581 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 45581 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 45581 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 45581 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 45581 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 45581 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 860790500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 860790500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 860790500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 860790500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 860790500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 860790500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001816 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001816 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001816 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001816 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001816 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001816 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18884.853338 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18884.853338 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18884.853338 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18884.853338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18884.853338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18884.853338 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 96393 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29915.680999 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 163475 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127546 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.281694 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26835.960013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1436.225853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1643.495133 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.818969 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043830 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050155 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.912954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15761 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 596 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3420655 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3420655 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 128383 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 128383 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 39935 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 39935 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4757 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4757 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41105 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 41105 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31900 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31900 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 41105 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36657 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 77762 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 41105 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36657 # number of overall hits -system.cpu.l2cache.overall_hits::total 77762 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4476 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 4476 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21603 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21603 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4476 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123883 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128359 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4476 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123883 # number of overall misses -system.cpu.l2cache.overall_misses::total 128359 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8277452000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8277452000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356943000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 356943000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1866770000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1866770000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 356943000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10144222000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10501165000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 356943000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10144222000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10501165000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 128383 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 128383 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 39935 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 39935 # number of WritebackClean accesses(hits+misses) +system.cpu.icache.writebacks::writebacks 43545 # number of writebacks +system.cpu.icache.writebacks::total 43545 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45588 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 45588 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 45588 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 872846000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 872846000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 872846000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 872846000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 872846000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 872846000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19146.398175 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19146.398175 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 97176 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31328.460689 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 268173 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.063758 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 10596662000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 480.299456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1381.968758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29466.192474 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.014658 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042174 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.899237 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.956069 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1189 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13615 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17003 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 39944 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4720 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41100 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 41100 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31726 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 31726 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 41100 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36446 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 77546 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 41100 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36446 # number of overall hits +system.cpu.l2cache.overall_hits::total 77546 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 102317 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102317 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4488 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 4488 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21784 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21784 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4488 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 124101 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128589 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4488 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses +system.cpu.l2cache.overall_misses::total 128589 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8191072500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8191072500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 369038000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 369038000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1957896000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1957896000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 369038000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10148968500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10518006500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 369038000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10148968500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10518006500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 39944 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45581 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 45581 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53503 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 53503 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 45581 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 160540 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 206121 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 45581 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 160540 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 206121 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955557 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955557 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098199 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098199 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403772 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403772 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098199 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.622736 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098199 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.622736 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80929.331248 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80929.331248 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79745.978552 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79745.978552 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86412.535296 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86412.535296 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79745.978552 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81885.504872 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81810.897561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79745.978552 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81885.504872 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81810.897561 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45588 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 45588 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 45588 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160547 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 206135 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 45588 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160547 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098447 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098447 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098447 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.623810 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098447 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.623810 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80055.831387 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80055.831387 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82227.718360 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82227.718360 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89877.708410 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89877.708410 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81795.538499 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81795.538499 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 86212 # number of writebacks -system.cpu.l2cache.writebacks::total 86212 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks +system.cpu.l2cache.writebacks::total 86552 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4464 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4464 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21543 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21543 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4464 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128287 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4464 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128287 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7254652000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7254652000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 311353500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 311353500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1646809500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1646809500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 311353500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8901461500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9212815000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 311353500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8901461500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9212815000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7167902500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7167902500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 323146000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 323146000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1736095500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1736095500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 323146000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8903998000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9227144000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 323146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8903998000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9227144000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097936 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402650 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402650 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771291 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.622387 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771291 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.622387 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70929.331248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70929.331248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69747.647849 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69747.647849 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76442.904888 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76442.904888 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 406103 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 200020 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 99083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214595 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 43538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 38242 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 45581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477524 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 612223 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5703552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24194624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 96393 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5517568 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 302514 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.037258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.189899 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 97176 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 291272 96.28% 96.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11213 3.71% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 302514 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 374972500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68384970 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68396468 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240842435 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 26006 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86212 # Transaction distribution -system.membus.trans_dist::CleanEvict 6916 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26006 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 349700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13727872 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 26198 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution +system.membus.trans_dist::CleanEvict 7237 # Transaction distribution +system.membus.trans_dist::ReadExReq 102317 # Transaction distribution +system.membus.trans_dist::ReadExResp 102317 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 221414 # Request fanout histogram +system.membus.snoop_fanout::samples 128515 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 221414 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 221414 # Request fanout histogram -system.membus.reqLayer0.occupancy 586752500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 128515 # Request fanout histogram +system.membus.reqLayer0.occupancy 587526000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 676437000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 677474000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 854b1472f..7d5e42cd5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033525 # Number of seconds simulated -sim_ticks 33524756000 # Number of ticks simulated -final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.037283 # Number of seconds simulated +sim_ticks 37283333000 # Number of ticks simulated +final_tick 37283333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128434 # Simulator instruction rate (inst/s) -host_op_rate 164252 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60722809 # Simulator tick rate (ticks/s) -host_mem_usage 277836 # Number of bytes of host memory used -host_seconds 552.10 # Real time elapsed on the host +host_inst_rate 125888 # Simulator instruction rate (inst/s) +host_op_rate 160996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66191855 # Simulator tick rate (ticks/s) +host_mem_usage 284264 # Number of bytes of host memory used +host_seconds 563.26 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory -system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 697984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 697984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6216960 # Number of bytes written to this memory -system.physmem.bytes_written::total 6216960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 45743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 153088 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97140 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97140 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20819958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 87325080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 184105620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 292250658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20819958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20819958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 185443855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 185443855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 185443855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20819958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 87325080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 184105620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 477694513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 153089 # Number of read requests accepted -system.physmem.writeReqs 97140 # Number of write requests accepted -system.physmem.readBursts 153089 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97140 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9788224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 6215872 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9797696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6216960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2379328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5690752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6174592 # Number of bytes read from this memory +system.physmem.bytes_read::total 14244672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2379328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2379328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6224768 # Number of bytes written to this memory +system.physmem.bytes_written::total 6224768 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 37177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88918 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96478 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222573 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97262 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97262 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 63817470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 152635281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 165612661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 382065412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 63817470 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 63817470 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166958464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166958464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166958464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 63817470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 152635281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 165612661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 549023876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222574 # Number of read requests accepted +system.physmem.writeReqs 97262 # Number of write requests accepted +system.physmem.readBursts 222574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97262 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14235136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 6223360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14244736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6224768 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9103 # Per bank write bursts -system.physmem.perBankRdBursts::1 9407 # Per bank write bursts -system.physmem.perBankRdBursts::2 9452 # Per bank write bursts -system.physmem.perBankRdBursts::3 11458 # Per bank write bursts -system.physmem.perBankRdBursts::4 10748 # Per bank write bursts -system.physmem.perBankRdBursts::5 11390 # Per bank write bursts -system.physmem.perBankRdBursts::6 10031 # Per bank write bursts -system.physmem.perBankRdBursts::7 8920 # Per bank write bursts -system.physmem.perBankRdBursts::8 9321 # Per bank write bursts -system.physmem.perBankRdBursts::9 9437 # Per bank write bursts -system.physmem.perBankRdBursts::10 9070 # Per bank write bursts -system.physmem.perBankRdBursts::11 9080 # Per bank write bursts -system.physmem.perBankRdBursts::12 8731 # Per bank write bursts -system.physmem.perBankRdBursts::13 8724 # Per bank write bursts -system.physmem.perBankRdBursts::14 9025 # Per bank write bursts -system.physmem.perBankRdBursts::15 9044 # Per bank write bursts -system.physmem.perBankWrBursts::0 5968 # Per bank write bursts -system.physmem.perBankWrBursts::1 6230 # Per bank write bursts -system.physmem.perBankWrBursts::2 6083 # Per bank write bursts -system.physmem.perBankWrBursts::3 6155 # Per bank write bursts -system.physmem.perBankWrBursts::4 6058 # Per bank write bursts -system.physmem.perBankWrBursts::5 6286 # Per bank write bursts -system.physmem.perBankWrBursts::6 6021 # Per bank write bursts -system.physmem.perBankWrBursts::7 5958 # Per bank write bursts -system.physmem.perBankWrBursts::8 5969 # Per bank write bursts -system.physmem.perBankWrBursts::9 6064 # Per bank write bursts -system.physmem.perBankWrBursts::10 6185 # Per bank write bursts -system.physmem.perBankWrBursts::11 5907 # Per bank write bursts -system.physmem.perBankWrBursts::12 6058 # Per bank write bursts -system.physmem.perBankWrBursts::13 6089 # Per bank write bursts -system.physmem.perBankWrBursts::14 6121 # Per bank write bursts -system.physmem.perBankWrBursts::15 5971 # Per bank write bursts +system.physmem.perBankRdBursts::0 9684 # Per bank write bursts +system.physmem.perBankRdBursts::1 9951 # Per bank write bursts +system.physmem.perBankRdBursts::2 12571 # Per bank write bursts +system.physmem.perBankRdBursts::3 25345 # Per bank write bursts +system.physmem.perBankRdBursts::4 17391 # Per bank write bursts +system.physmem.perBankRdBursts::5 22070 # Per bank write bursts +system.physmem.perBankRdBursts::6 11722 # Per bank write bursts +system.physmem.perBankRdBursts::7 14054 # Per bank write bursts +system.physmem.perBankRdBursts::8 11726 # Per bank write bursts +system.physmem.perBankRdBursts::9 15447 # Per bank write bursts +system.physmem.perBankRdBursts::10 11755 # Per bank write bursts +system.physmem.perBankRdBursts::11 11322 # Per bank write bursts +system.physmem.perBankRdBursts::12 9441 # Per bank write bursts +system.physmem.perBankRdBursts::13 9563 # Per bank write bursts +system.physmem.perBankRdBursts::14 9879 # Per bank write bursts +system.physmem.perBankRdBursts::15 20503 # Per bank write bursts +system.physmem.perBankWrBursts::0 5981 # Per bank write bursts +system.physmem.perBankWrBursts::1 6205 # Per bank write bursts +system.physmem.perBankWrBursts::2 6090 # Per bank write bursts +system.physmem.perBankWrBursts::3 6159 # Per bank write bursts +system.physmem.perBankWrBursts::4 6110 # Per bank write bursts +system.physmem.perBankWrBursts::5 6252 # Per bank write bursts +system.physmem.perBankWrBursts::6 5998 # Per bank write bursts +system.physmem.perBankWrBursts::7 5984 # Per bank write bursts +system.physmem.perBankWrBursts::8 5961 # Per bank write bursts +system.physmem.perBankWrBursts::9 6093 # Per bank write bursts +system.physmem.perBankWrBursts::10 6222 # Per bank write bursts +system.physmem.perBankWrBursts::11 5895 # Per bank write bursts +system.physmem.perBankWrBursts::12 6037 # Per bank write bursts +system.physmem.perBankWrBursts::13 6052 # Per bank write bursts +system.physmem.perBankWrBursts::14 6175 # Per bank write bursts +system.physmem.perBankWrBursts::15 6026 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33524744500 # Total gap between requests +system.physmem.totGap 37283321500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153089 # Read request sizes (log2) +system.physmem.readPktSize::6 222574 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97140 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 50282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97262 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 113358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,107 +198,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 96335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 166.118316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 104.810468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 234.858667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 60546 62.85% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22368 23.22% 86.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3987 4.14% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1542 1.60% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 931 0.97% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 863 0.90% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 636 0.66% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 773 0.80% 95.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4689 4.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 96335 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5845 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.165269 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 198.412430 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5844 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5845 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5845 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.616424 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.570046 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.313075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4545 77.76% 77.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 48 0.82% 78.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 753 12.88% 91.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 215 3.68% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 127 2.17% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 88 1.51% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 42 0.72% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 17 0.29% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.09% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5845 # Writes before turning the bus around for reads -system.physmem.totQLat 6714977565 # Total ticks spent queuing -system.physmem.totMemAccLat 9582621315 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 764705000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43905.67 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 132565 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 154.319345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.621145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 210.186270 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82651 62.35% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32256 24.33% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6354 4.79% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2721 2.05% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1163 0.88% 94.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1002 0.76% 95.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 846 0.64% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 812 0.61% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4760 3.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132565 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.864488 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 211.288279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5866 99.86% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 7 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554307 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.512747 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.243213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4672 79.54% 79.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 38 0.65% 80.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 729 12.41% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 209 3.56% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 107 1.82% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 58 0.99% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.53% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 16 0.27% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.19% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5874 # Writes before turning the bus around for reads +system.physmem.totQLat 7261518854 # Total ticks spent queuing +system.physmem.totMemAccLat 11431968854 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1112120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32647.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62655.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 291.97 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 185.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 292.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 185.44 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51397.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 166.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 382.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 166.96 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.73 # Data bus utilization in percentage -system.physmem.busUtilRead 2.28 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.45 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.busUtil 4.29 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing -system.physmem.readRowHits 120882 # Number of row buffer hits during reads -system.physmem.writeRowHits 32837 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes -system.physmem.avgGap 133976.26 # Average gap between requests -system.physmem.pageHitRate 61.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 378438480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 206489250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 627572400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 315854640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15155251200 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6817959750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25690916520 # Total energy per rank (pJ) -system.physmem_0.averagePower 766.433942 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11238384768 # Time in different power states -system.physmem_0.memoryStateTime::REF 1119300000 # Time in different power states +system.physmem.readRowHits 157163 # Number of row buffer hits during reads +system.physmem.writeRowHits 29925 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.77 # Row buffer hit rate for writes +system.physmem.avgGap 116570.12 # Average gap between requests +system.physmem.pageHitRate 58.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 537077520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 293048250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 957496800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 315958320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 23206024395 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2012333250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 29756923815 # Total energy per rank (pJ) +system.physmem_0.averagePower 798.183082 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3201879547 # Time in different power states +system.physmem_0.memoryStateTime::REF 1244880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21162395232 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32834079203 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 349513920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 190707000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 564751200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313295040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13737724470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 8061404250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25406746680 # Total energy per rank (pJ) -system.physmem_1.averagePower 757.956338 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 13314860915 # Time in different power states -system.physmem_1.memoryStateTime::REF 1119300000 # Time in different power states +system.physmem_1.actEnergy 464871960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 253650375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 777051600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313949520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 21592790730 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3427453500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 29264752965 # Total energy per rank (pJ) +system.physmem_1.averagePower 784.981262 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 5568954615 # Time in different power states +system.physmem_1.memoryStateTime::REF 1244880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30467009135 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17055826 # Number of BP lookups -system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9258903 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7371283 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17068882 # Number of BP lookups +system.cpu.branchPred.condPredicted 11456187 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 597693 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9279962 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7373647 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.612920 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1853216 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101575 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 232758 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 195217 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 79.457728 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1854916 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101589 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 233217 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 195584 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37633 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22185 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -328,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,7 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,130 +421,130 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 67049513 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 74566667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5112037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87027076 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17055826 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9419716 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60300614 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1224115 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12656 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22418203 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68072 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66043378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.665685 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.303820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5541341 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87099155 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17068882 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9424147 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 65038748 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1222021 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 11659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30739 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22432357 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69340 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 71233545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.545306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.327706 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20904696 31.65% 31.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8151419 12.34% 44.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9105743 13.79% 57.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27881520 42.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 26059108 36.58% 36.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8166381 11.46% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9112889 12.79% 60.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27895167 39.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66043378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.254377 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.297952 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8568047 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 20331818 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31035970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5662045 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 445498 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3138719 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168392 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100377883 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2807284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 445498 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13201972 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6021135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 843957 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31848304 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13682512 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98401933 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 864722 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3910657 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 69359 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4461482 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5194138 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103316551 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453880702 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114363596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 71233545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.228908 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.168071 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8928507 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 25221623 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30949867 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5689167 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 444381 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3134053 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168503 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100299686 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2798262 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 444381 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13572247 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10675080 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 842433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31772787 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13926617 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98328841 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 859440 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4124148 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69439 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4596367 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5265270 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103255092 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453545884 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114277398 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 716 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9687182 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18952 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18977 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12759909 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24172969 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21779154 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1438398 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2287665 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97467378 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34812 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94518121 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 609879 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6819583 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18148637 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1026 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66043378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.431152 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.152558 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9625723 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18974 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19002 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12839389 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24155878 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21759886 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1433320 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2321800 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97398916 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34841 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94478155 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 593843 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6751150 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17960313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1055 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 71233545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.326316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.168839 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17971444 27.21% 27.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17366377 26.30% 53.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17018277 25.77% 79.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11635318 17.62% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2050574 3.10% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1388 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23112455 32.45% 32.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17441476 24.48% 56.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17040128 23.92% 80.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11602976 16.29% 97.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2035055 2.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1455 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66043378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 71233545 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6745698 22.64% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 37 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11091756 37.22% 59.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11960162 40.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6731709 22.63% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 38 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11081856 37.26% 59.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11930481 40.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49324075 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86626 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49303920 52.19% 52.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86563 0.09% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued @@ -563,89 +565,89 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 12 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23968009 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21139361 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23954982 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21132627 22.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94518121 # Type of FU issued -system.cpu.iq.rate 1.409676 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29797653 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315259 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 285486823 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104332871 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93229184 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 329 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 574 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124315586 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1381077 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94478155 # Type of FU issued +system.cpu.iq.rate 1.267029 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29744084 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314825 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 290527434 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104196109 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93201296 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 348 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 616 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124222040 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1368179 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1306707 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11900 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1223416 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1289616 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2048 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1204148 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 147221 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 186554 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 144864 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185613 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 445498 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 578203 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 566637 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97517928 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 444381 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 624509 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1115710 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97447803 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24172969 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21779154 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18892 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 562180 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11900 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250835 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 223196 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 474031 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93719339 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23701905 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 798782 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24155878 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21759886 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18921 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1617 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1111435 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 249911 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221890 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 471801 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93685311 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23691817 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 792844 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15738 # number of nop insts executed -system.cpu.iew.exec_refs 44631646 # number of memory reference insts executed -system.cpu.iew.exec_branches 14212084 # Number of branches executed -system.cpu.iew.exec_stores 20929741 # Number of stores executed -system.cpu.iew.exec_rate 1.397763 # Inst execution rate -system.cpu.iew.wb_sent 93338125 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93229268 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44994314 # num instructions producing a value -system.cpu.iew.wb_consumers 76693481 # num instructions consuming a value -system.cpu.iew.wb_rate 1.390454 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586677 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5957514 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 14046 # number of nop insts executed +system.cpu.iew.exec_refs 44616394 # number of memory reference insts executed +system.cpu.iew.exec_branches 14207133 # Number of branches executed +system.cpu.iew.exec_stores 20924577 # Number of stores executed +system.cpu.iew.exec_rate 1.256397 # Inst execution rate +system.cpu.iew.wb_sent 93308677 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93201392 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44951021 # num instructions producing a value +system.cpu.iew.wb_consumers 76633881 # num instructions consuming a value +system.cpu.iew.wb_rate 1.249907 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586569 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5894305 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 432296 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 65078464 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.393520 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.163869 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 431064 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 70277782 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.290424 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.118209 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31565690 48.50% 48.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16713735 25.68% 74.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4316875 6.63% 80.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4188712 6.44% 87.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1942227 2.98% 90.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1235606 1.90% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 754913 1.16% 93.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 587526 0.90% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3773180 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 36842990 52.42% 52.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16674938 23.73% 76.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4291723 6.11% 82.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4149088 5.90% 88.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1947878 2.77% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1240751 1.77% 92.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 737656 1.05% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580756 0.83% 94.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3812002 5.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 65078464 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 70277782 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -691,546 +693,552 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3773180 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 157925658 # The number of ROB reads -system.cpu.rob.rob_writes 194257744 # The number of ROB writes -system.cpu.timesIdled 27177 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1006135 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3812002 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 163022945 # The number of ROB reads +system.cpu.rob.rob_writes 194122181 # The number of ROB writes +system.cpu.timesIdled 54257 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3333122 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.945589 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.945589 # CPI: Total CPI of All Threads -system.cpu.ipc 1.057542 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.057542 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102008139 # number of integer regfile reads -system.cpu.int_regfile_writes 56630693 # number of integer regfile writes -system.cpu.fp_regfile_reads 48 # number of floating regfile reads -system.cpu.fp_regfile_writes 42 # number of floating regfile writes -system.cpu.cc_regfile_reads 345209533 # number of cc regfile reads -system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes -system.cpu.misc_regfile_reads 44112663 # number of misc regfile reads +system.cpu.cpi 1.051603 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051603 # CPI: Total CPI of All Threads +system.cpu.ipc 0.950930 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.950930 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101976703 # number of integer regfile reads +system.cpu.int_regfile_writes 56611271 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.fp_regfile_writes 48 # number of floating regfile writes +system.cpu.cc_regfile_reads 345090037 # number of cc regfile reads +system.cpu.cc_regfile_writes 38758670 # number of cc regfile writes +system.cpu.misc_regfile_reads 44101489 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 486293 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 486805 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 82.847407 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 150823500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.756058 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997570 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484862 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.874566 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40338135 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485374 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.107325 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 151605500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.874566 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18832689 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59994 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59994 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84467396 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84467396 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21414103 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21414103 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18832546 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18832546 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60212 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60212 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15310 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15310 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40239255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40239255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40299249 # number of overall hits -system.cpu.dcache.overall_hits::total 40299249 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 567937 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 567937 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1017212 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1017212 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68679 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68679 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1585149 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1585149 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1653828 # number of overall misses -system.cpu.dcache.overall_misses::total 1653828 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9485185000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9485185000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14264451930 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14264451930 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5633500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5633500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23749636930 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23749636930 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23749636930 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23749636930 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21974503 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21974503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40246649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40246649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40306861 # number of overall hits +system.cpu.dcache.overall_hits::total 40306861 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 566310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 566310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1017355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1017355 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68643 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68643 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 613 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 613 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1583665 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1583665 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1652308 # number of overall misses +system.cpu.dcache.overall_misses::total 1652308 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13581553500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13581553500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13903205430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13903205430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5738500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5738500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27484758930 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27484758930 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27484758930 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27484758930 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21980413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21980413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128673 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128673 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15924 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15924 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41824404 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41824404 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41953077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41953077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025845 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025845 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051245 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.533748 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.533748 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038809 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038809 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037900 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037900 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039421 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039421 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16701.121779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16701.121779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14023.086564 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14023.086564 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9115.695793 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9115.695793 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14982.589605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14982.589605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14360.403216 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2907482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks -system.cpu.dcache.writebacks::total 486293 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 267392 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868636 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 868636 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1136028 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1136028 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1136028 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1136028 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 300545 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 300545 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148576 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148576 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37700 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37700 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449121 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449121 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 486821 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 486821 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3693304500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3693304500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2308719470 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2308719470 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1888982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1888982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6002023970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6002023970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7891006470 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7891006470 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013677 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013677 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292991 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292991 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010738 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010738 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011604 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12288.690546 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12288.690546 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325000 # number of replacements -system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy +system.cpu.dcache.demand_accesses::cpu.data 41830314 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41830314 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41959169 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41959169 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051252 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051252 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532715 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532715 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037859 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037859 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039379 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039379 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23982.542247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23982.542247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13666.031454 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13666.031454 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9361.337684 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9361.337684 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17355.159664 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17355.159664 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16634.161990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16634.161990 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2820837 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 130956 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21.540342 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484862 # number of writebacks +system.cpu.dcache.writebacks::total 484862 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 267183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868792 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 868792 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 613 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 613 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1135975 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135975 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135975 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135975 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299127 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299127 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148563 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148563 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37696 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37696 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447690 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447690 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485386 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485386 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6671017500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6671017500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2276896471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2276896471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1910092000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1910092000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947913971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8947913971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10858005971 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10858005971 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010703 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010703 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011568 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011568 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22301.622722 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22301.622722 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15326.134172 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15326.134172 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50670.946520 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50670.946520 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19986.852445 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19986.852445 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22369.837554 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22369.837554 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 325915 # number of replacements +system.cpu.icache.tags.tagsinuse 510.404253 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22094458 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 326427 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.685755 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1157973500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.404253 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996883 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996883 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22083387 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22083387 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22083387 # number of overall hits -system.cpu.icache.overall_hits::total 22083387 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 334707 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 334707 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 334707 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 334707 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 334707 # number of overall misses -system.cpu.icache.overall_misses::total 334707 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3526570179 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3526570179 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3526570179 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3526570179 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3526570179 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3526570179 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22418094 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22418094 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22418094 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22418094 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22418094 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22418094 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014930 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014930 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014930 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014930 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014930 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014930 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10536.290484 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10536.290484 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10536.290484 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10536.290484 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 264177 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16495 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45190725 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45190725 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22094458 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22094458 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22094458 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22094458 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22094458 # number of overall hits +system.cpu.icache.overall_hits::total 22094458 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 337685 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 337685 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 337685 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 337685 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 337685 # number of overall misses +system.cpu.icache.overall_misses::total 337685 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5566889382 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5566889382 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5566889382 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5566889382 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5566889382 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5566889382 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22432143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22432143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22432143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22432143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22432143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22432143 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015054 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015054 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015054 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015054 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015054 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015054 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16485.450589 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16485.450589 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16485.450589 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16485.450589 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 546680 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 53 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25668 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325000 # number of writebacks -system.cpu.icache.writebacks::total 325000 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9178 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 9178 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 9178 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 9178 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 9178 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 9178 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325529 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 325529 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 325529 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 325529 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 325529 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 325529 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3259633220 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3259633220 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3259633220 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3259633220 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3259633220 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3259633220 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.298114 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 26.500000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 325915 # number of writebacks +system.cpu.icache.writebacks::total 325915 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 11245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 11245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 11245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 11245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 11245 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326440 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 326440 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 326440 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 326440 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 326440 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 326440 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5156036946 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5156036946 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5156036946 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5156036946 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5156036946 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5156036946 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014552 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014552 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014552 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15794.746189 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15794.746189 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 822007 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 825699 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3235 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 128177 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 144531 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.195986 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78661 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 125486 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15697.579441 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 682126 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141813 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.810039 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15883.544788 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 105.518503 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.969455 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006440 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.975895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 30 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16324 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2742 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12115 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 553 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001831 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996338 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25089114 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25089114 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 260314 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 260314 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 470737 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 470737 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 137093 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 137093 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 314576 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 314576 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300687 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 300687 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 314576 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 437780 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 752356 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 314576 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 437780 # number of overall hits -system.cpu.l2cache.overall_hits::total 752356 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 11519 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 11519 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10935 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10935 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 37506 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 37506 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10935 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 49025 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 59960 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10935 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 49025 # number of overall misses -system.cpu.l2cache.overall_misses::total 59960 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1190791000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1190791000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 838826500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 838826500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3069049000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3069049000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 838826500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4259840000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 5098666500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 838826500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4259840000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 5098666500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 260314 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 260314 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 470737 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 470737 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 148612 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 148612 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 325511 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 325511 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 338193 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 338193 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 325511 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 486805 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 812316 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 325511 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 486805 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 812316 # number of overall (read+write) accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 15632.148504 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 65.430937 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.954111 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003994 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958104 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 23 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16304 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2745 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12082 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 548 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 792 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001404 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 25510486 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25510486 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 254711 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 254711 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 476176 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 476176 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 137223 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 137223 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 289219 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 289219 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 256138 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 256138 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 289219 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 393361 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 682580 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 289219 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 393361 # number of overall hits +system.cpu.l2cache.overall_hits::total 682580 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 11378 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 11378 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37206 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 37206 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80635 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 80635 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 37206 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 92013 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 129219 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 37206 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 92013 # number of overall misses +system.cpu.l2cache.overall_misses::total 129219 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1158421000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1158421000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2926655500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2926655500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6384062000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6384062000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2926655500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7542483000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10469138500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2926655500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7542483000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10469138500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 254711 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 254711 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 476176 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 476176 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 12 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 12 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 148601 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 148601 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 326425 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 326425 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336773 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 336773 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 326425 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 485374 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 811799 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 326425 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 485374 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 811799 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077511 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.077511 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.033593 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.033593 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.110901 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.110901 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.033593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.100708 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.073814 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.033593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.100708 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.073814 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103376.247938 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103376.247938 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76710.242341 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76710.242341 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81828.214152 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81828.214152 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76710.242341 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85034.464643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76710.242341 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85034.464643 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076567 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.076567 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239434 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239434 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113980 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.189571 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.159176 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113980 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.189571 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.159176 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101812.357181 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101812.357181 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78660.847713 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78660.847713 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79172.344515 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79172.344515 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78660.847713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81971.927880 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81018.569251 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78660.847713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81971.927880 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81018.569251 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 424 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 97140 # number of writebacks -system.cpu.l2cache.writebacks::total 97140 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3182 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3182 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 412 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 97262 # number of writebacks +system.cpu.l2cache.writebacks::total 97262 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2980 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 2980 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 28 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 28 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 100 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 100 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 115 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 115 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3282 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3310 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3095 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3123 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3282 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3310 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112662 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 112662 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8337 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 8337 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10907 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10907 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 37406 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 37406 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10907 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 45743 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 56650 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10907 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 45743 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112662 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 169312 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10325101509 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10325101509 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 232500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 232500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 662233000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 662233000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 771578500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 771578500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2838075000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2838075000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 771578500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3500308000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4271886500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 771578500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3500308000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10325101509 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14596988009 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 3095 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3123 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 115252 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 115252 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 12 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8398 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8398 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37178 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37178 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80520 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80520 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 37178 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 88918 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 126096 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 37178 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 88918 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115252 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 241348 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 9954483724 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 9954483724 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 680267500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 680267500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2701591500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2701591500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5893524000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5893524000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2701591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6573791500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9275383000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2701591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6573791500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 9954483724 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19229866724 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033507 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.110605 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.110605 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069739 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113894 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239093 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239093 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.155329 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.208431 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91646.708819 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14531.250000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14531.250000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79433.009476 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79433.009476 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70741.587971 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70741.587971 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75872.186280 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 79349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 142185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 325529 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 338193 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976039 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1459935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2435974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41632640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62278272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103910912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318692 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6218112 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1131024 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.140178 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.373630 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297300 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 86371.461875 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15458.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15458.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81003.512741 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81003.512741 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72666.402173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72666.402173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73193.293592 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73193.293592 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73558.106522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79676.925949 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1622603 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810817 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79904 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18775 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18774 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 663212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 351973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 556066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 144126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 326440 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336773 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 978779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455634 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2434413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41749696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62095104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103844800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 269627 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6225728 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1081438 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091286 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288019 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 983264 86.94% 86.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 136975 12.11% 99.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 10785 0.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 982719 90.87% 90.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98718 9.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1131024 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1623114500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488687208 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 144751 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution -system.membus.trans_dist::CleanEvict 28117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 8337 # Transaction distribution -system.membus.trans_dist::ReadExResp 8337 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 144752 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431450 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 431450 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16014592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16014592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 1081438 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1622078500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 489794228 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 728148836 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 348072 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205263 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214175 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97262 # Transaction distribution +system.membus.trans_dist::CleanEvict 28224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 12 # Transaction distribution +system.membus.trans_dist::ReadExReq 8398 # Transaction distribution +system.membus.trans_dist::ReadExResp 8398 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570645 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20469440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20469440 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 278362 # Request fanout histogram +system.membus.snoop_fanout::samples 222586 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 278362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222586 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 278362 # Request fanout histogram -system.membus.reqLayer0.occupancy 747889943 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222586 # Request fanout histogram +system.membus.reqLayer0.occupancy 837454269 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 799798093 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1175863136 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |