diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/long/se/50.vortex | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/long/se/50.vortex')
3 files changed, 2208 insertions, 2185 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index c7e2525ee..4f4f69eed 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043769 # Number of seconds simulated -sim_ticks 43769191000 # Number of ticks simulated -final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043690 # Number of seconds simulated +sim_ticks 43690025000 # Number of ticks simulated +final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69144 # Simulator instruction rate (inst/s) -host_op_rate 69144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34257993 # Simulator tick rate (ticks/s) -host_mem_usage 232832 # Number of bytes of host memory used -host_seconds 1277.63 # Real time elapsed on the host +host_inst_rate 111109 # Simulator instruction rate (inst/s) +host_op_rate 111109 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54950396 # Simulator tick rate (ticks/s) +host_mem_usage 264576 # Number of bytes of host memory used +host_seconds 795.08 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory @@ -23,81 +23,83 @@ system.physmem.num_reads::cpu.data 158412 # Nu system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10386118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 231632520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242018638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10386118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10386118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166688208 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166688208 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166688208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165515 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 113997 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 165515 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 113997 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 10592960 # Total number of bytes read from memory -system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10015 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10510 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10480 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10593 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7259 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6998 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7175 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6769 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6938 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7284 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7283 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43769170000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165515 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 113997 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 72862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 10404938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 232052236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 242457174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10404938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10404938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166990245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166990245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166990245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10404938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 232052236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 409447420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165515 # Number of read requests accepted +system.physmem.writeReqs 113997 # Number of write requests accepted +system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10592832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10379 # Per bank write bursts +system.physmem.perBankRdBursts::1 10437 # Per bank write bursts +system.physmem.perBankRdBursts::2 10256 # Per bank write bursts +system.physmem.perBankRdBursts::3 10015 # Per bank write bursts +system.physmem.perBankRdBursts::4 10350 # Per bank write bursts +system.physmem.perBankRdBursts::5 10362 # Per bank write bursts +system.physmem.perBankRdBursts::6 9796 # Per bank write bursts +system.physmem.perBankRdBursts::7 10273 # Per bank write bursts +system.physmem.perBankRdBursts::8 10509 # Per bank write bursts +system.physmem.perBankRdBursts::9 10590 # Per bank write bursts +system.physmem.perBankRdBursts::10 10479 # Per bank write bursts +system.physmem.perBankRdBursts::11 10188 # Per bank write bursts +system.physmem.perBankRdBursts::12 10237 # Per bank write bursts +system.physmem.perBankRdBursts::13 10581 # Per bank write bursts +system.physmem.perBankRdBursts::14 10468 # Per bank write bursts +system.physmem.perBankRdBursts::15 10593 # Per bank write bursts +system.physmem.perBankWrBursts::0 7081 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts +system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::4 7125 # Per bank write bursts +system.physmem.perBankWrBursts::5 7173 # Per bank write bursts +system.physmem.perBankWrBursts::6 6769 # Per bank write bursts +system.physmem.perBankWrBursts::7 7091 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::9 6938 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6989 # Per bank write bursts +system.physmem.perBankWrBursts::12 6964 # Per bank write bursts +system.physmem.perBankWrBursts::13 7284 # Per bank write bursts +system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 43690004000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 165515 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 113997 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 73680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,188 +127,195 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 366.351698 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.645495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 749.158032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 19754 40.46% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7696 15.76% 56.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4247 8.70% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2897 5.93% 70.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2142 4.39% 75.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1740 3.56% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1303 2.67% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1111 2.28% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 826 1.69% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 678 1.39% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 468 0.96% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 525 1.08% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 411 0.84% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 341 0.70% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 262 0.54% 90.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 362 0.74% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 210 0.43% 92.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 226 0.46% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 155 0.32% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 229 0.47% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 390 0.80% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 303 0.62% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 582 1.19% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 207 0.42% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 152 0.31% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 46 0.09% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 145 0.30% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 73 0.15% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 52 0.11% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 28 0.06% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 72 0.15% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 42 0.09% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 42 0.09% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 23 0.05% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 48 0.10% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 25 0.05% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 11 0.02% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 23 0.05% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 7 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 13 0.03% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 21 0.04% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 13 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 14 0.03% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 8 0.02% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 9 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 5 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 8 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 5 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 3 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 7 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 6 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 3 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 6 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 12 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 3 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 6 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 164 0.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48826 # Bytes accessed per row activation -system.physmem.totQLat 6287289000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8773086500 # Sum of mem lat for all requests -system.physmem.totBusLat 827575000 # Total cycles spent in databus access -system.physmem.totBankLat 1658222500 # Total cycles spent in bank access -system.physmem.avgQLat 37986.22 # Average queueing delay per request -system.physmem.avgBankLat 10018.56 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53004.78 # Average memory access latency -system.physmem.avgRdBW 242.02 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 166.69 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 242.02 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 166.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.19 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 10.49 # Average write queue length over time -system.physmem.readRowHits 153779 # Number of row buffer hits during reads -system.physmem.writeRowHits 76898 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.46 # Row buffer hit rate for writes -system.physmem.avgGap 156591.38 # Average gap between requests -system.membus.throughput 408706846 # Throughput (bytes/s) +system.physmem.bytesPerActivate::samples 51391 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.059076 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.605304 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 670.587406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 21918 42.65% 42.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7689 14.96% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4202 8.18% 65.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3191 6.21% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2222 4.32% 76.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1690 3.29% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1284 2.50% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1159 2.26% 84.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 851 1.66% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 652 1.27% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 530 1.03% 88.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 483 0.94% 89.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 404 0.79% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 335 0.65% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 260 0.51% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 388 0.75% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 222 0.43% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 237 0.46% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 182 0.35% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 255 0.50% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 215 0.42% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 327 0.64% 94.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 148 0.29% 95.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 683 1.33% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 243 0.47% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 177 0.34% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 59 0.11% 97.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 192 0.37% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 83 0.16% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 80 0.16% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 48 0.09% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 87 0.17% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 58 0.11% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 48 0.09% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 40 0.08% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 14 0.03% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 34 0.07% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 26 0.05% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 13 0.03% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 18 0.04% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 12 0.02% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 26 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 7 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 17 0.03% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 6 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 10 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 11 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 13 0.03% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 10 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 6 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 3 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 20 0.04% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 11 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 15 0.03% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 13 0.03% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 8 0.02% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 4 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 6 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 24 0.05% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 73 0.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 51391 # Bytes accessed per row activation +system.physmem.totQLat 6031819750 # Total ticks spent queuing +system.physmem.totMemAccLat 8481513500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 827565000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1622128750 # Total ticks spent accessing banks +system.physmem.avgQLat 36443.18 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9800.61 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 51243.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 242.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 166.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 242.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 166.99 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.20 # Data bus utilization in percentage +system.physmem.busUtilRead 1.89 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing +system.physmem.readRowHits 151507 # Number of row buffer hits during reads +system.physmem.writeRowHits 76598 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.19 # Row buffer hit rate for writes +system.physmem.avgGap 156308.15 # Average gap between requests +system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 10.59 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 409447420 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 34625 # Transaction distribution system.membus.trans_dist::ReadResp 34625 # Transaction distribution system.membus.trans_dist::Writeback 113997 # Transaction distribution @@ -318,39 +327,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1218630500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1522799000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1521664000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) -system.cpu.branchPred.lookups 18742730 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318368 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18742723 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15507340 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4664027 # Number of BTB hits +system.cpu.branchPred.BTBLookups 15507309 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4664026 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.076254 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 30.076308 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277790 # DTB read hits +system.cpu.dtb.read_hits 20277713 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367938 # DTB read accesses -system.cpu.dtb.write_hits 14728966 # DTB write hits +system.cpu.dtb.read_accesses 20367861 # DTB read accesses +system.cpu.dtb.write_hits 14728970 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736218 # DTB write accesses -system.cpu.dtb.data_hits 35006756 # DTB hits +system.cpu.dtb.write_accesses 14736222 # DTB write accesses +system.cpu.dtb.data_hits 35006683 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35104156 # DTB accesses -system.cpu.itb.fetch_hits 12367759 # ITB hits +system.cpu.dtb.data_accesses 35104083 # DTB accesses +system.cpu.itb.fetch_hits 12367758 # ITB hits system.cpu.itb.fetch_misses 11021 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378780 # ITB accesses +system.cpu.itb.fetch_accesses 12378779 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -364,34 +373,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87538383 # number of cpu cycles simulated +system.cpu.numCycles 87380051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8074238 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10668492 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74161920 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8074237 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10668486 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74161830 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126481170 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 126481080 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14174454 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 14174544 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 35060070 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed. +system.cpu.execution_unit.executions 44777932 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77194023 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77196543 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 231301 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17962893 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69575490 # Number of cycles cpu stages are processed. -system.cpu.activity 79.479981 # Percentage of cycles cpu is active +system.cpu.timesIdled 232942 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17804423 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69575628 # Number of cycles cpu stages are processed. +system.cpu.activity 79.624156 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -403,157 +412,157 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.990918 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.989126 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.990918 # CPI: Total CPI of All Threads -system.cpu.ipc 1.009165 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.989126 # CPI: Total CPI of All Threads +system.cpu.ipc 1.010994 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.009165 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34882792 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52655591 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.151432 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45083196 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42455187 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.498939 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44507774 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43030609 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.156276 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65417325 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22121058 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.270124 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41496378 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46042005 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.596362 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.010994 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34724442 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52655609 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.260447 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44924893 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42455158 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.586786 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44349560 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43030491 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.245212 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65259184 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120867 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.315695 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41338146 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46041905 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.691552 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 84371 # number of replacements -system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1906.431852 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250505 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760360 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12250515 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250515 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250515 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250515 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250515 # number of overall hits -system.cpu.icache.overall_hits::total 12250515 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117235 # number of overall misses -system.cpu.icache.overall_misses::total 117235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2053420481 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2053420481 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2053420481 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2053420481 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2053420481 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2053420481 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367750 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367750 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367750 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367750 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009479 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009479 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009479 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009479 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009479 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009479 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17515.421854 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17515.421854 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17515.421854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17515.421854 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1906.431852 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930875 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12250505 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250505 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250505 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250505 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250505 # number of overall hits +system.cpu.icache.overall_hits::total 12250505 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117242 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117242 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117242 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117242 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117242 # number of overall misses +system.cpu.icache.overall_misses::total 117242 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2020332731 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2020332731 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2020332731 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2020332731 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2020332731 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2020332731 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12367747 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367747 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367747 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367747 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367747 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367747 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009480 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009480 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009480 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17232.158535 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17232.158535 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17232.158535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17232.158535 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 376 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.812500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.117647 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30818 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30818 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30818 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30818 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30818 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30818 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30825 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30825 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30825 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30825 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30825 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30825 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1462353516 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1462353516 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1462353516 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1462353516 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1462353516 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1462353516 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1432321765 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1432321765 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1432321765 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1432321765 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1432321765 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1432321765 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16922.058345 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16922.058345 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16574.537012 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16574.537012 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 671326642 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution +system.cpu.toL2Bus.throughput 672540151 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 146994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 146994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168351 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577043 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 749877 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29383296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29383296 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 397908000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 131178984 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 130875735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 326782984 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 325637219 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.l2cache.tags.replacements 131591 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30890.802594 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 151432 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.925335 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27124.475533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.827773 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061262 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.054026 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.943061 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27098.006137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.747165 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1785.049292 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.826966 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061272 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.054475 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.942712 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168352 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168352 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33055 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 112369 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168351 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168351 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 79314 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 45935 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 125249 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 45934 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 125248 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 79314 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 45935 # number of overall hits -system.cpu.l2cache.overall_hits::total 125249 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 45934 # number of overall hits +system.cpu.l2cache.overall_hits::total 125248 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 7103 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 27522 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 34625 # number of ReadReq misses @@ -565,52 +574,52 @@ system.cpu.l2cache.demand_misses::total 165515 # nu system.cpu.l2cache.overall_misses::cpu.inst 7103 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses system.cpu.l2cache.overall_misses::total 165515 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 580141750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2014348750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2594490500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13747919500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13747919500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 580141750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15762268250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16342410000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 580141750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15762268250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16342410000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 550125750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2043322000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2593447750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13452980750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13452980750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 550125750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15496302750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16046428500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 550125750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15496302750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16046428500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 146995 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168352 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168352 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146994 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168351 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168351 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 86417 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290764 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204346 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290763 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 86417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290764 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204346 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 290763 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082194 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454331 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235554 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775215 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.569244 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81675.594819 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73190.493060 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74931.133574 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105034.146994 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105034.146994 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98736.730810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81675.594819 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99501.731245 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98736.730810 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775215 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.569244 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77449.774743 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74243.223603 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74901.018051 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.814042 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.814042 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 96948.485032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 96948.485032 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -632,73 +641,73 @@ system.cpu.l2cache.demand_mshr_misses::total 165515 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 490395250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1665695250 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1695556500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156502250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11851363750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11851363750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 460945750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13546920250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14007866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 460945750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13546920250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14007866000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454331 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235554 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569244 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69040.581444 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60522.318509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62269.761733 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92789.139736 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92789.139736 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69040.581444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87183.204240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569244 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64894.516402 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61607.314149 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62281.653430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90544.455268 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90544.455268 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200251 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574569 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574569 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754840 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754840 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754840 # number of overall hits -system.cpu.dcache.overall_hits::total 33754840 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038808 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038808 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135175 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135175 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135175 # number of overall misses -system.cpu.dcache.overall_misses::total 1135175 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010614984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5010614984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 87491278500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 87491278500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92501893484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92501893484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92501893484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92501893484 # number of overall miss cycles +system.cpu.dcache.tags.replacements 200250 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.382661 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33754883 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204346 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.184946 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 297515000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.382661 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180292 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180292 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574591 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574591 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754883 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754883 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754883 # number of overall hits +system.cpu.dcache.overall_hits::total 33754883 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96346 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96346 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038786 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038786 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135132 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135132 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135132 # number of overall misses +system.cpu.dcache.overall_misses::total 1135132 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5098666734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765880 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85921765880 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91020432614 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91020432614 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91020432614 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91020432614 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -707,56 +716,56 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071086 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51995.133023 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51995.133023 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84222.761569 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84222.761569 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81486.901565 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81486.901565 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5878259 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 106 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116796 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.377950 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.377950 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634839 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634839 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80184.888290 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80184.888290 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5745787 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.329284 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 106 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.220352 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks -system.cpu.dcache.writebacks::total 168352 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35600 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35600 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895228 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895228 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930828 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930828 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930828 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930828 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks +system.cpu.dcache.writebacks::total 168351 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35580 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35580 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895206 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895206 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930786 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930786 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930786 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930786 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2409027516 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2409027516 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14018315000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14018315000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16427342516 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16427342516 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16427342516 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16427342516 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2437943016 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2437943016 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723509265 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723509265 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161452281 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16161452281 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161452281 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16161452281 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -765,14 +774,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39643.680221 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39643.680221 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97634.176069 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97634.176069 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.925373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.925373 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index f889e2dcc..5daeaeb73 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024977 # Number of seconds simulated -sim_ticks 24977022500 # Number of ticks simulated -final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024874 # Number of seconds simulated +sim_ticks 24873813500 # Number of ticks simulated +final_tick 24873813500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179872 # Simulator instruction rate (inst/s) -host_op_rate 179872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56446381 # Simulator tick rate (ticks/s) -host_mem_usage 238148 # Number of bytes of host memory used -host_seconds 442.49 # Real time elapsed on the host +host_inst_rate 165069 # Simulator instruction rate (inst/s) +host_op_rate 165069 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51586823 # Simulator tick rate (ticks/s) +host_mem_usage 265596 # Number of bytes of host memory used +host_seconds 482.17 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 489600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10153536 # Number of bytes read from this memory -system.physmem.bytes_read::total 10643520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 10643136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7650 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158649 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166305 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19617390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 406515068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 426132458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19617390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19617390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 292149475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 292149475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 292149475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166305 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 114016 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 166305 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 114016 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 10643520 # Total number of bytes read from memory -system.physmem.bytesWritten 7297024 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10060 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9844 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10226 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10625 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6967 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24976988500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166305 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114016 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 72274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.num_reads::total 166299 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114017 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114017 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19683351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 408201822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 427885173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19683351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19683351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 293364264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 293364264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 293364264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19683351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 408201822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 721249438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166299 # Number of read requests accepted +system.physmem.writeReqs 114017 # Number of write requests accepted +system.physmem.readBursts 166299 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114017 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10643008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7296896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10643136 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10432 # Per bank write bursts +system.physmem.perBankRdBursts::1 10453 # Per bank write bursts +system.physmem.perBankRdBursts::2 10310 # Per bank write bursts +system.physmem.perBankRdBursts::3 10056 # Per bank write bursts +system.physmem.perBankRdBursts::4 10431 # Per bank write bursts +system.physmem.perBankRdBursts::5 10400 # Per bank write bursts +system.physmem.perBankRdBursts::6 9846 # Per bank write bursts +system.physmem.perBankRdBursts::7 10320 # Per bank write bursts +system.physmem.perBankRdBursts::8 10615 # Per bank write bursts +system.physmem.perBankRdBursts::9 10642 # Per bank write bursts +system.physmem.perBankRdBursts::10 10549 # Per bank write bursts +system.physmem.perBankRdBursts::11 10234 # Per bank write bursts +system.physmem.perBankRdBursts::12 10280 # Per bank write bursts +system.physmem.perBankRdBursts::13 10614 # Per bank write bursts +system.physmem.perBankRdBursts::14 10489 # Per bank write bursts +system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankWrBursts::0 7083 # Per bank write bursts +system.physmem.perBankWrBursts::1 7257 # Per bank write bursts +system.physmem.perBankWrBursts::2 7256 # Per bank write bursts +system.physmem.perBankWrBursts::3 6997 # Per bank write bursts +system.physmem.perBankWrBursts::4 7126 # Per bank write bursts +system.physmem.perBankWrBursts::5 7177 # Per bank write bursts +system.physmem.perBankWrBursts::6 6772 # Per bank write bursts +system.physmem.perBankWrBursts::7 7093 # Per bank write bursts +system.physmem.perBankWrBursts::8 7227 # Per bank write bursts +system.physmem.perBankWrBursts::9 6941 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::13 7287 # Per bank write bursts +system.physmem.perBankWrBursts::14 7286 # Per bank write bursts +system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24873779500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 166299 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 114017 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,230 +127,233 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49952 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.130045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.640646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 741.801736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 20814 41.67% 41.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7820 15.66% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4185 8.38% 65.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3013 6.03% 71.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2148 4.30% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1700 3.40% 79.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1301 2.60% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1098 2.20% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 776 1.55% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 657 1.32% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 496 0.99% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 568 1.14% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 406 0.81% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 302 0.60% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 268 0.54% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 357 0.71% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 241 0.48% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 170 0.34% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 145 0.29% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 323 0.65% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 351 0.70% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 146 0.29% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 301 0.60% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 689 1.38% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 236 0.47% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 76 0.15% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 36 0.07% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 184 0.37% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 89 0.18% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 34 0.07% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 40 0.08% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 93 0.19% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 64 0.13% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 19 0.04% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 44 0.09% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 19 0.04% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 19 0.04% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 36 0.07% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 21 0.04% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 12 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 20 0.04% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 10 0.02% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 10 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 17 0.03% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 15 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 9 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 8 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 9 0.02% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 10 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 6 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 5 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 11 0.02% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 7 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 169 0.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49952 # Bytes accessed per row activation -system.physmem.totQLat 6557959000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8953517750 # Sum of mem lat for all requests -system.physmem.totBusLat 831510000 # Total cycles spent in databus access -system.physmem.totBankLat 1564048750 # Total cycles spent in bank access -system.physmem.avgQLat 39434.04 # Average queueing delay per request -system.physmem.avgBankLat 9404.87 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53838.91 # Average memory access latency -system.physmem.avgRdBW 426.13 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 292.15 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 426.13 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 292.15 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.61 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.36 # Average read queue length over time -system.physmem.avgWrQLen 9.86 # Average write queue length over time -system.physmem.readRowHits 154145 # Number of row buffer hits during reads -system.physmem.writeRowHits 76216 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.85 # Row buffer hit rate for writes -system.physmem.avgGap 89101.38 # Average gap between requests -system.membus.throughput 718281933 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35508 # Transaction distribution -system.membus.trans_dist::ReadResp 35508 # Transaction distribution -system.membus.trans_dist::Writeback 114016 # Transaction distribution -system.membus.trans_dist::ReadExReq 130797 # Transaction distribution -system.membus.trans_dist::ReadExResp 130797 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446626 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446626 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17940544 # Total data (bytes) +system.physmem.bytesPerActivate::samples 52112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.243169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.634788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 670.449971 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 22509 43.19% 43.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7813 14.99% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4251 8.16% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3108 5.96% 72.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2227 4.27% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1678 3.22% 79.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1376 2.64% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1167 2.24% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 816 1.57% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 658 1.26% 87.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 508 0.97% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 506 0.97% 89.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 390 0.75% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 297 0.57% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 306 0.59% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 440 0.84% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 200 0.38% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 185 0.36% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 164 0.31% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 351 0.67% 93.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 222 0.43% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 266 0.51% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 128 0.25% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 805 1.54% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 220 0.42% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 67 0.13% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 43 0.08% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 225 0.43% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 103 0.20% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 52 0.10% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 34 0.07% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 84 0.16% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 57 0.11% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 36 0.07% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 55 0.11% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 39 0.07% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 21 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 12 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 17 0.03% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 18 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 24 0.05% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 13 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 9 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 11 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 6 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 11 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 9 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 13 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 6 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 10 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 5 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 6 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 8 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 7 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 8 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 15 0.03% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 82 0.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52112 # Bytes accessed per row activation +system.physmem.totQLat 6321612000 # Total ticks spent queuing +system.physmem.totMemAccLat 8667027000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831485000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1513930000 # Total ticks spent accessing banks +system.physmem.avgQLat 38013.99 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9103.77 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 52117.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 427.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 293.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 427.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 293.36 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 5.63 # Data bus utilization in percentage +system.physmem.busUtilRead 3.34 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.29 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.35 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.68 # Average write queue length when enqueuing +system.physmem.readRowHits 152202 # Number of row buffer hits during reads +system.physmem.writeRowHits 75997 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.65 # Row buffer hit rate for writes +system.physmem.avgGap 88734.78 # Average gap between requests +system.physmem.pageHitRate 81.41 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 721249438 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35493 # Transaction distribution +system.membus.trans_dist::ReadResp 35493 # Transaction distribution +system.membus.trans_dist::Writeback 114017 # Transaction distribution +system.membus.trans_dist::ReadExReq 130806 # Transaction distribution +system.membus.trans_dist::ReadExResp 130806 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446615 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17940224 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940224 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1242127000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1541382250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1539178500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) -system.cpu.branchPred.lookups 16531947 # Number of BP lookups -system.cpu.branchPred.condPredicted 10672978 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 414050 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11481292 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7335496 # Number of BTB hits +system.cpu.branchPred.lookups 16532535 # Number of BP lookups +system.cpu.branchPred.condPredicted 10677865 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 412540 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11187771 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7331268 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.890858 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1991572 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 40927 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.529300 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1986493 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41581 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22403443 # DTB read hits -system.cpu.dtb.read_misses 219972 # DTB read misses -system.cpu.dtb.read_acv 45 # DTB read access violations -system.cpu.dtb.read_accesses 22623415 # DTB read accesses -system.cpu.dtb.write_hits 15699616 # DTB write hits -system.cpu.dtb.write_misses 41064 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15740680 # DTB write accesses -system.cpu.dtb.data_hits 38103059 # DTB hits -system.cpu.dtb.data_misses 261036 # DTB misses -system.cpu.dtb.data_acv 46 # DTB access violations -system.cpu.dtb.data_accesses 38364095 # DTB accesses -system.cpu.itb.fetch_hits 13905618 # ITB hits -system.cpu.itb.fetch_misses 35229 # ITB misses +system.cpu.dtb.read_hits 22399036 # DTB read hits +system.cpu.dtb.read_misses 220951 # DTB read misses +system.cpu.dtb.read_acv 40 # DTB read access violations +system.cpu.dtb.read_accesses 22619987 # DTB read accesses +system.cpu.dtb.write_hits 15703469 # DTB write hits +system.cpu.dtb.write_misses 40937 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 15744406 # DTB write accesses +system.cpu.dtb.data_hits 38102505 # DTB hits +system.cpu.dtb.data_misses 261888 # DTB misses +system.cpu.dtb.data_acv 45 # DTB access violations +system.cpu.dtb.data_accesses 38364393 # DTB accesses +system.cpu.itb.fetch_hits 13899355 # ITB hits +system.cpu.itb.fetch_misses 34906 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13940847 # ITB accesses +system.cpu.itb.fetch_accesses 13934261 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -362,98 +367,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49954048 # number of cpu cycles simulated +system.cpu.numCycles 49747630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15782352 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105305571 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16531947 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9327068 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19535430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1996105 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7525610 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314470 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13905618 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 207845 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44615196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.360307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15785028 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105317585 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16532535 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9317761 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19533050 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1994568 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7608263 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7898 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 310217 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13899355 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 208294 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44693564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.356437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120216 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25079766 56.21% 56.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1526701 3.42% 59.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1368492 3.07% 62.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1511592 3.39% 66.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4137930 9.27% 75.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1849422 4.15% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 676249 1.52% 81.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069566 2.40% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7395478 16.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25160514 56.30% 56.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1525973 3.41% 59.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1366086 3.06% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510374 3.38% 66.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4139884 9.26% 75.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1847459 4.13% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 671184 1.50% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1072337 2.40% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7399753 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44615196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.330943 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.108049 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16870832 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7056928 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18547803 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 794977 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1344656 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3743758 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107019 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103586885 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 307942 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1344656 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17339272 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4755583 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85639 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18836599 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2253447 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102335224 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2492 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122982558 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319719 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44693564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.332328 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.117037 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16872770 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7137515 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18556178 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 782832 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1344269 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3743968 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106931 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103592319 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 303311 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1344269 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17342531 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4850765 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84983 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18829662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2241354 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102344042 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 512 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2574 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2122740 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61629886 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123330813 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123015128 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 315684 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5530 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4823408 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23239875 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16264209 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1185310 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 465013 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90722071 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5344 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88415019 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 95015 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10694229 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4666218 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 761 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44615196 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981724 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109954 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9083005 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5524 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5522 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4827061 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23228738 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16269123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1186061 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 452179 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90719899 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5267 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88414674 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10680066 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4660295 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 684 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44693564 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.978242 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.110252 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16409410 36.78% 36.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6866152 15.39% 52.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5567351 12.48% 64.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4772569 10.70% 75.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4725060 10.59% 85.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2625070 5.88% 91.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1917083 4.30% 96.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1291638 2.90% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 440863 0.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16504766 36.93% 36.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6842289 15.31% 52.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5576642 12.48% 64.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4760179 10.65% 75.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4735432 10.60% 85.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2623142 5.87% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1921443 4.30% 96.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1284900 2.87% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 444771 1.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44615196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44693564 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126842 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126888 6.81% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available @@ -482,19 +487,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 784071 42.12% 48.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 950643 51.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 786366 42.17% 48.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 951332 51.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49344695 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43834 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49347874 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43826 0.05% 55.86% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121349 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121152 0.14% 56.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38963 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 120827 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120926 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38966 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -516,84 +521,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22855764 25.85% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15889119 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22848043 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15894065 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88415019 # Type of FU issued -system.cpu.iq.rate 1.769927 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1861556 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021055 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222796879 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101023469 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86533748 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 604926 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 415943 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294379 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89974024 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 302551 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1471412 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88414674 # Type of FU issued +system.cpu.iq.rate 1.777264 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1864586 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021089 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222880329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101013312 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86537625 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 602080 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 409925 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294164 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89978136 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301124 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1470512 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2963237 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4955 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18224 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1650832 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2952100 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4699 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18249 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1655746 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2867 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 96301 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2987 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 95590 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1344656 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3651094 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 72855 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100203758 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 216158 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23239875 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16264209 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5344 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49772 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6561 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18224 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 192723 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161669 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 354392 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87578159 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22626447 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 836860 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1344269 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3728175 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74875 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100203568 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217116 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23228738 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16269123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5267 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49826 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6538 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18249 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 191969 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160202 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 352171 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87579420 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22623199 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 835254 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9476343 # number of nop insts executed -system.cpu.iew.exec_refs 38367436 # number of memory reference insts executed -system.cpu.iew.exec_branches 15087087 # Number of branches executed -system.cpu.iew.exec_stores 15740989 # Number of stores executed -system.cpu.iew.exec_rate 1.753174 # Inst execution rate -system.cpu.iew.wb_sent 87216851 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86828127 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33345535 # num instructions producing a value -system.cpu.iew.wb_consumers 43468305 # num instructions consuming a value +system.cpu.iew.exec_nop 9478402 # number of nop insts executed +system.cpu.iew.exec_refs 38367932 # number of memory reference insts executed +system.cpu.iew.exec_branches 15082234 # Number of branches executed +system.cpu.iew.exec_stores 15744733 # Number of stores executed +system.cpu.iew.exec_rate 1.760474 # Inst execution rate +system.cpu.iew.wb_sent 87221630 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86831789 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33348400 # num instructions producing a value +system.cpu.iew.wb_consumers 43473071 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.738160 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767123 # average fanout of values written-back +system.cpu.iew.wb_rate 1.745446 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767105 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8869178 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8866636 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 309326 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43270540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.041589 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791914 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 307777 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43349295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.037880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791190 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20425554 47.20% 47.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7044262 16.28% 63.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3374707 7.80% 71.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2054728 4.75% 76.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2036437 4.71% 80.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1166697 2.70% 83.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1108378 2.56% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 724905 1.68% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5334872 12.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20524240 47.35% 47.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7032147 16.22% 63.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3350548 7.73% 71.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2057076 4.75% 76.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2049777 4.73% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1169910 2.70% 83.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1109421 2.56% 86.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718391 1.66% 87.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5337785 12.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43270540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43349295 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -604,212 +609,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5334872 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5337785 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133828176 # The number of ROB reads -system.cpu.rob.rob_writes 195767077 # The number of ROB writes -system.cpu.timesIdled 83938 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5338852 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133901476 # The number of ROB reads +system.cpu.rob.rob_writes 195761663 # The number of ROB writes +system.cpu.timesIdled 83653 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5054066 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.627628 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.627628 # CPI: Total CPI of All Threads -system.cpu.ipc 1.593299 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.593299 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115893073 # number of integer regfile reads -system.cpu.int_regfile_writes 57500612 # number of integer regfile writes -system.cpu.fp_regfile_reads 249654 # number of floating regfile reads -system.cpu.fp_regfile_writes 240130 # number of floating regfile writes -system.cpu.misc_regfile_reads 38049 # number of misc regfile reads +system.cpu.cpi 0.625035 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625035 # CPI: Total CPI of All Threads +system.cpu.ipc 1.599911 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.599911 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115904116 # number of integer regfile reads +system.cpu.int_regfile_writes 57506232 # number of integer regfile writes +system.cpu.fp_regfile_reads 249599 # number of floating regfile reads +system.cpu.fp_regfile_writes 239957 # number of floating regfile writes +system.cpu.misc_regfile_reads 38110 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1198592827 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186551 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580061 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 766612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5969600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29937280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes) +system.cpu.toL2Bus.throughput 1204474416 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168935 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143420 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187275 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 767312 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5992768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29959872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29959872 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402997000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141571734 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141831227 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 327076000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 326236500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91227 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13799737 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13799737 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13799737 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13799737 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13799737 # number of overall hits -system.cpu.icache.overall_hits::total 13799737 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105880 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105880 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105880 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105880 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105880 # number of overall misses -system.cpu.icache.overall_misses::total 105880 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2067336982 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2067336982 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2067336982 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2067336982 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2067336982 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2067336982 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13905617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13905617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13905617 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13905617 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13905617 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13905617 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007614 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007614 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007614 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007614 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007614 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007614 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19525.283170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19525.283170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19525.283170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19525.283170 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.icache.tags.replacements 91589 # number of replacements +system.cpu.icache.tags.tagsinuse 1926.117780 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13792950 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93637 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.302348 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20015752250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1926.117780 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940487 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940487 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13792950 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13792950 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13792950 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13792950 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13792950 # number of overall hits +system.cpu.icache.overall_hits::total 13792950 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106403 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106403 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106403 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106403 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106403 # number of overall misses +system.cpu.icache.overall_misses::total 106403 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2026702474 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2026702474 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2026702474 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2026702474 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2026702474 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2026702474 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13899353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13899353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13899353 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13899353 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13899353 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13899353 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007655 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007655 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007655 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007655 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007655 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007655 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19047.418531 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19047.418531 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19047.418531 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19047.418531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19047.418531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19047.418531 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 673 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 35.812500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.866667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12604 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12604 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12604 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12604 # 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number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130806 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7651 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 158649 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166306 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7657 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166300 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7651 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158649 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166306 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 538279000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1751974750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2290253750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12463858000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12463858000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538279000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14215832750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14754111750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538279000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14215832750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14754111750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448098 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228454 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 166300 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 503573000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1760000500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2263573500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12201880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12201880000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503573000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13961880500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14465453500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503573000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13961880500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14465453500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081708 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.227863 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912049 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912049 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771767 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.556501 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082090 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771767 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.556501 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70298.942144 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62903.014146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64497.838576 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95291.619838 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95291.619838 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771823 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555836 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65817.932296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63211.597170 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63773.412408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93282.265340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93282.265340 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65817.932296 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88004.844027 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86984.085989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65817.932296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88004.844027 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86984.085989 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201470 # number of replacements -system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994745 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994745 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20615905 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20615905 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574108 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574108 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34190013 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34190013 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34190013 # number of overall hits -system.cpu.dcache.overall_hits::total 34190013 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267467 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267467 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039269 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039269 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306736 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306736 # number of overall misses -system.cpu.dcache.overall_misses::total 1306736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15939734750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15939734750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 90566913172 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 90566913172 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106506647922 # 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Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994631 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994631 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20611135 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20611135 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574043 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574043 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 55 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 55 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34185178 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34185178 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34185178 # number of overall hits +system.cpu.dcache.overall_hits::total 34185178 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267491 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105301044001 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105301044001 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105301044001 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20878626 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20878626 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35496749 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35496749 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35496749 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35496749 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012808 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012808 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071118 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036813 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036813 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036813 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036813 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59595.145382 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59595.145382 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87144.823113 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 87144.823113 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81505.864935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81505.864935 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5253118 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 160 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112229 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35492003 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35492003 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35492003 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35492003 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036820 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036820 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036820 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036820 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60927.246150 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60927.246150 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85635.179837 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85635.179837 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80577.769786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80577.769786 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5154697 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112181 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.807135 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 160 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.949822 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks -system.cpu.dcache.writebacks::total 168929 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205307 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205307 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895863 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101170 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101170 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101170 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62160 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62160 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205566 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205566 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2516687000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2516687000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14340164994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14340164994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16856851994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16856851994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16856851994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16856851994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002977 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002977 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 168935 # number of writebacks +system.cpu.dcache.writebacks::total 168935 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205357 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205357 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895917 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895917 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101274 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101274 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101274 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101274 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62134 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62134 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205551 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205551 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205551 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205551 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523454750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523454750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14076498244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14076498244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16599952994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16599952994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16599952994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16599952994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.242600 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.242600 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99996.966612 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99996.966612 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40613.106351 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40613.106351 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98150.834587 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98150.834587 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 9aa909b09..1084e1661 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026765 # Number of seconds simulated -sim_ticks 26765004500 # Number of ticks simulated -final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026816 # Number of seconds simulated +sim_ticks 26816405500 # Number of ticks simulated +final_tick 26816405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122306 # Simulator instruction rate (inst/s) -host_op_rate 173568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46166163 # Simulator tick rate (ticks/s) -host_mem_usage 255896 # Number of bytes of host memory used -host_seconds 579.75 # Real time elapsed on the host +host_inst_rate 109329 # Simulator instruction rate (inst/s) +host_op_rate 155152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41346943 # Simulator tick rate (ticks/s) +host_mem_usage 283460 # Number of bytes of host memory used +host_seconds 648.57 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7944704 # Number of bytes read from this memory -system.physmem.bytes_read::total 8242496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 297792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 297792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372160 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372160 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4653 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124136 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128789 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83940 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83940 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11126170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296831783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307957953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11126170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11126170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200715827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200715827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200715827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128790 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 83940 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 128790 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 83940 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 8242496 # Total number of bytes read from memory -system.physmem.bytesWritten 5372160 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8159 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8089 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7888 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7978 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8014 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5206 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5091 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5143 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5363 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5227 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26764988000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128790 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83940 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 76190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 50560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942848 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372096 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124107 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128770 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83939 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83939 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11128710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296193612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307322322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11128710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11128710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200328713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200328713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200328713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11128710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296193612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 507651035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128770 # Number of read requests accepted +system.physmem.writeReqs 83939 # Number of write requests accepted +system.physmem.readBursts 128770 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83939 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8241152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8241280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 318 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8144 # Per bank write bursts +system.physmem.perBankRdBursts::1 8386 # Per bank write bursts +system.physmem.perBankRdBursts::2 8247 # Per bank write bursts +system.physmem.perBankRdBursts::3 8164 # Per bank write bursts +system.physmem.perBankRdBursts::4 8296 # Per bank write bursts +system.physmem.perBankRdBursts::5 8451 # Per bank write bursts +system.physmem.perBankRdBursts::6 8094 # Per bank write bursts +system.physmem.perBankRdBursts::7 7961 # Per bank write bursts +system.physmem.perBankRdBursts::8 8061 # Per bank write bursts +system.physmem.perBankRdBursts::9 7610 # Per bank write bursts +system.physmem.perBankRdBursts::10 7787 # Per bank write bursts +system.physmem.perBankRdBursts::11 7813 # Per bank write bursts +system.physmem.perBankRdBursts::12 7882 # Per bank write bursts +system.physmem.perBankRdBursts::13 7886 # Per bank write bursts +system.physmem.perBankRdBursts::14 7979 # Per bank write bursts +system.physmem.perBankRdBursts::15 8007 # Per bank write bursts +system.physmem.perBankWrBursts::0 5180 # Per bank write bursts +system.physmem.perBankWrBursts::1 5376 # Per bank write bursts +system.physmem.perBankWrBursts::2 5287 # Per bank write bursts +system.physmem.perBankWrBursts::3 5157 # Per bank write bursts +system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::5 5517 # Per bank write bursts +system.physmem.perBankWrBursts::6 5205 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::8 5030 # Per bank write bursts +system.physmem.perBankWrBursts::9 5090 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::11 5144 # Per bank write bursts +system.physmem.perBankWrBursts::12 5342 # Per bank write bursts +system.physmem.perBankWrBursts::13 5363 # Per bank write bursts +system.physmem.perBankWrBursts::14 5451 # Per bank write bursts +system.physmem.perBankWrBursts::15 5223 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 26816294000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 128770 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 83939 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 72833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,214 +127,221 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34959 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 389.285277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.799947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 855.459025 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 13425 38.40% 38.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5427 15.52% 53.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3113 8.90% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2218 6.34% 69.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1684 4.82% 73.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1324 3.79% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1016 2.91% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 832 2.38% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 675 1.93% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 524 1.50% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 431 1.23% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 550 1.57% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 311 0.89% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 325 0.93% 91.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 173 0.49% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 178 0.51% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 117 0.33% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 209 0.60% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 130 0.37% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 238 0.68% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 111 0.32% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 314 0.90% 95.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 120 0.34% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 318 0.91% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 69 0.20% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 140 0.40% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 41 0.12% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 97 0.28% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 65 0.19% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 25 0.07% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 42 0.12% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 12 0.03% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 31 0.09% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.05% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 26 0.07% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 33 0.09% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 11 0.03% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 15 0.04% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 11 0.03% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 8 0.02% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 11 0.03% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 15 0.04% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 9 0.03% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 11 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 6 0.02% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 5 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 3 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 7 0.02% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 3 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 4 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 6 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 3 0.01% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 9 0.03% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 3 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 3 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 4 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 4 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 4 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 5 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 2 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 6 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 239 0.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34959 # Bytes accessed per row activation -system.physmem.totQLat 2852295000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4861110000 # Sum of mem lat for all requests -system.physmem.totBusLat 643935000 # Total cycles spent in databus access -system.physmem.totBankLat 1364880000 # Total cycles spent in bank access -system.physmem.avgQLat 22147.38 # Average queueing delay per request -system.physmem.avgBankLat 10597.96 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37745.35 # Average memory access latency -system.physmem.avgRdBW 307.96 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 200.72 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 307.96 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 200.72 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 37861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.431816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.292002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 695.442994 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 15095 39.87% 39.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5646 14.91% 54.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3407 9.00% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2352 6.21% 69.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1734 4.58% 74.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1565 4.13% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1073 2.83% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 929 2.45% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 665 1.76% 85.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 565 1.49% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 384 1.01% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 558 1.47% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 286 0.76% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 361 0.95% 91.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 176 0.46% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 218 0.58% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 133 0.35% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 117 0.31% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 270 0.71% 94.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 104 0.27% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 418 1.10% 95.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 100 0.26% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 243 0.64% 96.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 38 0.10% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 144 0.38% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 38 0.10% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 86 0.23% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 54 0.14% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 16 0.04% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 43 0.11% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 22 0.06% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 34 0.09% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 17 0.04% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 32 0.08% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 11 0.03% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 29 0.08% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 17 0.04% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 31 0.08% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 15 0.04% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 11 0.03% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 11 0.03% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 9 0.02% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 8 0.02% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 21 0.06% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 10 0.03% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 21 0.06% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 6 0.02% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 11 0.03% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 10 0.03% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 7 0.02% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 17 0.04% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 5 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 7 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 6 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 6 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 13 0.03% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 11 0.03% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 8 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 10 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 6 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 7 0.02% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.02% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 4 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 2 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 6 0.02% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 3 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 36 0.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37861 # Bytes accessed per row activation +system.physmem.totQLat 3024623000 # Total ticks spent queuing +system.physmem.totMemAccLat 4968016750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643840000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1299553750 # Total ticks spent accessing banks +system.physmem.avgQLat 23488.93 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10092.21 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 38581.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 307.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 200.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 307.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 200.33 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.97 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 10.24 # Average write queue length over time -system.physmem.readRowHits 120249 # Number of row buffer hits during reads -system.physmem.writeRowHits 57506 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.51 # Row buffer hit rate for writes -system.physmem.avgGap 125816.71 # Average gap between requests -system.membus.throughput 508673780 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26538 # Transaction distribution -system.membus.trans_dist::ReadResp 26537 # Transaction distribution -system.membus.trans_dist::Writeback 83940 # Transaction distribution -system.membus.trans_dist::UpgradeReq 321 # Transaction distribution -system.membus.trans_dist::UpgradeResp 321 # Transaction distribution -system.membus.trans_dist::ReadExReq 102252 # Transaction distribution -system.membus.trans_dist::ReadExResp 102252 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342161 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13614656 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13614656 # Total data (bytes) +system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.56 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.76 # Average write queue length when enqueuing +system.physmem.readRowHits 117866 # Number of row buffer hits during reads +system.physmem.writeRowHits 56971 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.87 # Row buffer hit rate for writes +system.physmem.avgGap 126070.33 # Average gap between requests +system.physmem.pageHitRate 82.20 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.88 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 507651035 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26514 # Transaction distribution +system.membus.trans_dist::ReadResp 26514 # Transaction distribution +system.membus.trans_dist::Writeback 83939 # Transaction distribution +system.membus.trans_dist::UpgradeReq 318 # Transaction distribution +system.membus.trans_dist::UpgradeResp 318 # Transaction distribution +system.membus.trans_dist::ReadExReq 102256 # Transaction distribution +system.membus.trans_dist::ReadExResp 102256 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342115 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342115 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613376 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13613376 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13613376 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934803500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1207011429 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1203423433 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) -system.cpu.branchPred.lookups 16635237 # Number of BP lookups -system.cpu.branchPred.condPredicted 12768503 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 604840 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10652885 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7773045 # Number of BTB hits +system.cpu.branchPred.lookups 16622919 # Number of BP lookups +system.cpu.branchPred.condPredicted 12749857 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 605504 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10570940 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7775711 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.966572 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1823659 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113448 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.557423 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1829148 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113993 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -376,136 +385,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53530010 # number of cpu cycles simulated +system.cpu.numCycles 53632812 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12549473 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85279503 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16635237 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9596704 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21206249 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2379470 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10773225 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 477 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11686664 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 178212 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46277294 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.580240 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.332526 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12575227 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85200235 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16622919 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9604859 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21200799 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2368859 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10684050 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 493 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11692200 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 184239 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46197272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332808 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25091643 54.22% 54.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2136768 4.62% 58.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1963962 4.24% 63.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042989 4.41% 67.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466847 3.17% 70.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1383026 2.99% 73.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 957932 2.07% 75.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1190240 2.57% 78.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10043887 21.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25016575 54.15% 54.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2138831 4.63% 58.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1968354 4.26% 63.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2045405 4.43% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466932 3.18% 70.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1376276 2.98% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 961294 2.08% 75.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1190217 2.58% 78.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10033388 21.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46277294 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310765 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.593116 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14640784 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9115289 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19504792 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1371825 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1644604 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3334519 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105037 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116943845 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363315 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1644604 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16350397 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2675070 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1001661 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19117578 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5487984 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115077475 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 183 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17134 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4627273 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 285 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115384718 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 530174580 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476867094 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3452 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46197272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309939 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.588584 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14661485 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9032065 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19500717 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1369785 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1633220 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3334387 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105402 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116870755 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 365005 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1633220 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16370455 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2587455 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1031873 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19111398 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5462871 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114984523 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15960 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4602334 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 241 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115277175 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529754178 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476504412 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2548 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16252046 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20256 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20253 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13031784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29643166 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22451729 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3891559 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4392801 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111618845 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35897 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107291250 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 275974 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10887740 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26073816 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2111 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46277294 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.318443 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.990403 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16144503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20627 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20613 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12986013 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29603679 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22442541 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3905979 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4383979 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111534291 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36144 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107247539 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 279427 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10792871 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25872402 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2358 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46197272 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.321512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.989577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11003161 23.78% 23.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8115395 17.54% 41.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7436608 16.07% 57.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7096880 15.34% 72.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5407297 11.68% 84.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3935038 8.50% 92.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1843993 3.98% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 867713 1.88% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571209 1.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10946962 23.70% 23.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8090791 17.51% 41.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7422192 16.07% 57.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7125519 15.42% 72.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5414632 11.72% 84.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3916527 8.48% 92.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1842332 3.99% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 865884 1.87% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 572433 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46277294 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46197272 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 113414 4.57% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1362149 54.91% 59.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1005332 40.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111334 4.52% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1349070 54.73% 59.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1004381 40.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56660345 52.81% 52.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91595 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56643981 52.82% 52.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91446 0.09% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 269 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 176 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued @@ -531,84 +540,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28911335 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21627699 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28888115 26.94% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21623814 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107291250 # Type of FU issued -system.cpu.iq.rate 2.004320 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2480897 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023123 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263615967 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122570490 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105600159 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 698 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1174 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 216 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109771796 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 351 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2179165 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107247539 # Type of FU issued +system.cpu.iq.rate 1.999663 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2464786 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022982 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263436010 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122391385 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105557389 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 553 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 926 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109712054 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 271 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2181647 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2336058 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6530 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30281 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1895991 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2296571 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6409 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29938 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1886803 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 805 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1644604 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1147402 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 47438 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111664541 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 286964 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29643166 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22451729 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19977 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6774 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4975 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30281 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393124 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181749 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 574873 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106260947 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28610039 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030303 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1633220 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1092915 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45139 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111580294 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 294739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29603679 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22442541 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20224 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6335 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5295 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29938 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 394730 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181332 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 576062 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106214921 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28587238 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1032618 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9799 # number of nop insts executed -system.cpu.iew.exec_refs 49952901 # number of memory reference insts executed -system.cpu.iew.exec_branches 14605114 # Number of branches executed -system.cpu.iew.exec_stores 21342862 # Number of stores executed -system.cpu.iew.exec_rate 1.985072 # Inst execution rate -system.cpu.iew.wb_sent 105821179 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105600375 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53334269 # num instructions producing a value -system.cpu.iew.wb_consumers 103952809 # num instructions consuming a value +system.cpu.iew.exec_nop 9859 # number of nop insts executed +system.cpu.iew.exec_refs 49925863 # number of memory reference insts executed +system.cpu.iew.exec_branches 14600722 # Number of branches executed +system.cpu.iew.exec_stores 21338625 # Number of stores executed +system.cpu.iew.exec_rate 1.980409 # Inst execution rate +system.cpu.iew.wb_sent 105779922 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105557547 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53302648 # num instructions producing a value +system.cpu.iew.wb_consumers 103946447 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.972732 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.513062 # average fanout of values written-back +system.cpu.iew.wb_rate 1.968152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512790 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11033009 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10948789 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 501673 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44632690 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.254680 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.761954 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 502113 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44564052 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.258153 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.763889 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15532654 34.80% 34.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11684135 26.18% 60.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3462025 7.76% 68.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2877014 6.45% 75.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1854993 4.16% 79.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1951437 4.37% 83.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 690877 1.55% 85.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 565658 1.27% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6013897 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15506218 34.80% 34.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11644493 26.13% 60.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3446423 7.73% 68.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2869378 6.44% 75.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1870309 4.20% 79.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1959985 4.40% 83.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685768 1.54% 85.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 560638 1.26% 86.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6020840 13.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44632690 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44564052 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -619,226 +628,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6013897 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6020840 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150258931 # The number of ROB reads -system.cpu.rob.rob_writes 224984633 # The number of ROB writes -system.cpu.timesIdled 80350 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7252716 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150099130 # The number of ROB reads +system.cpu.rob.rob_writes 224804524 # The number of ROB writes +system.cpu.timesIdled 76985 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7435540 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.754926 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.754926 # CPI: Total CPI of All Threads -system.cpu.ipc 1.324633 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.324633 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511766096 # number of integer regfile reads -system.cpu.int_regfile_writes 103375635 # number of integer regfile writes -system.cpu.fp_regfile_reads 1160 # number of floating regfile reads -system.cpu.fp_regfile_writes 1012 # number of floating regfile writes -system.cpu.misc_regfile_reads 49188390 # number of misc regfile reads +system.cpu.cpi 0.756376 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.756376 # CPI: Total CPI of All Threads +system.cpu.ipc 1.322094 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.322094 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511539854 # number of integer regfile reads +system.cpu.int_regfile_writes 103334614 # number of integer regfile writes +system.cpu.fp_regfile_reads 734 # number of floating regfile reads +system.cpu.fp_regfile_writes 630 # number of floating regfile writes +system.cpu.misc_regfile_reads 49164319 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 771895107 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 86668 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 86666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129110 # Transaction distribution +system.cpu.toL2Bus.throughput 775188755 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 88572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 88572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129187 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61963 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454719 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 516682 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1966784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20627776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 107050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107050 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65806 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 520581 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2089088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18665280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20754368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20754368 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 33408 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291762996 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47827231 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 50495227 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 260303004 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 28871 # number of replacements -system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 30799 # number of replacements +system.cpu.icache.tags.tagsinuse 1804.677341 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11655246 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 32836 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 354.953283 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11651673 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11651673 # number of overall hits -system.cpu.icache.overall_hits::total 11651673 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34991 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34991 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34991 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34991 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34991 # number of overall misses -system.cpu.icache.overall_misses::total 34991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 840169228 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 840169228 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 840169228 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 840169228 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 840169228 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 840169228 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11686664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11686664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11686664 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11686664 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11686664 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11686664 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002994 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002994 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002994 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002994 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002994 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002994 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24011.009345 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24011.009345 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24011.009345 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24011.009345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24011.009345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24011.009345 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1080 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1804.677341 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.881190 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.881190 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11655255 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11655255 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11655255 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11655255 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11655255 # number of overall hits +system.cpu.icache.overall_hits::total 11655255 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 36945 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 36945 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 36945 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 36945 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 36945 # number of overall misses +system.cpu.icache.overall_misses::total 36945 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 836533724 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 836533724 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 836533724 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 836533724 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 836533724 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 836533724 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11692200 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11692200 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11692200 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11692200 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11692200 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11692200 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003160 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003160 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003160 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003160 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003160 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003160 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22642.677602 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22642.677602 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22642.677602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22642.677602 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 965 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.956522 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 48.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3759 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3759 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3759 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3759 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3759 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3759 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31232 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31232 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31232 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31232 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31232 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31232 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 684118269 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 684118269 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 684118269 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 684118269 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 684118269 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 684118269 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002672 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002672 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002672 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002672 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21904.401543 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21904.401543 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3781 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3781 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3781 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3781 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3781 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3781 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33164 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 33164 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 33164 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 33164 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 33164 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 33164 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 680570772 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 680570772 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 680570772 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 680570772 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 680570772 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 680570772 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002836 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002836 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002836 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20521.371728 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20521.371728 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20521.371728 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20521.371728 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20521.371728 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20521.371728 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95660 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29916.504006 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 88398 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126774 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.697288 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95639 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29886.699201 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 90376 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126754 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.713003 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26705.369214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.053749 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1845.081043 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.814983 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041689 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.056307 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.912979 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26062 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33492 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 59554 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129110 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129110 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4780 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4780 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26062 # 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number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4663 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21851 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26514 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 318 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 318 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102256 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102256 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4663 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124107 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128770 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4663 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124107 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128770 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307037750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1604664499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1911702249 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3189317 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3189317 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7230852500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7230852500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307037750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8835516999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9142554749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307037750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8835516999 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9142554749 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394365 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.301124 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.946429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.946429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955217 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955217 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.660021 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.660021 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65845.539352 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73436.661892 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72101.616090 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.298742 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.298742 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70713.234431 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70713.234431 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158372 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26075013 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26075013 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266800 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266800 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15987 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15987 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 158362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.865935 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44347537 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 272.978474 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.865935 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993375 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993375 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26048299 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26048299 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266707 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44341813 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44341813 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44341813 # number of overall hits -system.cpu.dcache.overall_hits::total 44341813 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125377 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125377 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583101 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583101 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1708478 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1708478 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1708478 # number of overall misses -system.cpu.dcache.overall_misses::total 1708478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5199394222 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5199394222 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 124981048011 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 124981048011 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 861250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 861250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 130180442233 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 130180442233 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 130180442233 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 130180442233 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26200390 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26200390 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44315006 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44315006 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44315006 # number of overall hits +system.cpu.dcache.overall_hits::total 44315006 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125034 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125034 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583194 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583194 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708228 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708228 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708228 # number of overall misses +system.cpu.dcache.overall_misses::total 1708228 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5241649212 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5241649212 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126812367989 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126812367989 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 914750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 914750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 132054017201 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 132054017201 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 132054017201 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 132054017201 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26173333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26173333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46050291 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46050291 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46050291 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46050291 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004785 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004785 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079754 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079754 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002620 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002620 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037100 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037100 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037100 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037100 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41470.080015 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41470.080015 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78946.983175 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 78946.983175 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20505.952381 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20505.952381 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76196.733135 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76196.733135 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9105 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1249 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 129 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.581395 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 78.062500 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46023234 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46023234 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46023234 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46023234 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004777 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004777 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079758 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079758 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002558 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037117 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037117 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037117 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037117 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41921.790969 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41921.790969 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80099.070606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80099.070606 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22310.975610 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22310.975610 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77304.679001 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77304.679001 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4730 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.028777 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 87.428571 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129110 # number of writebacks -system.cpu.dcache.writebacks::total 129110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69907 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69907 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475766 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475766 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545673 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545673 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545673 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545673 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55470 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55470 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107335 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107335 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162805 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162805 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162805 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162805 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2262652309 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2262652309 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8543267922 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8543267922 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10805920231 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10805920231 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10805920231 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10805920231 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40790.559023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40790.559023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79594.427931 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79594.427931 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129187 # number of writebacks +system.cpu.dcache.writebacks::total 129187 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69592 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69592 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475842 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475842 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545434 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545434 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545434 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545434 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55442 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55442 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107352 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107352 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162794 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162794 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162794 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162794 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2274282063 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2274282063 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8672803924 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8672803924 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947085987 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10947085987 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947085987 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10947085987 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003537 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003537 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41020.923902 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41020.923902 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80788.470862 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80788.470862 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |