diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
| commit | 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch) | |
| tree | 81108e7ff1951b652258f53bd5615a617b734ce2 /tests/long/se/50.vortex | |
| parent | ddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff) | |
| download | gem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz | |
update stats for preceeding changes
Diffstat (limited to 'tests/long/se/50.vortex')
9 files changed, 1939 insertions, 1862 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index fc9577d62..00b189ec1 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index e501186a7..2318eb90a 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:54:39 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:19:26 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 47910283500 because target called exit() +Exiting @ tick 43266024500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index e532ddba3..130fea357 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043596 # Number of seconds simulated -sim_ticks 43595903500 # Number of ticks simulated -final_tick 43595903500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043266 # Number of seconds simulated +sim_ticks 43266024500 # Number of ticks simulated +final_tick 43266024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146921 # Simulator instruction rate (inst/s) -host_op_rate 146921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72505010 # Simulator tick rate (ticks/s) -host_mem_usage 252940 # Number of bytes of host memory used -host_seconds 601.28 # Real time elapsed on the host +host_inst_rate 113775 # Simulator instruction rate (inst/s) +host_op_rate 113775 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55722813 # Simulator tick rate (ticks/s) +host_mem_usage 252752 # Number of bytes of host memory used +host_seconds 776.45 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 454912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10138304 # Number of bytes read from this memory -system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 454912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 454912 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 454720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory +system.physmem.bytes_read::total 10593088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454720 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7108 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158411 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165517 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10434742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 232551758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242986500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10434742 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10434742 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 167350770 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 167350770 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 167350770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10434742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 232551758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 410337269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165519 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 10509863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 234326313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 244836176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10509863 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10509863 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 168626725 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 168626725 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 168626725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10509863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 234326313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 413462901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165517 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279516 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10593216 # Total number of bytes read from memory +system.physmem.cpureqs 279514 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10593088 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10593088 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10332 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10222 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10233 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 9969 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10217 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 10609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10334 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 10345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9920 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10624 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10242 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 6899 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 7374 # Tr system.physmem.perBankWrReqs::15 7193 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43595883500 # Total gap between requests +system.physmem.totGap 43266004500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165519 # Categorize read packet sizes +system.physmem.readPktSize::6 165517 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 71904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6270 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,13 +138,13 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4923 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4950 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see @@ -161,57 +161,57 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9323896604 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11720942604 # Sum of mem lat for all requests +system.physmem.totQLat 9309879146 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11706015146 # Sum of mem lat for all requests system.physmem.totBusLat 662068000 # Total cycles spent in databus access -system.physmem.totBankLat 1734978000 # Total cycles spent in bank access -system.physmem.avgQLat 56331.96 # Average queueing delay per request -system.physmem.avgBankLat 10482.17 # Average bank access latency per request +system.physmem.totBankLat 1734068000 # Total cycles spent in bank access +system.physmem.avgQLat 56247.27 # Average queueing delay per request +system.physmem.avgBankLat 10476.68 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70814.13 # Average memory access latency -system.physmem.avgRdBW 242.99 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 167.35 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 242.99 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 167.35 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 70723.94 # Average memory access latency +system.physmem.avgRdBW 244.84 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 168.63 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 244.84 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 168.63 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.56 # Data bus utilization in percentage +system.physmem.busUtil 2.58 # Data bus utilization in percentage system.physmem.avgRdQLen 0.27 # Average read queue length over time -system.physmem.avgWrQLen 10.36 # Average write queue length over time -system.physmem.readRowHits 151893 # Number of row buffer hits during reads -system.physmem.writeRowHits 41557 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.45 # Row buffer hit rate for writes -system.physmem.avgGap 155969.19 # Average gap between requests +system.physmem.avgWrQLen 10.35 # Average write queue length over time +system.physmem.readRowHits 151965 # Number of row buffer hits during reads +system.physmem.writeRowHits 41713 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.59 # Row buffer hit rate for writes +system.physmem.avgGap 154790.12 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277538 # DTB read hits +system.cpu.dtb.read_hits 20277550 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367686 # DTB read accesses -system.cpu.dtb.write_hits 14728672 # DTB write hits +system.cpu.dtb.read_accesses 20367698 # DTB read accesses +system.cpu.dtb.write_hits 14728696 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14735924 # DTB write accesses -system.cpu.dtb.data_hits 35006210 # DTB hits +system.cpu.dtb.write_accesses 14735948 # DTB write accesses +system.cpu.dtb.data_hits 35006246 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103610 # DTB accesses -system.cpu.itb.fetch_hits 12476759 # ITB hits -system.cpu.itb.fetch_misses 12943 # ITB misses +system.cpu.dtb.data_accesses 35103646 # DTB accesses +system.cpu.itb.fetch_hits 12367278 # ITB hits +system.cpu.itb.fetch_misses 11044 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12489702 # ITB accesses +system.cpu.itb.fetch_accesses 12378322 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87191808 # number of cpu cycles simulated +system.cpu.numCycles 86532050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18827150 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12439421 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5024981 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16201522 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5047120 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660945 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 18742312 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12317439 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4774431 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 15498318 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 4661486 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660962 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.152135 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8476186 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10350964 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74333119 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 30.077367 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8071751 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10670561 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74169472 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126652369 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65259 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126488722 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66053 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292889 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14121677 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064639 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4680318 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 234163 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4914481 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8857790 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.683882 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44776328 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293683 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14165611 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060577 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4447125 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216806 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4663931 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9108659 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.863863 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44777842 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77836216 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77186042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 230753 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16919077 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70272731 # Number of cycles cpu stages are processed. -system.cpu.activity 80.595566 # Percentage of cycles cpu is active +system.cpu.timesIdled 230961 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16958681 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69573369 # Number of cycles cpu stages are processed. +system.cpu.activity 80.401850 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -272,302 +272,194 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.986995 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.979527 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.986995 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013176 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.979527 # CPI: Total CPI of All Threads +system.cpu.ipc 1.020901 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.013176 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33768817 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53422991 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.270654 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44539685 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42652123 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.917581 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44072021 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43119787 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.453943 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65076368 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22115440 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.364126 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41085926 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46105882 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.878686 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85196 # number of replacements -system.cpu.icache.tagsinuse 1908.917223 # Cycle average of tags in use -system.cpu.icache.total_refs 12358549 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87242 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.658249 # Average number of references to valid blocks. +system.cpu.ipc_total 1.020901 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 33881250 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52650800 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.845432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44079875 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42452175 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 49.059481 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 43502532 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43029518 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.726683 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 64419596 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22112454 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.554062 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40482959 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46049091 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 53.216226 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 84282 # number of replacements +system.cpu.icache.tagsinuse 1908.908494 # Cycle average of tags in use +system.cpu.icache.total_refs 12250113 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 86328 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.901967 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1908.917223 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.932088 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.932088 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12358549 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12358549 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12358549 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12358549 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12358549 # number of overall hits -system.cpu.icache.overall_hits::total 12358549 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118203 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118203 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118203 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118203 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118203 # number of overall misses -system.cpu.icache.overall_misses::total 118203 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1846898500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1846898500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1846898500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1846898500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1846898500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1846898500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12476752 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12476752 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12476752 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12476752 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12476752 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12476752 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009474 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009474 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009474 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009474 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009474 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15624.802247 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15624.802247 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15624.802247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15624.802247 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1908.908494 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.932084 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.932084 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12250113 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250113 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250113 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250113 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250113 # number of overall hits +system.cpu.icache.overall_hits::total 12250113 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117156 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117156 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117156 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117156 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117156 # number of overall misses +system.cpu.icache.overall_misses::total 117156 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1822166500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1822166500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1822166500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1822166500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1822166500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1822166500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12367269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367269 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367269 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367269 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367269 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15553.334870 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15553.334870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15553.334870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15553.334870 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 309 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 12.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.263158 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 6.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30961 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30961 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30961 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30961 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30961 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30961 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87242 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87242 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87242 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87242 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87242 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87242 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1292347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1292347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1292347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1292347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1292347500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1292347500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006992 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006992 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006992 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14813.363976 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14813.363976 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30828 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30828 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30828 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30828 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30828 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86328 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 86328 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 86328 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 86328 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 86328 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 86328 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1279244500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1279244500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1279244500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1279244500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1279244500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1279244500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006980 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for 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Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.184647 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 249990000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.664341 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995768 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995768 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180268 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180268 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574719 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574719 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754987 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754987 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754987 # number of overall hits -system.cpu.dcache.overall_hits::total 33754987 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96370 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96370 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038658 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038658 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135028 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135028 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135028 # number of overall misses -system.cpu.dcache.overall_misses::total 1135028 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3954988500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3954988500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 91520281000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 91520281000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95475269500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95475269500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95475269500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95475269500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071076 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071076 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032532 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032532 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032532 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032532 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.623327 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.623327 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88113.971105 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 88113.971105 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84117.105041 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84117.105041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84117.105041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84117.105041 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6175044 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 397 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116295 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.098104 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 397 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168353 # number of writebacks -system.cpu.dcache.writebacks::total 168353 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35603 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35603 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895078 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895078 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930681 # number of 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misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1939972500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1939972500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14546837500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14546837500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16486810000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16486810000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16486810000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16486810000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31924.770023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31924.770023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101315.207550 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101315.207550 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80680.460198 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80680.460198 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80680.460198 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80680.460198 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 131596 # number of replacements -system.cpu.l2cache.tagsinuse 30981.821005 # Cycle average of tags in use -system.cpu.l2cache.total_refs 152256 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.930353 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 131593 # number of replacements +system.cpu.l2cache.tagsinuse 30981.522130 # Cycle average of tags in use +system.cpu.l2cache.total_refs 151339 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 163652 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.924761 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27273.690706 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2026.855781 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1681.274518 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.832327 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061855 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051308 # 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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99861.957187 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97995.825253 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082302 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775218 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.569427 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082302 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.569427 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56005.418719 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55958.486247 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 55968.116444 # average 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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -578,50 +470,158 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks system.cpu.l2cache.writebacks::total 113997 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7108 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27520 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34628 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7105 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34626 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses 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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569427 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569427 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43308.036735 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43144.052142 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 43177.700572 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96624.975338 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96624.975338 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 200249 # number of replacements +system.cpu.dcache.tagsinuse 4078.683111 # Cycle average of tags in use +system.cpu.dcache.total_refs 33755002 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 204345 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 165.186337 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 248488000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4078.683111 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995772 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995772 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # 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cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032531 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032531 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032531 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032531 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40910.768209 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40910.768209 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88012.808503 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 88012.808503 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84013.662839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84013.662839 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6187652 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 65 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116324 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.193253 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 65 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks +system.cpu.dcache.writebacks::total 168350 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35602 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35602 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895066 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895066 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses 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+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16475949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16475949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16475949500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16475949500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31840.582572 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31840.582572 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101275.640758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101275.640758 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 0698ab8df..06d858804 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 3d5324180..8fd1a4d9e 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 10:05:33 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 12:32:34 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 21619648000 because target called exit() +Exiting @ tick 24414646000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 04dfac9bb..c5e407e29 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024767 # Number of seconds simulated -sim_ticks 24766869000 # Number of ticks simulated -final_tick 24766869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024415 # Number of seconds simulated +sim_ticks 24414646000 # Number of ticks simulated +final_tick 24414646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162319 # Simulator instruction rate (inst/s) -host_op_rate 162319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50509376 # Simulator tick rate (ticks/s) -host_mem_usage 253968 # Number of bytes of host memory used -host_seconds 490.34 # Real time elapsed on the host +host_inst_rate 171645 # Simulator instruction rate (inst/s) +host_op_rate 171645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52651835 # Simulator tick rate (ticks/s) +host_mem_usage 254848 # Number of bytes of host memory used +host_seconds 463.70 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 491520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory -system.physmem.bytes_read::total 10646272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 491520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 491520 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 490368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153920 # Number of bytes read from this memory +system.physmem.bytes_read::total 10644288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490368 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7680 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158655 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166317 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19845867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 410013555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 429859422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19845867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19845867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 294625857 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 294625857 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 294625857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19845867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 410013555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 724485279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166348 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 20084993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 415894623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 435979616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20084993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20084993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 298876338 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 298876338 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 298876338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20084993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 415894623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 734855955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166317 # Total number of read requests seen system.physmem.writeReqs 114015 # Total number of write requests seen -system.physmem.cpureqs 280363 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10646272 # Total number of bytes read from memory +system.physmem.cpureqs 280332 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10644288 # Total number of bytes read from memory system.physmem.bytesWritten 7296960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10646272 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10644288 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10314 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10735 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10586 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10583 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10274 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 10277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10016 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10446 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10255 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis +system.physmem.perBankRdReqs::7 10017 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10445 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10374 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9953 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10252 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7409 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 6902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7249 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7298 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7207 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6885 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7299 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6884 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7381 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 7081 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 7120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7375 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6936 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7376 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7191 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24766835500 # Total gap between requests +system.physmem.totGap 24414612500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166348 # Categorize read packet sizes +system.physmem.readPktSize::6 166317 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,14 +138,14 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4936 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see @@ -161,57 +161,57 @@ system.physmem.wrQLenPdf::19 4957 # Wh system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9402171924 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11754135924 # Sum of mem lat for all requests -system.physmem.totBusLat 665384000 # Total cycles spent in databus access -system.physmem.totBankLat 1686580000 # Total cycles spent in bank access -system.physmem.avgQLat 56521.78 # Average queueing delay per request -system.physmem.avgBankLat 10138.99 # Average bank access latency per request +system.physmem.totQLat 9394568799 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11745778799 # Sum of mem lat for all requests +system.physmem.totBusLat 665260000 # Total cycles spent in databus access +system.physmem.totBankLat 1685950000 # Total cycles spent in bank access +system.physmem.avgQLat 56486.60 # Average queueing delay per request +system.physmem.avgBankLat 10137.09 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70660.77 # Average memory access latency -system.physmem.avgRdBW 429.86 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 294.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 429.86 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 294.63 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 70623.69 # Average memory access latency +system.physmem.avgRdBW 435.98 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 298.88 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 435.98 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 298.88 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 4.53 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.47 # Average read queue length over time -system.physmem.avgWrQLen 9.66 # Average write queue length over time -system.physmem.readRowHits 152267 # Number of row buffer hits during reads -system.physmem.writeRowHits 40679 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.68 # Row buffer hit rate for writes -system.physmem.avgGap 88338.46 # Average gap between requests +system.physmem.busUtil 4.59 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.48 # Average read queue length over time +system.physmem.avgWrQLen 10.01 # Average write queue length over time +system.physmem.readRowHits 152275 # Number of row buffer hits during reads +system.physmem.writeRowHits 40821 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 35.80 # Row buffer hit rate for writes +system.physmem.avgGap 87091.78 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22524754 # DTB read hits -system.cpu.dtb.read_misses 221109 # DTB read misses -system.cpu.dtb.read_acv 49 # DTB read access violations -system.cpu.dtb.read_accesses 22745863 # DTB read accesses -system.cpu.dtb.write_hits 15800982 # DTB write hits -system.cpu.dtb.write_misses 41722 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15842704 # DTB write accesses -system.cpu.dtb.data_hits 38325736 # DTB hits -system.cpu.dtb.data_misses 262831 # DTB misses -system.cpu.dtb.data_acv 50 # DTB access violations -system.cpu.dtb.data_accesses 38588567 # DTB accesses -system.cpu.itb.fetch_hits 14187534 # ITB hits -system.cpu.itb.fetch_misses 37797 # ITB misses +system.cpu.dtb.read_hits 22403664 # DTB read hits +system.cpu.dtb.read_misses 220373 # DTB read misses +system.cpu.dtb.read_acv 50 # DTB read access violations +system.cpu.dtb.read_accesses 22624037 # DTB read accesses +system.cpu.dtb.write_hits 15711393 # DTB write hits +system.cpu.dtb.write_misses 41143 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15752536 # DTB write accesses +system.cpu.dtb.data_hits 38115057 # DTB hits +system.cpu.dtb.data_misses 261516 # DTB misses +system.cpu.dtb.data_acv 54 # DTB access violations +system.cpu.dtb.data_accesses 38376573 # DTB accesses +system.cpu.itb.fetch_hits 13911095 # ITB hits +system.cpu.itb.fetch_misses 34570 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14225331 # ITB accesses +system.cpu.itb.fetch_accesses 13945665 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49533742 # number of cpu cycles simulated +system.cpu.numCycles 48829295 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16746521 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10800034 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477053 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12193904 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7496910 # Number of BTB hits +system.cpu.BPredUnit.lookups 16536427 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10675204 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 418905 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11705282 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7341882 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 2006546 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45028 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 16102899 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106919359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16746521 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9503456 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19851092 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2196928 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6491501 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314458 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14187534 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 227935 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44359313 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.410302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.133631 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1987114 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 42052 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15791672 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105370615 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16536427 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9328996 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19544366 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2001802 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6569447 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 313140 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13911095 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 206120 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43680847 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.412284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.135635 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24508221 55.25% 55.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1552927 3.50% 58.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1407762 3.17% 61.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1534147 3.46% 65.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4200830 9.47% 74.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1874236 4.23% 79.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 688640 1.55% 80.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1098273 2.48% 83.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7494277 16.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24136481 55.26% 55.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1528556 3.50% 58.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1370450 3.14% 61.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1506920 3.45% 65.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4142263 9.48% 74.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1846581 4.23% 79.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 675220 1.55% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1067886 2.44% 83.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7406490 16.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44359313 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.338083 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.158516 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17202144 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6044851 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18844952 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 783382 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1483984 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3808507 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109388 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 105012446 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304839 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1483984 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17687031 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3815602 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84566 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19093119 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2195011 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103566225 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 486 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2675 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2071816 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62457346 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124882897 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124424416 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 458481 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43680847 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.338658 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.157938 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16869436 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6110909 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18556945 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 793975 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1349582 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3748874 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107098 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103640564 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305578 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1349582 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17328003 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3849727 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84405 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18840913 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2228217 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102377631 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2729 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2099672 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61646345 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123373260 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122920505 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 452755 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9910465 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5561 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5559 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4548155 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23430190 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16410014 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1178549 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 390985 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91582200 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5227 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89129103 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 121099 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11405338 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5024468 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44359313 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.009253 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109781 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9099464 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5534 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4609870 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23237420 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16278692 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1191956 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 452268 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90762555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5288 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88451556 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 99102 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10723978 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4670719 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 705 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43680847 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.024951 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.111086 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15871640 35.78% 35.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6995929 15.77% 51.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5623158 12.68% 64.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4788485 10.79% 75.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4723434 10.65% 85.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2673880 6.03% 91.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1944632 4.38% 96.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1314765 2.96% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 423390 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15440168 35.35% 35.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6886071 15.76% 51.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5612203 12.85% 63.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4740584 10.85% 74.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4695591 10.75% 85.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2649897 6.07% 91.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1923598 4.40% 96.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1315990 3.01% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 416745 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44359313 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43680847 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 127127 6.74% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 794266 42.09% 48.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 965741 51.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126167 6.80% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 781555 42.12% 48.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 947649 51.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49762830 55.83% 55.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43850 0.05% 55.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121597 0.14% 56.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121881 0.14% 56.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 60 0.00% 56.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38947 0.04% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23025644 25.83% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16014206 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49366923 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43857 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121501 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121281 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 51 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22854121 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15904789 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89129103 # Type of FU issued -system.cpu.iq.rate 1.799361 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1887134 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021173 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224014583 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102585406 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87044839 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611169 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 425269 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 296604 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90710574 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305663 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1465776 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88451556 # Type of FU issued +system.cpu.iq.rate 1.811444 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1855371 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020976 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221933846 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101092156 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86564383 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 604586 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 417604 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294342 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90004545 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 302382 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1470214 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3153552 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5566 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18132 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1796637 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2960782 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4826 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18180 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1665315 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2518 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 82425 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2876 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 81924 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1483984 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2836184 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 76819 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101124099 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 260669 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23430190 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16410014 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5227 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60088 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 531 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18132 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 252052 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 171036 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 423088 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88146777 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22749364 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 982326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1349582 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2855245 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 77128 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100251958 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 208716 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23237420 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16278692 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5288 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60129 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 488 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18180 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 198098 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161281 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 359379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87608240 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22627118 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 843316 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9536672 # number of nop insts executed -system.cpu.iew.exec_refs 38592395 # number of memory reference insts executed -system.cpu.iew.exec_branches 15153499 # Number of branches executed -system.cpu.iew.exec_stores 15843031 # Number of stores executed -system.cpu.iew.exec_rate 1.779530 # Inst execution rate -system.cpu.iew.wb_sent 87753741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87341443 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33435183 # num instructions producing a value -system.cpu.iew.wb_consumers 43872218 # num instructions consuming a value +system.cpu.iew.exec_nop 9484115 # number of nop insts executed +system.cpu.iew.exec_refs 38379967 # number of memory reference insts executed +system.cpu.iew.exec_branches 15086881 # Number of branches executed +system.cpu.iew.exec_stores 15752849 # Number of stores executed +system.cpu.iew.exec_rate 1.794174 # Inst execution rate +system.cpu.iew.wb_sent 87251382 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86858725 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33364118 # num instructions producing a value +system.cpu.iew.wb_consumers 43780682 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.763272 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762104 # average fanout of values written-back +system.cpu.iew.wb_rate 1.778824 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762074 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9751269 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8914358 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 370067 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42875329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.060408 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.788298 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 313984 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42331265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.086889 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.804714 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19913451 46.45% 46.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7068985 16.49% 62.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3438952 8.02% 70.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2090019 4.87% 75.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2085052 4.86% 80.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1168150 2.72% 83.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1107868 2.58% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727256 1.70% 87.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275596 12.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19478152 46.01% 46.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7019307 16.58% 62.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3402930 8.04% 70.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2062880 4.87% 75.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2059752 4.87% 80.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1161194 2.74% 83.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1088223 2.57% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718067 1.70% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5340760 12.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42875329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42331265 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,304 +475,192 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275596 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5340760 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 134374332 # The number of ROB reads -system.cpu.rob.rob_writes 197671452 # The number of ROB writes -system.cpu.timesIdled 69954 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5174429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132928193 # The number of ROB reads +system.cpu.rob.rob_writes 195862433 # The number of ROB writes +system.cpu.timesIdled 69428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5148448 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.622348 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.622348 # CPI: Total CPI of All Threads -system.cpu.ipc 1.606819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.606819 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116696990 # number of integer regfile reads -system.cpu.int_regfile_writes 57893587 # number of integer regfile writes -system.cpu.fp_regfile_reads 251486 # number of floating regfile reads -system.cpu.fp_regfile_writes 240711 # number of floating regfile writes -system.cpu.misc_regfile_reads 38028 # number of misc regfile reads +system.cpu.cpi 0.613497 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.613497 # CPI: Total CPI of All Threads +system.cpu.ipc 1.630000 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.630000 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115949669 # number of integer regfile reads +system.cpu.int_regfile_writes 57525330 # number of integer regfile writes +system.cpu.fp_regfile_reads 249508 # number of floating regfile reads +system.cpu.fp_regfile_writes 240213 # number of floating regfile writes +system.cpu.misc_regfile_reads 38023 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 92300 # number of replacements -system.cpu.icache.tagsinuse 1931.186939 # Cycle average of tags in use -system.cpu.icache.total_refs 14080520 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 94348 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 149.240259 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20259707000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1931.186939 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942962 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942962 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14080520 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14080520 # number of ReadReq hits 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-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007543 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007543 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007543 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007543 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007543 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007543 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16835.339292 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16835.339292 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16835.339292 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16835.339292 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16835.339292 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16835.339292 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 434 # number of cycles access was blocked +system.cpu.icache.replacements 91621 # number of replacements +system.cpu.icache.tagsinuse 1930.572235 # Cycle average of tags in use +system.cpu.icache.total_refs 13805106 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93669 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.381802 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19945764000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1930.572235 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942662 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942662 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13805106 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13805106 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13805106 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13805106 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13805106 # number of overall hits +system.cpu.icache.overall_hits::total 13805106 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105989 # number of overall misses +system.cpu.icache.overall_misses::total 105989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1780097998 # number of ReadReq miss cycles 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13911095 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007619 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007619 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007619 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007619 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007619 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007619 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16795.120229 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16795.120229 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16795.120229 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16795.120229 # average overall miss latency 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system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12665 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12665 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12665 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12665 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12665 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12665 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94349 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 94349 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 94349 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 94349 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 94349 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 94349 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1400064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1400064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1400064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1400064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1400064000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1400064000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006650 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006650 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006650 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14839.203383 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14839.203383 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14839.203383 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14839.203383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14839.203383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14839.203383 # average overall mshr miss latency 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accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006733 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006733 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14852.343333 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14852.343333 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14852.343333 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14852.343333 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14852.343333 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14852.343333 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201586 # number of replacements -system.cpu.dcache.tagsinuse 4077.128651 # Cycle average of tags in use -system.cpu.dcache.total_refs 34331018 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205682 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.913089 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 177489000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4077.128651 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995393 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995393 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20756846 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20756846 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574115 # number of WriteReq hits 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1306054 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306054 # number of overall misses -system.cpu.dcache.overall_misses::total 1306054 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12393965000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12393965000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 93492268598 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 93492268598 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105886233598 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105886233598 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105886233598 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105886233598 # number of overall miss cycles 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MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14350563397 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339509017 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14011054380 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14350563397 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081808 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448078 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.227926 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081808 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771657 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555740 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081808 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771657 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555740 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44304.974162 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45318.307966 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45099.693750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97468.021491 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97468.021491 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44304.974162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88311.458069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86283.886272 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44304.974162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88311.458069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86283.886272 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 201507 # number of replacements +system.cpu.dcache.tagsinuse 4077.368240 # Cycle average of tags in use +system.cpu.dcache.total_refs 34205521 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205603 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.366838 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 173993000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4077.368240 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995451 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995451 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20631452 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20631452 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574012 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34205464 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34205464 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34205464 # number of overall hits +system.cpu.dcache.overall_hits::total 34205464 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267045 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267045 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039365 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039365 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306410 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306410 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306410 # number of overall misses +system.cpu.dcache.overall_misses::total 1306410 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12450634000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12450634000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 93436551833 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 93436551833 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105887185833 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105887185833 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105887185833 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105887185833 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20898497 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20898497 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35511874 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35511874 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35511874 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35511874 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012778 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012778 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071124 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071124 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036788 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036788 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036788 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036788 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46623.730083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46623.730083 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89897.727779 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89897.727779 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81052.032542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81052.032542 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5486905 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112436 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.800251 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168957 # number of writebacks +system.cpu.dcache.writebacks::total 168957 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204872 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204872 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895935 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895935 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100807 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100807 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100807 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100807 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62173 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62173 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143430 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143430 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205603 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205603 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205603 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205603 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2029919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2029919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14640535990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14640535990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16670455490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16670455490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16670455490 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16670455490 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005790 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005790 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32649.534364 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32649.534364 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102074.433452 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102074.433452 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index b2095b317..889e8b1f0 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 726190563..dc0676551 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:57:39 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 20:20:38 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24260940500 because target called exit() +Exiting @ tick 26292466000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index bbe40238a..69c62381b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026781 # Number of seconds simulated -sim_ticks 26780535000 # Number of ticks simulated -final_tick 26780535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026292 # Number of seconds simulated +sim_ticks 26292466000 # Number of ticks simulated +final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149394 # Simulator instruction rate (inst/s) -host_op_rate 211994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56410244 # Simulator tick rate (ticks/s) -host_mem_usage 261852 # Number of bytes of host memory used -host_seconds 474.75 # Real time elapsed on the host -sim_insts 70924159 # Number of instructions simulated -sim_ops 100643406 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 300160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7944448 # Number of bytes read from this memory -system.physmem.bytes_read::total 8244608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 300160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 300160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372672 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372672 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4690 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124132 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128822 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83948 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83948 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11208141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296650086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307858226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11208141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11208141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200618546 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200618546 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200618546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11208141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296650086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 508476772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128823 # Total number of read requests seen -system.physmem.writeReqs 83948 # Total number of write requests seen -system.physmem.cpureqs 213079 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8244608 # Total number of bytes read from memory -system.physmem.bytesWritten 5372672 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8244608 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372672 # bytesWritten derated as per pkt->getSize() +host_inst_rate 115195 # Simulator instruction rate (inst/s) +host_op_rate 163465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42703788 # Simulator tick rate (ticks/s) +host_mem_usage 260928 # Number of bytes of host memory used +host_seconds 615.69 # Real time elapsed on the host +sim_insts 70925094 # Number of instructions simulated +sim_ops 100644341 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83943 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11350476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302110574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 313461050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11350476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11350476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 204330472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 204330472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 204330472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11350476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302110574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 517791522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128777 # Total number of read requests seen +system.physmem.writeReqs 83943 # Total number of write requests seen +system.physmem.cpureqs 213018 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8241664 # Total number of bytes read from memory +system.physmem.bytesWritten 5372352 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372352 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 308 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8046 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 298 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8167 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8037 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7891 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 7896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7927 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8032 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7950 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7992 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8024 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8177 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8153 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8060 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8008 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7981 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5174 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 7983 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5171 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5234 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5166 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5164 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5232 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5126 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5372 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26780515500 # Total gap between requests +system.physmem.totGap 26292446500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128823 # Categorize read packet sizes +system.physmem.readPktSize::6 128777 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 83948 # categorize write packet sizes +system.physmem.writePktSize::6 83943 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,14 +102,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 308 # categorize neither packet sizes +system.physmem.neitherpktsize::6 298 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 71083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,11 +138,11 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -154,44 +154,44 @@ system.physmem.wrQLenPdf::12 3650 # Wh system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4847041699 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6735959699 # Sum of mem lat for all requests -system.physmem.totBusLat 515280000 # Total cycles spent in databus access -system.physmem.totBankLat 1373638000 # Total cycles spent in bank access -system.physmem.avgQLat 37626.47 # Average queueing delay per request -system.physmem.avgBankLat 10663.24 # Average bank access latency per request +system.physmem.totQLat 4868161034 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6756433034 # Sum of mem lat for all requests +system.physmem.totBusLat 515096000 # Total cycles spent in databus access +system.physmem.totBankLat 1373176000 # Total cycles spent in bank access +system.physmem.avgQLat 37803.91 # Average queueing delay per request +system.physmem.avgBankLat 10663.46 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52289.70 # Average memory access latency -system.physmem.avgRdBW 307.86 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 200.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 307.86 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 200.62 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52467.37 # Average memory access latency +system.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 204.33 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.18 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.25 # Average read queue length over time -system.physmem.avgWrQLen 9.64 # Average write queue length over time -system.physmem.readRowHits 118946 # Number of row buffer hits during reads -system.physmem.writeRowHits 27105 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.29 # Row buffer hit rate for writes -system.physmem.avgGap 125865.44 # Average gap between requests +system.physmem.busUtil 3.24 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.26 # Average read queue length over time +system.physmem.avgWrQLen 9.45 # Average write queue length over time +system.physmem.readRowHits 118938 # Number of row buffer hits during reads +system.physmem.writeRowHits 27082 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.26 # Row buffer hit rate for writes +system.physmem.avgGap 123601.20 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,581 +235,455 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53561071 # number of cpu cycles simulated +system.cpu.numCycles 52584933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16989438 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12991194 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 680202 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11755292 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8009849 # Number of BTB hits +system.cpu.BPredUnit.lookups 16605622 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12744819 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 601134 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10608037 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7769778 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1851785 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114363 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12914479 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87008149 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16989438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9861634 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21655288 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2666634 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10515039 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 571 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11971869 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 198806 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47045662 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.589318 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.332778 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12549160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10606958 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11672224 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 180779 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46048900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.587178 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25412140 54.02% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2169507 4.61% 58.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2024864 4.30% 62.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2094897 4.45% 67.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1497374 3.18% 70.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1417625 3.01% 73.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 986770 2.10% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1225872 2.61% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10216613 21.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24897026 54.07% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1463280 3.18% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1379331 3.00% 73.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 959670 2.08% 75.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1190775 2.59% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10011040 21.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47045662 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317198 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.624466 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15025286 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8880734 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19918391 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1367786 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1853465 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3434521 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108932 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119105730 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 372945 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1853465 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16780714 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2530019 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 932679 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19483180 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5465605 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116933277 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14375 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4623545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 215 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117254635 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 538431443 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 538426294 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5149 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18095515 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25625 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25611 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12984960 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29963650 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22702028 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3806099 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4346835 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113028204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41641 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108286515 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 316116 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12256138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28707838 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4549 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47045662 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.301732 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.993875 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 46048900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8956467 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19461806 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3326611 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104659 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116720432 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 360894 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 926852 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19086495 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114852318 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115176508 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529186359 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529181674 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 16015892 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 24809 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29582757 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22430841 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3912004 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4391398 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111440700 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41006 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107204361 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269260 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46048900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11469393 24.38% 24.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8159881 17.34% 41.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7486298 15.91% 57.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7193710 15.29% 72.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5478307 11.64% 84.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3936871 8.37% 92.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1856294 3.95% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881703 1.87% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 583205 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10795987 23.44% 23.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5412181 11.75% 84.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3900032 8.47% 92.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1833850 3.98% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 869462 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 573509 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47045662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46048900 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112009 4.47% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1372514 54.80% 59.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1019865 40.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1351687 54.87% 59.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1001007 40.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57275495 52.89% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91732 0.08% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 181 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29138143 26.91% 79.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21780957 20.11% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56616683 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91709 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 161 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28875176 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21620625 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108286515 # Type of FU issued -system.cpu.iq.rate 2.021739 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2504390 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023127 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 266438684 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125354112 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106381358 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110790645 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2168801 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107204361 # Type of FU issued +system.cpu.iq.rate 2.038690 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263189734 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 696 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109667441 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2181528 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2653236 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7465 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30261 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2142984 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2272156 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6578 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29396 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1871610 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 473 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 28 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 493 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1853465 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1042007 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 44975 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113079657 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 348290 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29963650 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22702028 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25073 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6129 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5511 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30261 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 453510 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 204690 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 658200 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107104018 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28789803 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1182497 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1617500 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 290951 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6480 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5483 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29396 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 390184 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 182395 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 572579 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106179962 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28578383 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1024399 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9812 # number of nop insts executed -system.cpu.iew.exec_refs 50259028 # number of memory reference insts executed -system.cpu.iew.exec_branches 14733119 # Number of branches executed -system.cpu.iew.exec_stores 21469225 # Number of stores executed -system.cpu.iew.exec_rate 1.999662 # Inst execution rate -system.cpu.iew.wb_sent 106622925 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106381514 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53628948 # num instructions producing a value -system.cpu.iew.wb_consumers 104196549 # num instructions consuming a value +system.cpu.iew.exec_nop 9804 # number of nop insts executed +system.cpu.iew.exec_refs 49916161 # number of memory reference insts executed +system.cpu.iew.exec_branches 14598129 # Number of branches executed +system.cpu.iew.exec_stores 21337778 # Number of stores executed +system.cpu.iew.exec_rate 2.019209 # Inst execution rate +system.cpu.iew.wb_sent 105751543 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105534073 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53248858 # num instructions producing a value +system.cpu.iew.wb_consumers 103476528 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.986172 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514690 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006926 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514598 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12431579 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 573556 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45192198 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.227131 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.747743 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44431401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15976760 35.35% 35.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11724717 25.94% 61.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3516948 7.78% 69.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2892652 6.40% 75.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1888504 4.18% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1974510 4.37% 84.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692586 1.53% 85.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 573861 1.27% 86.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5951660 13.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15343377 34.53% 34.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1877627 4.23% 79.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1953879 4.40% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 688656 1.55% 85.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 567495 1.28% 86.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6007585 13.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45192198 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929711 # Number of instructions committed -system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 44431401 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70930646 # Number of instructions committed +system.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869458 # Number of memory references committed -system.cpu.commit.loads 27310414 # Number of loads committed +system.cpu.commit.refs 47869832 # Number of memory references committed +system.cpu.commit.loads 27310601 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13744811 # Number of branches committed +system.cpu.commit.branches 13744998 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486751 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5951660 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 152295776 # The number of ROB reads -system.cpu.rob.rob_writes 228025366 # The number of ROB writes -system.cpu.timesIdled 74466 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6515409 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924159 # Number of Instructions Simulated -system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated -system.cpu.cpi 0.755188 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.755188 # CPI: Total CPI of All Threads -system.cpu.ipc 1.324174 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.324174 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 515451838 # number of integer regfile reads -system.cpu.int_regfile_writes 104231541 # number of integer regfile writes -system.cpu.fp_regfile_reads 698 # number of floating regfile reads -system.cpu.fp_regfile_writes 610 # number of floating regfile writes -system.cpu.misc_regfile_reads 145512549 # number of misc regfile reads -system.cpu.misc_regfile_writes 38452 # number of misc regfile writes -system.cpu.icache.replacements 31300 # number of replacements -system.cpu.icache.tagsinuse 1822.220766 # Cycle average of tags in use -system.cpu.icache.total_refs 11934433 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 33335 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 358.015089 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 149890854 # The number of ROB reads +system.cpu.rob.rob_writes 224611140 # The number of ROB writes +system.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6536033 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70925094 # Number of Instructions Simulated +system.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70925094 # Number of Instructions Simulated +system.cpu.cpi 0.741415 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.741415 # CPI: Total CPI of All Threads +system.cpu.ipc 1.348772 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.348772 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511431338 # number of integer regfile reads +system.cpu.int_regfile_writes 103318196 # number of integer regfile writes +system.cpu.fp_regfile_reads 686 # number of floating regfile reads +system.cpu.fp_regfile_writes 582 # number of floating regfile writes +system.cpu.misc_regfile_reads 143076838 # number of misc regfile reads +system.cpu.misc_regfile_writes 38826 # number of misc regfile writes +system.cpu.icache.replacements 30543 # number of replacements +system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use +system.cpu.icache.total_refs 11635566 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1822.220766 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.889756 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.889756 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11934443 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11934443 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11934443 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11934443 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11934443 # number of overall hits -system.cpu.icache.overall_hits::total 11934443 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 37425 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 37425 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 37425 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 37425 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 37425 # number of overall misses -system.cpu.icache.overall_misses::total 37425 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 718344999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 718344999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 718344999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 718344999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 718344999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 718344999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11971868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11971868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11971868 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11971868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11971868 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11971868 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003126 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003126 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003126 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003126 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003126 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003126 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19194.255150 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19194.255150 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19194.255150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19194.255150 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1820.333452 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11635567 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11635567 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits +system.cpu.icache.overall_hits::total 11635567 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 36657 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 36657 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 36657 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 36657 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 36657 # number of overall misses +system.cpu.icache.overall_misses::total 36657 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 709011999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 709011999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 709011999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 709011999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 709011999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 709011999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11672224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11672224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11672224 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11672224 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11672224 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11672224 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003141 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003141 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003141 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003141 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003141 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003141 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19341.790081 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19341.790081 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19341.790081 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19341.790081 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.157895 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33651 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 33651 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 33651 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 33651 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 33651 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 33651 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 589350499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 589350499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 589350499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 589350499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 589350499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 589350499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002811 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002811 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002811 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17513.610264 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17513.610264 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32884 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32884 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32884 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32884 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32884 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32884 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580604499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 580604499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580604499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 580604499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580604499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 580604499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002817 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002817 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.139734 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.139734 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158507 # number of replacements -system.cpu.dcache.tagsinuse 4072.917720 # Cycle average of tags in use -system.cpu.dcache.total_refs 44563863 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162603 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.065442 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 285154000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.917720 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994365 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994365 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26258448 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26258448 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18265067 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18265067 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20455 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20455 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44523515 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44523515 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44523515 # number of overall hits -system.cpu.dcache.overall_hits::total 44523515 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125393 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125393 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1584834 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1584834 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1710227 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1710227 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1710227 # number of overall misses -system.cpu.dcache.overall_misses::total 1710227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4597179000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4597179000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 120104513482 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 120104513482 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 949000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 949000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 124701692482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 124701692482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 124701692482 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 124701692482 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26383841 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26383841 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20499 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20499 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46233742 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46233742 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46233742 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46233742 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036991 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036991 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036991 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036991 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36662.166150 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36662.166150 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75783.655248 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75783.655248 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21568.181818 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21568.181818 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72915.286966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72915.286966 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2506 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 608 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.418803 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129149 # number of writebacks -system.cpu.dcache.writebacks::total 129149 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69778 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69778 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477521 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1477521 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1547299 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1547299 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1547299 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1547299 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55615 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55615 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107313 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107313 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162928 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162928 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162928 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162928 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2039094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2039094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257233993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257233993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10296327993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10296327993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10296327993 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10296327993 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002108 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002108 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003524 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003524 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003524 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003524 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36664.461027 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36664.461027 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76945.328087 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76945.328087 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63195.571007 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63195.571007 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63195.571007 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63195.571007 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 95689 # number of replacements -system.cpu.l2cache.tagsinuse 30139.737825 # Cycle average of tags in use -system.cpu.l2cache.total_refs 90978 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 126809 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.717441 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 95650 # number of replacements +system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use +system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.709468 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26886.974949 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1383.020531 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1869.742346 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.820525 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.042206 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8421265207 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210181444 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8211083763 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8421265207 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394759 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.302265 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.940063 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.940063 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955360 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955360 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.661158 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.661158 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45064.632075 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63587.961751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.437163 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66707.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66707.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 158306 # number of replacements +system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use +system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits +system.cpu.dcache.overall_hits::total 44303188 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses +system.cpu.dcache.overall_misses::total 1709363 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks +system.cpu.dcache.writebacks::total 129052 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |