regressions: stats update due to decoder changes

1 files changed, 132 insertions, 132 deletions

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 69c62381b..0ed850d63 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.026292                       # Nu
 sim_ticks                                 26292466000                       # Number of ticks simulated
 final_tick                                26292466000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 115195                       # Simulator instruction rate (inst/s)
-host_op_rate                                   163465                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               42703788                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260928                       # Number of bytes of host memory used
-host_seconds                                   615.69                       # Real time elapsed on the host
+host_inst_rate                                 139577                       # Simulator instruction rate (inst/s)
+host_op_rate                                   198063                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               51742306                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305460                       # Number of bytes of host memory used
+host_seconds                                   508.14                       # Real time elapsed on the host
 sim_insts                                    70925094                       # Number of instructions simulated
 sim_ops                                     100644341                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            298432                       # Number of bytes read from this memory
@@ -503,7 +503,7 @@ system.cpu.int_regfile_reads                511431338                       # nu
 system.cpu.int_regfile_writes               103318196                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                       686                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                      582                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               143076838                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                49170129                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  38826                       # number of misc regfile writes
 system.cpu.icache.replacements                  30543                       # number of replacements
 system.cpu.icache.tagsinuse               1820.333452                       # Cycle average of tags in use
@@ -589,6 +589,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                 158306                       # number of replacements
+system.cpu.dcache.tagsinuse               4072.986675                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 44343623                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 162402                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 273.048503                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              280868000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4072.986675                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994382                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994382                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     26038019                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        26038019                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18265169                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18265169                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        20453                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        20453                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        19412                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        19412                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      44303188                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         44303188                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     44303188                       # number of overall hits
+system.cpu.dcache.overall_hits::total        44303188                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       124631                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        124631                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1584732                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1584732                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           40                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           40                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1709363                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1709363                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1709363                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1709363                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4670085000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4670085000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 120039172981                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       743000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       743000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 124709257981                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 124709257981                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 124709257981                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 124709257981                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     26162650                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     26162650                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        20493                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        20493                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        19412                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        19412                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     46012551                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     46012551                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     46012551                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     46012551                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004764                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004764                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079836                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.079836                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001952                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001952                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037150                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037150                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037150                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037150                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        18575                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        18575                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72956.568020                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72956.568020                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         4330                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          648                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               137                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              15                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.605839                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    43.200000                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       129052                       # number of writebacks
+system.cpu.dcache.writebacks::total            129052                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69229                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        69229                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1477415                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1477415                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           40                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           40                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1546644                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1546644                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1546644                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1546644                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55402                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        55402                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107317                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107317                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       162719                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       162719                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       162719                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       162719                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2060277500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2060277500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8253592492                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8253592492                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10313869992                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10313869992                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10313869992                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10313869992                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002118                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002118                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005406                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005406                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003536                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003536                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 95650                       # number of replacements
 system.cpu.l2cache.tagsinuse             30136.955692                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                   89930                       # Total number of references to valid blocks.
@@ -756,131 +882,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45064.632075
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 158306                       # number of replacements
-system.cpu.dcache.tagsinuse               4072.986675                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 44343623                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 162402                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 273.048503                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              280868000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4072.986675                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.994382                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.994382                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     26038019                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        26038019                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18265169                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18265169                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        20453                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        20453                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        19412                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        19412                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      44303188                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         44303188                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     44303188                       # number of overall hits
-system.cpu.dcache.overall_hits::total        44303188                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       124631                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        124631                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1584732                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1584732                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           40                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           40                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1709363                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1709363                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1709363                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1709363                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   4670085000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4670085000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 120039172981                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       743000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       743000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 124709257981                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 124709257981                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 124709257981                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 124709257981                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     26162650                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     26162650                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        20493                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        20493                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        19412                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        19412                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     46012551                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     46012551                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     46012551                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     46012551                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004764                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004764                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079836                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.079836                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001952                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001952                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037150                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037150                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037150                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037150                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        18575                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        18575                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72956.568020                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72956.568020                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         4330                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          648                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               137                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              15                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.605839                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    43.200000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       129052                       # number of writebacks
-system.cpu.dcache.writebacks::total            129052                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69229                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        69229                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1477415                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1477415                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           40                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           40                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1546644                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1546644                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1546644                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1546644                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55402                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        55402                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107317                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107317                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       162719                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       162719                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       162719                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       162719                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2060277500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2060277500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8253592492                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8253592492                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10313869992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  10313869992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10313869992                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10313869992                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002118                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002118                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005406                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005406                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003536                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003536                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------