diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
| commit | ebd9018a139178aed432b257ff4ce6dc2d5f795f (patch) | |
| tree | 0d844028751908a7c7f66f82e5bd9564467086c9 /tests/long/se/50.vortex | |
| parent | 9e57e4e89d3c6b6d7e0f0f182bfd01c5585c16c5 (diff) | |
| download | gem5-ebd9018a139178aed432b257ff4ce6dc2d5f795f.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/long/se/50.vortex')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt | 444 | ||||
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1763 |
2 files changed, 1103 insertions, 1104 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index d9533629f..35c099c69 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060131 # Number of seconds simulated -sim_ticks 60130734500 # Number of ticks simulated -final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060132 # Number of seconds simulated +sim_ticks 60131512500 # Number of ticks simulated +final_tick 60131512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 310652 # Simulator instruction rate (inst/s) -host_op_rate 397278 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 263409545 # Simulator tick rate (ticks/s) -host_mem_usage 281384 # Number of bytes of host memory used -host_seconds 228.28 # Real time elapsed on the host +host_inst_rate 320494 # Simulator instruction rate (inst/s) +host_op_rate 409865 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 271758284 # Simulator tick rate (ticks/s) +host_mem_usage 281048 # Number of bytes of host memory used +host_seconds 221.27 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory @@ -26,17 +26,17 @@ system.physmem.num_reads::cpu.data 124041 # Nu system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4761829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 132021026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136782856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4761829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4761829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92120217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92120217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92120217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4761829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 132021026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 228903073 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128515 # Number of read requests accepted system.physmem.writeReqs 86552 # Number of write requests accepted system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 5706 # Pe system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60130703000 # Total gap between requests +system.physmem.totGap 60131481000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -196,16 +196,16 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 258.799568 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.901911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8565 26.06% 26.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6426 19.55% 45.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3391 10.32% 55.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2471 7.52% 63.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1617 4.92% 75.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1341 4.08% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1209 3.68% 82.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes @@ -227,12 +227,12 @@ system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Wr system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads -system.physmem.totQLat 3048956750 # Total ticks spent queuing -system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3049168000 # Total ticks spent queuing +system.physmem.totMemAccLat 5458730500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst +system.physmem.avgQLat 23727.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 42477.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s @@ -247,62 +247,62 @@ system.physmem.readRowHits 112228 # Nu system.physmem.writeRowHits 69923 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes -system.physmem.avgGap 279590.56 # Average gap between requests +system.physmem.avgGap 279594.18 # Average gap between requests system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ) -system.physmem_0.averagePower 386.883743 # Core power per rank (mW) -system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states +system.physmem_0.refreshEnergy 2502199440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2202561510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 166933440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5874746040 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 2984525760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8651084625 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 23265974460 # Total energy per rank (pJ) +system.physmem_0.averagePower 386.918165 # Core power per rank (mW) +system.physmem_0.totalIdleTime 54864943500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 285874500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1063428000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34209724750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 7772192000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3916970750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12883322500 # Time in different power states system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ) -system.physmem_1.averagePower 383.200220 # Core power per rank (mW) -system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states +system.physmem_1.actBackEnergy 2186669910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 154102560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5325095040 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3204580800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8848579860 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23042291445 # Total energy per rank (pJ) +system.physmem_1.averagePower 383.198268 # Core power per rank (mW) +system.physmem_1.totalIdleTime 54933017000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 256278500 # Time in different power states system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.physmem_1.memoryStateTime::SREF 34910026000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8345277500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3889148250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 11677774250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 14827796 # Number of BP lookups system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 9662877 # Number of BTB lookups system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 68.011846 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720082 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -332,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -362,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -392,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -423,16 +423,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120261469 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120263025 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.695850 # CPI: cycles per instruction -system.cpu.ipc 0.589675 # IPC: instructions per cycle +system.cpu.cpi 1.695872 # CPI: cycles per instruction +system.cpu.ipc 0.589667 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -472,16 +472,16 @@ system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked -system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 98355658 # Number of cycles that the object actually ticked +system.cpu.idleCycles 21907367 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 156451 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4067.127626 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42637298 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.575177 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127626 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -489,11 +489,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 86034719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86034719 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22880155 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22880155 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits @@ -502,10 +502,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits -system.cpu.dcache.overall_hits::total 42605457 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 42522297 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42522297 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42605460 # number of overall hits +system.cpu.dcache.overall_hits::total 42605460 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses @@ -516,16 +516,16 @@ system.cpu.dcache.demand_misses::cpu.data 255005 # n system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses system.cpu.dcache.overall_misses::total 299788 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839905000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1839905000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545313000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18545313000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20385218000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20385218000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20385218000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20385218000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22927401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22927401 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses) @@ -534,10 +534,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42777302 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42777302 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42905248 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42905248 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses @@ -548,14 +548,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79940.463912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67998.779137 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -582,16 +582,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136566 system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773861500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 773861500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479489000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479489000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253350500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10253350500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12150126500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12150126500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -602,26 +602,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26206.830573 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26206.830573 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.730645 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.730645 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.950169 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.950169 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75079.818549 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75079.818549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75679.561125 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75679.561125 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 43545 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1851.999823 # Cycle average of tags in use system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1851.999823 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904297 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904297 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id @@ -631,7 +631,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits @@ -644,12 +644,12 @@ system.cpu.icache.demand_misses::cpu.inst 45588 # n system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses system.cpu.icache.overall_misses::total 45588 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042263500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1042263500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1042263500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1042263500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1042263500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1042263500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses @@ -662,12 +662,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.672194 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22862.672194 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22862.672194 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22862.672194 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,34 +682,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 45588 system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996683000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 996683000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996683000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 996683000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996683000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 996683000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996676500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 996676500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996676500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 996676500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996676500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 996676500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.694130 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.694130 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 97176 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31292.341702 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.063766 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 10980034000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 476.637646 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.081673 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 10980599000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 476.632754 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.083150 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.625798 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy @@ -723,7 +723,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits @@ -752,18 +752,18 @@ system.cpu.l2cache.demand_misses::total 128588 # nu system.cpu.l2cache.overall_misses::cpu.inst 4487 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses system.cpu.l2cache.overall_misses::total 128588 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269336000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9269336000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492869500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 492869500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2252818000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2252818000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 492869500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11522154000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12015023500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 492869500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9269327500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492863000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 492863000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2253034500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2253034500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 492863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11522362000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12015225000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 492863000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11522362000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12015225000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses) @@ -792,18 +792,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.623805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.207219 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.207219 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109842.433697 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109842.433697 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103426.115498 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103426.115498 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93439.706660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93439.706660 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -836,18 +836,18 @@ system.cpu.l2cache.demand_mshr_misses::total 128516 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246157500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246157500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446695500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029647000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029647000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446695500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275804500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10722500000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446695500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275804500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10722500000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses @@ -862,25 +862,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution @@ -920,7 +920,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 26198 # Transaction distribution system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution system.membus.trans_dist::CleanEvict 7237 # Transaction distribution @@ -943,9 +943,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 128515 # Request fanout histogram -system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 588249500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 677382500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index da2276c3c..ad340b529 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.037982 # Number of seconds simulated -sim_ticks 37982056000 # Number of ticks simulated -final_tick 37982056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.038007 # Number of seconds simulated +sim_ticks 38007342000 # Number of ticks simulated +final_tick 38007342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220867 # Simulator instruction rate (inst/s) -host_op_rate 282464 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118308818 # Simulator tick rate (ticks/s) -host_mem_usage 284316 # Number of bytes of host memory used -host_seconds 321.04 # Real time elapsed on the host +host_inst_rate 224949 # Simulator instruction rate (inst/s) +host_op_rate 287684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120575368 # Simulator tick rate (ticks/s) +host_mem_usage 283980 # Number of bytes of host memory used +host_seconds 315.22 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2372544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5696640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6178368 # Number of bytes read from this memory -system.physmem.bytes_read::total 14247552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2372544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2372544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6227072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6227072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 37071 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 89010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96537 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222618 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97298 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97298 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 62464865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 149982402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 162665444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 375112711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 62464865 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 62464865 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163947734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163947734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163947734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 62464865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 149982402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 162665444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 539060445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222619 # Number of read requests accepted -system.physmem.writeReqs 97298 # Number of write requests accepted -system.physmem.readBursts 222619 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97298 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14237568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue -system.physmem.bytesWritten 6225984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14247616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6227072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2373952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5705216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6169536 # Number of bytes read from this memory +system.physmem.bytes_read::total 14248704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2373952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2373952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6224192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6224192 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 37093 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 89144 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96399 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222636 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97253 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97253 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 62460353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 150108261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 162324848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 374893461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 62460353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 62460353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 163762886 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 163762886 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 163762886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 62460353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 150108261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 162324848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 538656347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222637 # Number of read requests accepted +system.physmem.writeReqs 97253 # Number of write requests accepted +system.physmem.readBursts 222637 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97253 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14240000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 6222848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14248768 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6224192 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9655 # Per bank write bursts -system.physmem.perBankRdBursts::1 9974 # Per bank write bursts -system.physmem.perBankRdBursts::2 12579 # Per bank write bursts -system.physmem.perBankRdBursts::3 25363 # Per bank write bursts -system.physmem.perBankRdBursts::4 17343 # Per bank write bursts -system.physmem.perBankRdBursts::5 22132 # Per bank write bursts -system.physmem.perBankRdBursts::6 11760 # Per bank write bursts -system.physmem.perBankRdBursts::7 14137 # Per bank write bursts -system.physmem.perBankRdBursts::8 11660 # Per bank write bursts -system.physmem.perBankRdBursts::9 15453 # Per bank write bursts -system.physmem.perBankRdBursts::10 11698 # Per bank write bursts -system.physmem.perBankRdBursts::11 11338 # Per bank write bursts -system.physmem.perBankRdBursts::12 9437 # Per bank write bursts -system.physmem.perBankRdBursts::13 9564 # Per bank write bursts -system.physmem.perBankRdBursts::14 9858 # Per bank write bursts -system.physmem.perBankRdBursts::15 20511 # Per bank write bursts -system.physmem.perBankWrBursts::0 5992 # Per bank write bursts -system.physmem.perBankWrBursts::1 6239 # Per bank write bursts -system.physmem.perBankWrBursts::2 6121 # Per bank write bursts -system.physmem.perBankWrBursts::3 6129 # Per bank write bursts -system.physmem.perBankWrBursts::4 6098 # Per bank write bursts -system.physmem.perBankWrBursts::5 6229 # Per bank write bursts -system.physmem.perBankWrBursts::6 6018 # Per bank write bursts -system.physmem.perBankWrBursts::7 5980 # Per bank write bursts -system.physmem.perBankWrBursts::8 5938 # Per bank write bursts -system.physmem.perBankWrBursts::9 6095 # Per bank write bursts -system.physmem.perBankWrBursts::10 6202 # Per bank write bursts -system.physmem.perBankWrBursts::11 5916 # Per bank write bursts -system.physmem.perBankWrBursts::12 6046 # Per bank write bursts -system.physmem.perBankWrBursts::13 6090 # Per bank write bursts -system.physmem.perBankWrBursts::14 6173 # Per bank write bursts -system.physmem.perBankWrBursts::15 6015 # Per bank write bursts +system.physmem.perBankRdBursts::0 9656 # Per bank write bursts +system.physmem.perBankRdBursts::1 9952 # Per bank write bursts +system.physmem.perBankRdBursts::2 12608 # Per bank write bursts +system.physmem.perBankRdBursts::3 25349 # Per bank write bursts +system.physmem.perBankRdBursts::4 17405 # Per bank write bursts +system.physmem.perBankRdBursts::5 22083 # Per bank write bursts +system.physmem.perBankRdBursts::6 11752 # Per bank write bursts +system.physmem.perBankRdBursts::7 14068 # Per bank write bursts +system.physmem.perBankRdBursts::8 11731 # Per bank write bursts +system.physmem.perBankRdBursts::9 15466 # Per bank write bursts +system.physmem.perBankRdBursts::10 11740 # Per bank write bursts +system.physmem.perBankRdBursts::11 11331 # Per bank write bursts +system.physmem.perBankRdBursts::12 9464 # Per bank write bursts +system.physmem.perBankRdBursts::13 9568 # Per bank write bursts +system.physmem.perBankRdBursts::14 9844 # Per bank write bursts +system.physmem.perBankRdBursts::15 20483 # Per bank write bursts +system.physmem.perBankWrBursts::0 5965 # Per bank write bursts +system.physmem.perBankWrBursts::1 6210 # Per bank write bursts +system.physmem.perBankWrBursts::2 6157 # Per bank write bursts +system.physmem.perBankWrBursts::3 6128 # Per bank write bursts +system.physmem.perBankWrBursts::4 6115 # Per bank write bursts +system.physmem.perBankWrBursts::5 6243 # Per bank write bursts +system.physmem.perBankWrBursts::6 6020 # Per bank write bursts +system.physmem.perBankWrBursts::7 5952 # Per bank write bursts +system.physmem.perBankWrBursts::8 5952 # Per bank write bursts +system.physmem.perBankWrBursts::9 6130 # Per bank write bursts +system.physmem.perBankWrBursts::10 6213 # Per bank write bursts +system.physmem.perBankWrBursts::11 5918 # Per bank write bursts +system.physmem.perBankWrBursts::12 6006 # Per bank write bursts +system.physmem.perBankWrBursts::13 6051 # Per bank write bursts +system.physmem.perBankWrBursts::14 6145 # Per bank write bursts +system.physmem.perBankWrBursts::15 6027 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37982044500 # Total gap between requests +system.physmem.totGap 38007330500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222619 # Read request sizes (log2) +system.physmem.readPktSize::6 222637 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97298 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 111989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5252 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97253 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 112108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59931 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 4622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,120 +198,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 132891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 153.980270 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.520664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 209.589027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 82855 62.35% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32511 24.46% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6209 4.67% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2728 2.05% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1195 0.90% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 994 0.75% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 885 0.67% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 776 0.58% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4738 3.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 132891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 132899 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 153.968593 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.497917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 209.528989 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82983 62.44% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32243 24.26% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6367 4.79% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2726 2.05% 93.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1184 0.89% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1005 0.76% 95.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 875 0.66% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 807 0.61% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4709 3.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132899 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.813870 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 211.295819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5876 99.88% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 6 0.10% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.820840 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 210.672420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5878 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.535951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.496117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.216118 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4707 80.01% 80.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 47 0.80% 80.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 703 11.95% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 205 3.48% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 109 1.85% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 61 1.04% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 33 0.56% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.19% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads -system.physmem.totQLat 8417974819 # Total ticks spent queuing -system.physmem.totMemAccLat 12589137319 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1112310000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37840.06 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56590.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 163.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 375.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 163.95 # Average system write bandwidth in MiByte/s +system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.528392 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.490234 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.186972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4697 79.85% 79.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 46 0.78% 80.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 744 12.65% 93.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 191 3.25% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 91 1.55% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 73 1.24% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.34% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 15 0.26% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads +system.physmem.totQLat 8329547257 # Total ticks spent queuing +system.physmem.totMemAccLat 12501422257 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1112500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37436.00 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.98 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 56185.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 163.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 374.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 163.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.21 # Data bus utilization in percentage system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing -system.physmem.readRowHits 157076 # Number of row buffer hits during reads -system.physmem.writeRowHits 29766 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes -system.physmem.avgGap 118724.68 # Average gap between requests +system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing +system.physmem.readRowHits 157173 # Number of row buffer hits during reads +system.physmem.writeRowHits 29653 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.64 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.49 # Row buffer hit rate for writes +system.physmem.avgGap 118813.75 # Average gap between requests system.physmem.pageHitRate 58.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 508332300 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 270162255 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 877813020 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 254767320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3007433520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2937544590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 74566560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13007568150 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1007588640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 71626485 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 22017862440 # Total energy per rank (pJ) -system.physmem_0.averagePower 579.691165 # Core power per rank (mW) -system.physmem_0.totalIdleTime 31344656336 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 41004063 # Time in different power states -system.physmem_0.memoryStateTime::REF 1272480000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 195565250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2624595348 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5323818601 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28524592738 # Time in different power states -system.physmem_1.actEnergy 440580840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 234159090 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 710558520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 253039500 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2889422640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2771748120 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 73304160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11932439280 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1384694400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 508589940 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 21198847170 # Total energy per rank (pJ) -system.physmem_1.averagePower 558.127949 # Core power per rank (mW) -system.physmem_1.totalIdleTime 31712588164 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 50452548 # Time in different power states -system.physmem_1.memoryStateTime::REF 1222746000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1938473750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3605935527 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4996269288 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26168178887 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17071043 # Number of BP lookups -system.cpu.branchPred.condPredicted 11458506 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 598065 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9277652 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7374059 # Number of BTB hits +system.physmem_0.actEnergy 507596880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 269771370 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 877313220 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 254683800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3009892080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2962459860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75632160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13054365150 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 948417120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 77983215 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 22038660255 # Total energy per rank (pJ) +system.physmem_0.averagePower 579.852702 # Core power per rank (mW) +system.physmem_0.totalIdleTime 31313307761 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 43781047 # Time in different power states +system.physmem_0.memoryStateTime::REF 1273526000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 214718250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2469720434 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5376727192 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28628869077 # Time in different power states +system.physmem_1.actEnergy 441337680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 234557565 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 711336780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 252841140 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2899256880.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2760551040 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 73978560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11934955830 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1428119040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 493845795 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 21231004530 # Total energy per rank (pJ) +system.physmem_1.averagePower 558.602674 # Core power per rank (mW) +system.physmem_1.totalIdleTime 31760586804 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 51273339 # Time in different power states +system.physmem_1.memoryStateTime::REF 1226918000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1868150750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3718457459 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4968563857 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26173978595 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17074531 # Number of BP lookups +system.cpu.branchPred.condPredicted 11460402 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 598628 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9274722 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7374340 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.481953 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1854771 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101571 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 233347 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 194967 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 38380 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22266 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 79.510092 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1855435 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101567 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 233050 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 195925 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37125 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22231 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +340,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -371,7 +370,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,7 +400,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -432,134 +431,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 75964113 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 76014685 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5537723 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87105546 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17071043 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9423797 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 66074321 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1222765 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 12043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 60 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 33616 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22433583 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69302 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 72269145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.523281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.330897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5565404 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87125388 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17074531 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9425700 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 66120510 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1223729 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 11256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 32224 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22440736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69274 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 72341306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.522198 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.331033 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27092588 37.49% 37.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8164913 11.30% 48.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9113637 12.61% 61.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27898007 38.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27150688 37.53% 37.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8169627 11.29% 48.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9114831 12.60% 61.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27906160 38.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 72269145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224725 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.146667 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8914938 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 26268747 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30971085 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5669704 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 444671 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3134143 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168562 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100303161 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2799230 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 444671 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13550474 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11467047 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 876029 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31784130 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14146794 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98330583 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 860090 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4210253 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 70388 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4670257 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5435231 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103259286 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453553071 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114279094 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 72341306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224621 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.146165 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8942287 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 26299816 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30976482 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5677371 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 445350 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3133946 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168438 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100318297 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2804928 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 445350 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13582767 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11480611 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 882043 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31792045 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14158490 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98346425 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 855389 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4229008 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 68182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4663621 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5443965 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103273055 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453619684 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114297516 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 686 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9629917 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18998 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19022 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12803731 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24155645 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21760500 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1435489 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2293932 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97400499 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34856 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94484787 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 595355 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6752748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17957034 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1070 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 72269145 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.307401 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.171287 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9643686 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18991 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19021 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12815345 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24159121 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21761593 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1442839 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2330212 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97411129 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34857 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94489103 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 595557 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6763379 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17995254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 72341306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.306157 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.170975 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24146655 33.41% 33.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17449315 24.14% 57.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17027031 23.56% 81.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11604628 16.06% 97.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2040054 2.82% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1462 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24199109 33.45% 33.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17470195 24.15% 57.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17034708 23.55% 81.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11601119 16.04% 97.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2034740 2.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1435 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 72269145 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 72341306 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6736684 22.63% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 37 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11088448 37.25% 59.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11940306 40.11% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 30 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6739464 22.68% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 40 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11065982 37.24% 59.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11909373 40.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 33 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49305598 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86530 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49308872 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86547 0.09% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued @@ -582,91 +581,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 11 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 13 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23958815 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21133689 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23960981 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21132544 22.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 62 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94484787 # Type of FU issued -system.cpu.iq.rate 1.243808 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29765526 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315030 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 291599265 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104199326 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93203450 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 335 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124250121 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 192 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1368397 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94489103 # Type of FU issued +system.cpu.iq.rate 1.243037 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29714913 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314480 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 291629642 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104220574 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93205627 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 544 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124203819 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 197 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1369166 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1289383 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2091 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1204762 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1292859 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2033 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11913 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1205855 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 147075 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 188044 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 148706 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 187344 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 444671 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 622988 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1195662 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97449431 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 445350 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 625818 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1199933 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97461708 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24155645 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21760500 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18936 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1589 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1191442 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 249986 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 222081 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 472067 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93691189 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23695668 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 793598 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24159121 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21761593 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18937 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1609 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1195657 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11913 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 250763 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 222991 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 473754 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93695211 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23697676 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 793892 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14076 # number of nop insts executed -system.cpu.iew.exec_refs 44621004 # number of memory reference insts executed -system.cpu.iew.exec_branches 14207535 # Number of branches executed -system.cpu.iew.exec_stores 20925336 # Number of stores executed -system.cpu.iew.exec_rate 1.233361 # Inst execution rate -system.cpu.iew.wb_sent 93310594 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93203542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44951761 # num instructions producing a value -system.cpu.iew.wb_consumers 76639550 # num instructions consuming a value -system.cpu.iew.wb_rate 1.226942 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586535 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5895620 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 15722 # number of nop insts executed +system.cpu.iew.exec_refs 44622526 # number of memory reference insts executed +system.cpu.iew.exec_branches 14207940 # Number of branches executed +system.cpu.iew.exec_stores 20924850 # Number of stores executed +system.cpu.iew.exec_rate 1.232594 # Inst execution rate +system.cpu.iew.wb_sent 93313259 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93205726 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44957522 # num instructions producing a value +system.cpu.iew.wb_consumers 76634731 # num instructions consuming a value +system.cpu.iew.wb_rate 1.226154 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586647 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5905401 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 431354 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 71312758 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.271696 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.107515 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 432114 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 71383083 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.270443 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.106463 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 37859507 53.09% 53.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16683603 23.39% 76.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4297164 6.03% 82.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4156384 5.83% 88.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1956005 2.74% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1240140 1.74% 92.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 732437 1.03% 93.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 578410 0.81% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3809108 5.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 37916370 53.12% 53.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16693361 23.39% 76.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4299601 6.02% 82.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4172974 5.85% 88.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1943479 2.72% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1233650 1.73% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 737671 1.03% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 579334 0.81% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3806643 5.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 71312758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 71383083 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -716,552 +715,552 @@ system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3809108 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 164062130 # The number of ROB reads -system.cpu.rob.rob_writes 194125448 # The number of ROB writes -system.cpu.timesIdled 54252 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3694968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3806643 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 164144701 # The number of ROB reads +system.cpu.rob.rob_writes 194146843 # The number of ROB writes +system.cpu.timesIdled 54077 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3673379 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.071311 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.071311 # CPI: Total CPI of All Threads -system.cpu.ipc 0.933436 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.933436 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 101982930 # number of integer regfile reads -system.cpu.int_regfile_writes 56612163 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 45 # number of floating regfile writes -system.cpu.cc_regfile_reads 345107562 # number of cc regfile reads -system.cpu.cc_regfile_writes 38759661 # number of cc regfile writes -system.cpu.misc_regfile_reads 44102170 # number of misc regfile reads +system.cpu.cpi 1.072024 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.072024 # CPI: Total CPI of All Threads +system.cpu.ipc 0.932815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.932815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101986551 # number of integer regfile reads +system.cpu.int_regfile_writes 56614441 # number of integer regfile writes +system.cpu.fp_regfile_reads 62 # number of floating regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 345121100 # number of cc regfile reads +system.cpu.cc_regfile_writes 38758964 # number of cc regfile writes +system.cpu.misc_regfile_reads 44102244 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 484814 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.868965 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40339815 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485326 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.119007 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 154595500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.868965 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484796 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.868688 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40338903 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485308 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.120210 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 154723500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.868688 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997790 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84466838 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84466838 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21417711 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21417711 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830642 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830642 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15309 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15309 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84466908 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84466908 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21416602 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21416602 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18830761 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18830761 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60264 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60264 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40248353 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40248353 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40308541 # number of overall hits -system.cpu.dcache.overall_hits::total 40308541 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 562442 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 562442 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019259 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019259 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68672 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68672 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 614 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 614 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1581701 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1581701 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1650373 # number of overall misses -system.cpu.dcache.overall_misses::total 1650373 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14412910000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14412910000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14258561428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14258561428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5705500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5705500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28671471428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28671471428 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28671471428 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28671471428 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21980153 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21980153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40247363 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40247363 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40307627 # number of overall hits +system.cpu.dcache.overall_hits::total 40307627 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 563583 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 563583 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1019140 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1019140 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68608 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68608 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 617 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 617 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1582723 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1582723 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1651331 # number of overall misses +system.cpu.dcache.overall_misses::total 1651331 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14467064000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14467064000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14294982430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14294982430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6393500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6393500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28762046430 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28762046430 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28762046430 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28762046430 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21980185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21980185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128860 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128860 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128872 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41830054 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41830054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41958914 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41958914 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025589 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025589 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051348 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051348 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532919 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532919 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038561 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038561 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037813 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037813 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039333 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.593395 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.593395 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13989.144494 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13989.144494 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9292.345277 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9292.345277 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18126.985712 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18126.985712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17372.722062 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17372.722062 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2956958 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131265 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.666667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.526629 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 484814 # number of writebacks -system.cpu.dcache.writebacks::total 484814 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263368 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 263368 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870698 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870698 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 614 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1134066 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1134066 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1134066 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1134066 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299074 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299074 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148561 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148561 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37704 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37704 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447635 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447635 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485339 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485339 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7124794500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7124794500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2343478471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2343478471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1981400500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1981400500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9468272971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9468272971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11449673471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11449673471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013607 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013607 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41830086 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41830086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41958958 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41958958 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025641 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025641 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051342 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051342 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532373 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532373 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038749 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038749 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037837 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037837 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039356 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039356 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25669.801964 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25669.801964 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14026.514934 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14026.514934 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10362.236629 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10362.236629 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18172.508032 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18172.508032 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17417.493180 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17417.493180 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2976739 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131356 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.661614 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484796 # number of writebacks +system.cpu.dcache.writebacks::total 484796 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 264511 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 264511 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870576 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870576 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 617 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 617 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1135087 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135087 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135087 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135087 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299072 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299072 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148564 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148564 # 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number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2001432500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9463416971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9463416971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11464849471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11464849471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013606 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013606 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292597 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292597 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292430 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292430 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010701 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010701 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011567 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.011567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23822.848191 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23822.848191 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15774.520036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15774.520036 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52551.466688 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52551.466688 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21151.770909 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21151.770909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23591.084728 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23591.084728 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325639 # number of replacements -system.cpu.icache.tags.tagsinuse 510.373274 # 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average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.878349 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53108.117073 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53108.117073 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21140.875557 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21140.875557 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23623.181045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23623.181045 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 325456 # number of replacements +system.cpu.icache.tags.tagsinuse 510.336563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22103277 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 325967 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.808327 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1174665500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.336563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996751 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996751 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 328 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45192862 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45192862 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22095836 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22095836 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22095836 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22095836 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22095836 # number of overall hits -system.cpu.icache.overall_hits::total 22095836 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 337513 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 337513 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 337513 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 337513 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 337513 # number of overall misses -system.cpu.icache.overall_misses::total 337513 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5817859355 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5817859355 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5817859355 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5817859355 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5817859355 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5817859355 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22433349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22433349 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22433349 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22433349 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22433349 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22433349 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015045 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015045 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015045 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015045 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015045 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17237.437832 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17237.437832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17237.437832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17237.437832 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 562602 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 332 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45207041 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45207041 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22103280 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22103280 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22103280 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22103280 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22103280 # number of overall hits +system.cpu.icache.overall_hits::total 22103280 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 337250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 337250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 337250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 337250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 337250 # number of overall misses +system.cpu.icache.overall_misses::total 337250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5803062852 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5803062852 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5803062852 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5803062852 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5803062852 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5803062852 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22440530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22440530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22440530 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22440530 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22440530 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22440530 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015029 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015029 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015029 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015029 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015029 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17207.006233 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17207.006233 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17207.006233 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17207.006233 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 559762 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26054 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25894 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.593690 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.617440 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325639 # number of writebacks -system.cpu.icache.writebacks::total 325639 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11348 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 11348 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 11348 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 11348 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 11348 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 11348 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326165 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 326165 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 326165 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 326165 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 326165 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 326165 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5383419413 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5383419413 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5383419413 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5383419413 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5383419413 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5383419413 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16505.202621 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16505.202621 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16505.202621 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.343365 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.953683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004538 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958221 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 24 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16299 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2543 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 510 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 881 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001648 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25499859 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25499859 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 257633 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85641.021833 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85641.021833 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.221585 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88283.519946 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87263.333514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.221585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88283.519946 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87263.333514 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 452 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 97298 # number of writebacks -system.cpu.l2cache.writebacks::total 97298 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3085 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3085 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 119 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 119 # 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number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8461 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8461 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37094 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37094 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80683 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80683 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 37094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 89144 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 126238 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 37094 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 89144 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 114995 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 241233 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10227090401 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10227090401 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 218000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 218000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 733523000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 733523000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2920395500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2920395500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6427576500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6427576500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2920395500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7161099500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10081495000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2920395500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7161099500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10227090401 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20308585401 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113665 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239570 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239570 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.155373 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056940 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056940 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113797 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239620 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239620 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.155604 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.297472 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89513.458694 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86665.467626 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86665.467626 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79075.285930 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79075.285930 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79569.145903 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79569.145903 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79893.339255 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84488.752411 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1621957 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 810494 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 18773 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18772 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 662893 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 354931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 552820 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 28222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 146565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 326165 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336729 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455492 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2433446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41714496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62088960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103803456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 272099 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6227968 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1083589 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091107 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.287765 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297350 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 88935.087621 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15571.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15571.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86694.598747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86694.598747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78729.592387 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78729.592387 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79664.569984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79664.569984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79861.016493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84186.597194 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1621556 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810285 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18616 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18570 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 46 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 662693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 357682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 549823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 146207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 325982 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336712 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977404 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455440 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2432844 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41691008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62086656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103777664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 271801 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6225152 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1083090 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091523 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288499 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 984867 90.89% 90.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98721 9.11% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 984008 90.85% 90.85% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 99036 9.14% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 46 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1083589 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1621431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1083090 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1621030000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489373744 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 489099244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728066857 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728047842 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 348152 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 205320 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 348230 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205331 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 214278 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97298 # Transaction distribution -system.membus.trans_dist::CleanEvict 28222 # Transaction distribution -system.membus.trans_dist::UpgradeReq 13 # Transaction distribution -system.membus.trans_dist::ReadExReq 8340 # Transaction distribution -system.membus.trans_dist::ReadExResp 8340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 214279 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 570770 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20474624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20474624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214175 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97253 # Transaction distribution +system.membus.trans_dist::CleanEvict 28326 # Transaction distribution +system.membus.trans_dist::UpgradeReq 14 # Transaction distribution +system.membus.trans_dist::ReadExReq 8461 # Transaction distribution +system.membus.trans_dist::ReadExResp 8461 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570866 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20472896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20472896 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 222632 # Request fanout histogram +system.membus.snoop_fanout::samples 222651 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222632 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222651 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222632 # Request fanout histogram -system.membus.reqLayer0.occupancy 835899979 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222651 # Request fanout histogram +system.membus.reqLayer0.occupancy 835869990 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1175524166 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1175713686 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |