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authorAli Saidi <Ali.Saidi@ARM.com>2012-06-29 11:19:03 -0400
committerAli Saidi <Ali.Saidi@ARM.com>2012-06-29 11:19:03 -0400
commit3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch)
tree63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing
parentaf2b14a362281f36347728e13dcd6b2c4d3c4991 (diff)
downloadgem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing')
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini2
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt670
3 files changed, 340 insertions, 340 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index 1fcd4f24c..4a4e79f41 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -191,7 +191,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 0482efbeb..74ab835bf 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 13:44:37
+gem5 compiled Jun 28 2012 22:05:18
+gem5 started Jun 28 2012 22:25:40
gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -23,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1009998808500 because target called exit()
+Exiting @ tick 991340143500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index 0ddfc2b1c..35d38838f 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.009999 # Number of seconds simulated
-sim_ticks 1009998808500 # Number of ticks simulated
-final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.991340 # Number of seconds simulated
+sim_ticks 991340143500 # Number of ticks simulated
+final_tick 991340143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 98665 # Simulator instruction rate (inst/s)
-host_op_rate 98665 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 54760444 # Simulator tick rate (ticks/s)
-host_mem_usage 215204 # Number of bytes of host memory used
-host_seconds 18443.95 # Real time elapsed on the host
+host_inst_rate 147354 # Simulator instruction rate (inst/s)
+host_op_rate 147354 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 80272080 # Simulator tick rate (ticks/s)
+host_mem_usage 218972 # Number of bytes of host memory used
+host_seconds 12349.75 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 172563072 # Number of bytes read from this memory
-system.physmem.bytes_read::total 172618048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 137579712 # Number of bytes read from this memory
+system.physmem.bytes_read::total 137634688 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 74938304 # Number of bytes written to this memory
-system.physmem.bytes_written::total 74938304 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2696298 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2697157 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1170911 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1170911 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 54432 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 170854728 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 170909160 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 54432 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 54432 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 74196428 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 74196428 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 74196428 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 54432 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 170854728 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 245105588 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 2149683 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2150542 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 55456 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 138781540 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 138836996 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 55456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 55456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 67691285 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 67691285 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 67691285 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 55456 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 138781540 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 206528281 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 444614444 # DTB read hits
+system.cpu.dtb.read_hits 444614343 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 449511522 # DTB read accesses
-system.cpu.dtb.write_hits 160920906 # DTB write hits
+system.cpu.dtb.read_accesses 449511421 # DTB read accesses
+system.cpu.dtb.write_hits 160920087 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 162622210 # DTB write accesses
-system.cpu.dtb.data_hits 605535350 # DTB hits
+system.cpu.dtb.write_accesses 162621391 # DTB write accesses
+system.cpu.dtb.data_hits 605534430 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 612133732 # DTB accesses
-system.cpu.itb.fetch_hits 231980230 # ITB hits
+system.cpu.dtb.data_accesses 612132812 # DTB accesses
+system.cpu.itb.fetch_hits 232194533 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 231980252 # ITB accesses
+system.cpu.itb.fetch_accesses 232194555 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 2019997618 # number of cpu cycles simulated
+system.cpu.numCycles 1982680288 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 232477361 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 138151285 # Number of BTB hits
+system.cpu.branch_predictor.lookups 328915928 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 253819011 # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 140072488 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 231593889 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 138169193 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 59.425694 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 175108073 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 153783039 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 1669728742 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct 59.660120 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 175201939 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 153713989 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 1669764044 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 3045931359 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses 3045966661 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 651109695 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 617989652 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 121368305 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 12075594 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 133443899 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 81756170 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 62.009227 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards 651015392 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 617989806 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 121318277 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 12155753 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 133474030 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 81726039 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 62.023228 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 1139614733 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 1746574278 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed.
-system.cpu.activity 78.063714 # Percentage of cycles cpu is active
+system.cpu.timesIdled 7486032 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 405569141 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 1577111147 # Number of cycles cpu stages are processed.
+system.cpu.activity 79.544400 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
@@ -114,144 +114,144 @@ system.cpu.committedInsts 1819780127 # Nu
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
-system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 1.089516 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 1.089516 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.917838 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 1087591326 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 932406292 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 46.158782 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 1046003601 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 973994017 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 48.217582 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 1610294122 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 409703496 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 20.282375 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 997062989 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 1022934629 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 50.640388 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 0.917838 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 791779407 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 1190900881 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 60.065200 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 1050371352 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 932308936 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 47.022656 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 1008674680 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 974005608 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 49.125702 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 1572973951 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 409706337 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 20.664266 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 959730175 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 1022950113 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 51.594305 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.tagsinuse 666.311000 # Cycle average of tags in use
-system.cpu.icache.total_refs 231979155 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 666.725255 # Cycle average of tags in use
+system.cpu.icache.total_refs 232193463 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 270057.223516 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 270306.708964 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 666.311000 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.325347 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.325347 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 231979155 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 231979155 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 231979155 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 231979155 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 231979155 # number of overall hits
-system.cpu.icache.overall_hits::total 231979155 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses
-system.cpu.icache.overall_misses::total 1072 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 58539000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 58539000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 58539000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 58539000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 58539000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 58539000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 231980227 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 231980227 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 231980227 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 231980227 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 666.725255 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.325549 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.325549 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 232193463 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 232193463 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 232193463 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 232193463 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 232193463 # number of overall hits
+system.cpu.icache.overall_hits::total 232193463 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1067 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1067 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1067 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1067 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1067 # number of overall misses
+system.cpu.icache.overall_misses::total 1067 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 58495000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 58495000 # number of ReadReq miss cycles
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.597095 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40112.619831 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40051.608045 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.861467 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40024.167616 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.241229 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40086.156385 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40086.156385 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------