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authorAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:33 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:33 -0600
commitf3585c841e964c98911784a187fc4f081a02a0a6 (patch)
tree2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf /tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing
parentcfc4a999828a5b51f4c514e3a7c47b4eebc450b9 (diff)
downloadgem5-f3585c841e964c98911784a187fc4f081a02a0a6.tar.xz
stats: update stats for cache occupancy and clock domain changes
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing')
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini9
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr1
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout8
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt36
4 files changed, 43 insertions, 11 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index cd7da392b..317ef3f76 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -120,6 +120,7 @@ mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
+sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
@@ -136,6 +137,7 @@ block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
+sequential_access=false
size=262144
[system.cpu.dtb]
@@ -158,6 +160,7 @@ mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
+sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
@@ -174,6 +177,7 @@ block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
+sequential_access=false
size=131072
[system.cpu.interrupts]
@@ -183,6 +187,7 @@ eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
@@ -204,6 +209,7 @@ mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
+sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
@@ -220,6 +226,7 @@ block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=20
+sequential_access=false
size=2097152
[system.cpu.toL2Bus]
@@ -246,7 +253,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
index 1b49765a7..506aa6e28 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
@@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 037bfdea9..45898c91d 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:05:17
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:29:41
+gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1017016979500 because target called exit()
+Exiting @ tick 1009838214500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index 864d4a591..01fe4f841 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds 1.009838 # Nu
sim_ticks 1009838214500 # Number of ticks simulated
final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 87394 # Simulator instruction rate (inst/s)
-host_op_rate 87394 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48496748 # Simulator tick rate (ticks/s)
-host_mem_usage 275936 # Number of bytes of host memory used
-host_seconds 20822.81 # Real time elapsed on the host
+host_inst_rate 128161 # Simulator instruction rate (inst/s)
+host_op_rate 128161 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 71119760 # Simulator tick rate (ticks/s)
+host_mem_usage 230508 # Number of bytes of host memory used
+host_seconds 14199.12 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory
system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory
@@ -325,6 +327,7 @@ system.membus.reqLayer0.occupancy 11785228500 # La
system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 18364778000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 326538257 # Number of BP lookups
system.cpu.branchPred.condPredicted 252572868 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect
@@ -436,6 +439,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 858 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 785 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.418945 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 463858599 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 463858599 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 231927731 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 231927731 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 231927731 # number of demand (read+write) hits
@@ -544,6 +553,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.455687
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001058 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.486850 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.943594 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 29793 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 613 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 725 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12815 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15482 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909210 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 106291061 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 106291061 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.data 6044291 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6044291 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3693280 # number of Writeback hits
@@ -675,6 +693,14 @@ system.cpu.dcache.tags.warmup_cycle 12709353000 # Cy
system.cpu.dcache.tags.occ_blocks::cpu.data 4082.357931 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.996669 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 590 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 2876 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 593 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1219759777 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1219759777 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 156014425 # number of WriteReq hits