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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-16 10:44:12 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-16 10:44:12 -0400 |
| commit | 10e64501206b72901c266855fde2909523b875e0 (patch) | |
| tree | df5db553cf78ff00467b4ca87614a5721439b2ec /tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout | |
| parent | b10ff075b102b2a2e4abf5d22735b919a8fda1a9 (diff) | |
| download | gem5-10e64501206b72901c266855fde2909523b875e0.tar.xz | |
test: update stats
Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout')
| -rwxr-xr-x | tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index a9e5ff044..3d7fe8a25 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,10 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:05:25 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 15 2013 19:07:40 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second |