diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 1612 |
1 files changed, 790 insertions, 822 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 09d12ecba..2f4d3475f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.685387 # Number of seconds simulated -sim_ticks 685386545000 # Number of ticks simulated -final_tick 685386545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.682192 # Number of seconds simulated +sim_ticks 682191807000 # Number of ticks simulated +final_tick 682191807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166100 # Simulator instruction rate (inst/s) -host_op_rate 166100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65575812 # Simulator tick rate (ticks/s) -host_mem_usage 231660 # Number of bytes of host memory used -host_seconds 10451.82 # Real time elapsed on the host +host_inst_rate 139307 # Simulator instruction rate (inst/s) +host_op_rate 139307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54741914 # Simulator tick rate (ticks/s) +host_mem_usage 268504 # Number of bytes of host memory used +host_seconds 12461.96 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125792064 # Number of bytes read from this memory -system.physmem.bytes_read::total 125853824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65263104 # Number of bytes written to this memory -system.physmem.bytes_written::total 65263104 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965501 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966466 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019736 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019736 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 183534481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 183624591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90110 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90110 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 95220871 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 95220871 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 95220871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 183534481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 278845462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966466 # Number of read requests accepted -system.physmem.writeReqs 1019736 # Number of write requests accepted -system.physmem.readBursts 1966466 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1019736 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125817344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36480 # Total number of bytes read from write queue -system.physmem.bytesWritten 65263104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125853824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65263104 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 570 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125800064 # Number of bytes read from this memory +system.physmem.bytes_read::total 125861760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265984 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 964 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965626 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966590 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019781 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019781 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 184405709 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 184496147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95671017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95671017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95671017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 184405709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 280167164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966590 # Number of read requests accepted +system.physmem.writeReqs 1019781 # Number of write requests accepted +system.physmem.readBursts 1966590 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1019781 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125780416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue +system.physmem.bytesWritten 65264896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125861760 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65265984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119017 # Per bank write bursts -system.physmem.perBankRdBursts::1 114428 # Per bank write bursts -system.physmem.perBankRdBursts::2 116569 # Per bank write bursts -system.physmem.perBankRdBursts::3 118023 # Per bank write bursts -system.physmem.perBankRdBursts::4 118127 # Per bank write bursts -system.physmem.perBankRdBursts::5 117816 # Per bank write bursts -system.physmem.perBankRdBursts::6 120202 # Per bank write bursts -system.physmem.perBankRdBursts::7 124913 # Per bank write bursts -system.physmem.perBankRdBursts::8 127544 # Per bank write bursts -system.physmem.perBankRdBursts::9 130446 # Per bank write bursts -system.physmem.perBankRdBursts::10 129104 # Per bank write bursts -system.physmem.perBankRdBursts::11 130773 # Per bank write bursts -system.physmem.perBankRdBursts::12 126663 # Per bank write bursts -system.physmem.perBankRdBursts::13 125636 # Per bank write bursts -system.physmem.perBankRdBursts::14 122981 # Per bank write bursts -system.physmem.perBankRdBursts::15 123654 # Per bank write bursts -system.physmem.perBankWrBursts::0 61274 # Per bank write bursts -system.physmem.perBankWrBursts::1 61571 # Per bank write bursts -system.physmem.perBankWrBursts::2 60654 # Per bank write bursts -system.physmem.perBankWrBursts::3 61312 # Per bank write bursts -system.physmem.perBankWrBursts::4 61747 # Per bank write bursts -system.physmem.perBankWrBursts::5 63190 # Per bank write bursts -system.physmem.perBankWrBursts::6 64213 # Per bank write bursts -system.physmem.perBankWrBursts::7 65700 # Per bank write bursts -system.physmem.perBankWrBursts::8 65483 # Per bank write bursts -system.physmem.perBankWrBursts::9 65878 # Per bank write bursts -system.physmem.perBankWrBursts::10 65419 # Per bank write bursts -system.physmem.perBankWrBursts::11 65720 # Per bank write bursts -system.physmem.perBankWrBursts::12 64327 # Per bank write bursts -system.physmem.perBankWrBursts::13 64305 # Per bank write bursts -system.physmem.perBankWrBursts::14 64649 # Per bank write bursts -system.physmem.perBankWrBursts::15 64294 # Per bank write bursts +system.physmem.perBankRdBursts::0 118991 # Per bank write bursts +system.physmem.perBankRdBursts::1 114394 # Per bank write bursts +system.physmem.perBankRdBursts::2 116519 # Per bank write bursts +system.physmem.perBankRdBursts::3 118029 # Per bank write bursts +system.physmem.perBankRdBursts::4 118142 # Per bank write bursts +system.physmem.perBankRdBursts::5 117777 # Per bank write bursts +system.physmem.perBankRdBursts::6 120156 # Per bank write bursts +system.physmem.perBankRdBursts::7 124892 # Per bank write bursts +system.physmem.perBankRdBursts::8 127514 # Per bank write bursts +system.physmem.perBankRdBursts::9 130376 # Per bank write bursts +system.physmem.perBankRdBursts::10 129025 # Per bank write bursts +system.physmem.perBankRdBursts::11 130742 # Per bank write bursts +system.physmem.perBankRdBursts::12 126628 # Per bank write bursts +system.physmem.perBankRdBursts::13 125605 # Per bank write bursts +system.physmem.perBankRdBursts::14 122932 # Per bank write bursts +system.physmem.perBankRdBursts::15 123597 # Per bank write bursts +system.physmem.perBankWrBursts::0 61284 # Per bank write bursts +system.physmem.perBankWrBursts::1 61572 # Per bank write bursts +system.physmem.perBankWrBursts::2 60658 # Per bank write bursts +system.physmem.perBankWrBursts::3 61323 # Per bank write bursts +system.physmem.perBankWrBursts::4 61765 # Per bank write bursts +system.physmem.perBankWrBursts::5 63192 # Per bank write bursts +system.physmem.perBankWrBursts::6 64214 # Per bank write bursts +system.physmem.perBankWrBursts::7 65706 # Per bank write bursts +system.physmem.perBankWrBursts::8 65482 # Per bank write bursts +system.physmem.perBankWrBursts::9 65855 # Per bank write bursts +system.physmem.perBankWrBursts::10 65405 # Per bank write bursts +system.physmem.perBankWrBursts::11 65740 # Per bank write bursts +system.physmem.perBankWrBursts::12 64329 # Per bank write bursts +system.physmem.perBankWrBursts::13 64310 # Per bank write bursts +system.physmem.perBankWrBursts::14 64647 # Per bank write bursts +system.physmem.perBankWrBursts::15 64282 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 685386422500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 682191684500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1966466 # Read request sizes (log2) +system.physmem.readPktSize::6 1966590 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1019736 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1645035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 231982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019781 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1642976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 230548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,235 +129,203 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 46127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 49473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 48655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1821867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.857955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.098310 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 197.882118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1460616 80.17% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 186071 10.21% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 71892 3.95% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32365 1.78% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16766 0.92% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10653 0.58% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7007 0.38% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6870 0.38% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3886 0.21% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3166 0.17% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2723 0.15% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1980 0.11% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1594 0.09% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1502 0.08% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1242 0.07% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1240 0.07% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1003 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1017 0.06% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 831 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 807 0.04% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 751 0.04% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2873 0.16% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 389 0.02% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 742 0.04% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 289 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 237 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 196 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 198 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 161 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 132 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 165 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 370 0.02% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 134 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 101 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 73 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 67 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 51 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 72 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 49 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 40 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 35 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 42 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 34 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 27 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 45 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 32 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 23 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 19 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 35 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 9 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 10 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 20 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 11 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 24 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 22 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 8 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 26 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 4 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 11 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 22 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 17 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 89 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 28 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 123 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1821867 # Bytes accessed per row activation -system.physmem.totQLat 24443368500 # Total ticks spent queuing -system.physmem.totMemAccLat 84807426000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9829480000 # Total ticks spent in databus transfers -system.physmem.totBankLat 50534577500 # Total ticks spent accessing banks -system.physmem.avgQLat 12433.70 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 25705.62 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 31804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 54150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 57221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 64812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 65271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 65616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 73465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 64939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 17452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1251998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 113.111439 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 84.586325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 150.844327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 955672 76.33% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 201584 16.10% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38062 3.04% 95.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 16101 1.29% 96.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9606 0.77% 97.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4835 0.39% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3234 0.26% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2576 0.21% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20328 1.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1251998 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 58888 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.373692 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.339848 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 58850 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 58888 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 58888 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.317009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.233410 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.918536 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 34047 57.82% 57.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 20086 34.11% 91.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 4266 7.24% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 290 0.49% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 84 0.14% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 30 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 14 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 5 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 4 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 12 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 19 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 9 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::78-79 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::86-87 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-89 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-105 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::106-107 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 58888 # Writes before turning the bus around for reads +system.physmem.totQLat 20653307250 # Total ticks spent queuing +system.physmem.totMemAccLat 80037239750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9826595000 # Total ticks spent in databus transfers +system.physmem.totBankLat 49557337500 # Total ticks spent accessing banks +system.physmem.avgQLat 10508.88 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 25215.93 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43139.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 183.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 95.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 183.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 95.22 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40724.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 184.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 184.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.18 # Data bus utilization in percentage -system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing -system.physmem.readRowHits 819101 # Number of row buffer hits during reads -system.physmem.writeRowHits 344664 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes -system.physmem.avgGap 229517.77 # Average gap between requests -system.physmem.pageHitRate 38.98 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 7.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 278845462 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191273 # Transaction distribution -system.membus.trans_dist::ReadResp 1191273 # Transaction distribution -system.membus.trans_dist::Writeback 1019736 # Transaction distribution -system.membus.trans_dist::ReadExReq 775193 # Transaction distribution -system.membus.trans_dist::ReadExResp 775193 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4952668 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191116928 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191116928 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191116928 # Total data (bytes) +system.physmem.busUtil 2.19 # Data bus utilization in percentage +system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.29 # Average write queue length when enqueuing +system.physmem.readRowHits 797879 # Number of row buffer hits during reads +system.physmem.writeRowHits 422825 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.46 # Row buffer hit rate for writes +system.physmem.avgGap 228435.01 # Average gap between requests +system.physmem.pageHitRate 40.89 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 7.23 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 280167164 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191439 # Transaction distribution +system.membus.trans_dist::ReadResp 1191439 # Transaction distribution +system.membus.trans_dist::Writeback 1019781 # Transaction distribution +system.membus.trans_dist::ReadExReq 775151 # Transaction distribution +system.membus.trans_dist::ReadExResp 775151 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4952961 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191127744 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191127744 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191127744 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11873404000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11872683000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18493738500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18474077250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 381642976 # Number of BP lookups -system.cpu.branchPred.condPredicted 296606399 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16082111 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262443817 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259723367 # Number of BTB hits +system.cpu.branchPred.lookups 381618384 # Number of BP lookups +system.cpu.branchPred.condPredicted 296575373 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16092188 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262164042 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259697812 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.963416 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24699577 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3003 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.059280 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24705469 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3069 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613972689 # DTB read hits -system.cpu.dtb.read_misses 11257711 # DTB read misses +system.cpu.dtb.read_hits 613976008 # DTB read hits +system.cpu.dtb.read_misses 11261750 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625230400 # DTB read accesses -system.cpu.dtb.write_hits 212364531 # DTB write hits -system.cpu.dtb.write_misses 7123508 # DTB write misses +system.cpu.dtb.read_accesses 625237758 # DTB read accesses +system.cpu.dtb.write_hits 212363538 # DTB write hits +system.cpu.dtb.write_misses 7134748 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219488039 # DTB write accesses -system.cpu.dtb.data_hits 826337220 # DTB hits -system.cpu.dtb.data_misses 18381219 # DTB misses +system.cpu.dtb.write_accesses 219498286 # DTB write accesses +system.cpu.dtb.data_hits 826339546 # DTB hits +system.cpu.dtb.data_misses 18396498 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844718439 # DTB accesses -system.cpu.itb.fetch_hits 391054896 # ITB hits -system.cpu.itb.fetch_misses 42 # ITB misses +system.cpu.dtb.data_accesses 844736044 # DTB accesses +system.cpu.itb.fetch_hits 391110222 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391054938 # ITB accesses +system.cpu.itb.fetch_accesses 391110266 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -371,138 +339,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1370773091 # number of cpu cycles simulated +system.cpu.numCycles 1364383615 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402523002 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3161115412 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381642976 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284422944 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574525052 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140645567 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 190952168 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1444 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 391054896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8064214 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1284797805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.460399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.144459 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402585287 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3161125101 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381618384 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284403281 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574536383 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140665925 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 188120516 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1448 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 391110222 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8062763 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1282059246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.465662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.145744 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 710272753 55.28% 55.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42667609 3.32% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21782496 1.70% 60.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39699327 3.09% 63.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129330544 10.07% 73.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61540269 4.79% 78.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38580495 3.00% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28116157 2.19% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212808155 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 707522863 55.19% 55.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42675531 3.33% 58.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21787283 1.70% 60.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39707555 3.10% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129310443 10.09% 73.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61549431 4.80% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38571496 3.01% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28142716 2.20% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212791928 16.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1284797805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.278414 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.306082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434521910 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 172167391 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542471492 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18841651 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116795361 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58349498 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 879 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3088463521 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116795361 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457475867 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116907635 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7798 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535572514 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 58038630 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3006337354 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 608843 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1808950 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51752219 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2247576032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3898866654 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3898722180 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 144473 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1282059246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.279700 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.316889 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434597074 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 169317553 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542454813 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18875119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116814687 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58354170 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 898 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3088496267 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2037 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116814687 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457547940 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 113953082 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6967 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535589228 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 58147342 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3006454755 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 609106 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1833248 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51828481 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2247677853 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3898974365 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3898830865 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 143499 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 871373069 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 157 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 156 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123546719 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679659315 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255464076 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67507479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36716823 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2724801247 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509489521 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3207288 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 979575578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 416138423 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1284797805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.953217 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971436 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 871474890 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 178 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 177 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123676155 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679702242 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255475560 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67614908 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37053481 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2724914461 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 131 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509610552 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3196332 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979670705 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416123894 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1282059246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.957484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971278 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 442944970 34.48% 34.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203642722 15.85% 50.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185470521 14.44% 64.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153370563 11.94% 76.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133097213 10.36% 87.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80758631 6.29% 93.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65098641 5.07% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15296137 1.19% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5118407 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 440049739 34.32% 34.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203670606 15.89% 50.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185671301 14.48% 64.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153363283 11.96% 76.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133052268 10.38% 87.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80767651 6.30% 93.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65047769 5.07% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15319478 1.19% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5117151 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1284797805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1282059246 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2193136 11.83% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11923525 64.32% 76.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4420966 23.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2188252 11.81% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11925862 64.39% 76.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4407339 23.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643778581 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643881644 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 99 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 160 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 33 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 265 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 161 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 23 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued @@ -524,84 +493,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641602507 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224107818 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641614566 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224113754 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509489521 # Type of FU issued -system.cpu.iq.rate 1.830711 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18537627 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007387 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6323623582 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3703265011 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413078875 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1898180 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1217876 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850894 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527088869 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 938279 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62595515 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509610552 # Type of FU issued +system.cpu.iq.rate 1.839373 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18521453 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007380 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6321098058 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3703474382 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413201675 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1900077 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1218284 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 852187 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527192648 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 939357 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62588107 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235063652 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 262733 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107683 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94735574 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235106579 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263309 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 109146 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94747058 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 113 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1541249 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 184 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1530387 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116795361 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 56591518 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1298088 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2866959659 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8943399 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679659315 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255464076 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 282702 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18018 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107683 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10360004 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8558145 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18918149 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462143246 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625230973 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47346275 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116814687 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 54760955 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1302145 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2867095326 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8936600 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679702242 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255475560 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 285836 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18373 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 109146 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10363389 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8561306 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18924695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462265598 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625238282 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47344954 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142158292 # number of nop insts executed -system.cpu.iew.exec_refs 844719037 # number of memory reference insts executed -system.cpu.iew.exec_branches 300873221 # Number of branches executed -system.cpu.iew.exec_stores 219488064 # Number of stores executed -system.cpu.iew.exec_rate 1.796171 # Inst execution rate -system.cpu.iew.wb_sent 2441862108 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413929769 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388272639 # num instructions producing a value -system.cpu.iew.wb_consumers 1764258225 # num instructions consuming a value +system.cpu.iew.exec_nop 142180734 # number of nop insts executed +system.cpu.iew.exec_refs 844736593 # number of memory reference insts executed +system.cpu.iew.exec_branches 300891924 # Number of branches executed +system.cpu.iew.exec_stores 219498311 # Number of stores executed +system.cpu.iew.exec_rate 1.804673 # Inst execution rate +system.cpu.iew.wb_sent 2442007403 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2414053862 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388335082 # num instructions producing a value +system.cpu.iew.wb_consumers 1764294016 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.760999 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786887 # average fanout of values written-back +system.cpu.iew.wb_rate 1.769337 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 826504574 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 826637792 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16081360 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1168002444 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.558028 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.499439 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16091391 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1165244559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.561715 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.500982 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 654033697 56.00% 56.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174911016 14.98% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86140681 7.38% 78.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53576194 4.59% 82.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34697975 2.97% 85.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25994339 2.23% 88.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21604457 1.85% 89.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22883851 1.96% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94160234 8.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 651170378 55.88% 55.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175014835 15.02% 70.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86149099 7.39% 78.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53527990 4.59% 82.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34710349 2.98% 85.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26102733 2.24% 88.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21568948 1.85% 89.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22887442 1.96% 91.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94112785 8.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1168002444 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1165244559 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -612,225 +581,224 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94160234 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94112785 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3634347710 # The number of ROB reads -system.cpu.rob.rob_writes 5409463480 # The number of ROB writes -system.cpu.timesIdled 947782 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 85975286 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3631770492 # The number of ROB reads +system.cpu.rob.rob_writes 5409749589 # The number of ROB writes +system.cpu.timesIdled 953701 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 82324369 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.789596 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.789596 # CPI: Total CPI of All Threads -system.cpu.ipc 1.266471 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.266471 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318031256 # number of integer regfile reads -system.cpu.int_regfile_writes 1931984794 # number of integer regfile writes -system.cpu.fp_regfile_reads 30556 # number of floating regfile reads -system.cpu.fp_regfile_writes 536 # number of floating regfile writes +system.cpu.cpi 0.785915 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.785915 # CPI: Total CPI of All Threads +system.cpu.ipc 1.272402 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.272402 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318200326 # number of integer regfile reads +system.cpu.int_regfile_writes 1932098427 # number of integer regfile writes +system.cpu.fp_regfile_reads 30699 # number of floating regfile reads +system.cpu.fp_regfile_writes 520 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1205179048 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883628 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085762 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22087692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825951744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 826013504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 826013504 # Total data (bytes) +system.cpu.toL2Bus.throughput 1210780745 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3724768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883565 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1928 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22087254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825923008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 825984704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 825984704 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178550909 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10177843430 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1610000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1605500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14084464250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14065476499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 773.100738 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391053395 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 405236.678756 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 773.695817 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391108717 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 964 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 405714.436722 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 773.100738 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 782110757 # Number of tag accesses -system.cpu.icache.tags.data_accesses 782110757 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 391053395 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391053395 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391053395 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391053395 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391053395 # number of overall hits -system.cpu.icache.overall_hits::total 391053395 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1501 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1501 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1501 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1501 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1501 # number of overall misses -system.cpu.icache.overall_misses::total 1501 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 108152500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 108152500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 108152500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 108152500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 108152500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 108152500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391054896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391054896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391054896 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391054896 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391054896 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391054896 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 773.695817 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 963 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.470215 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 782221404 # Number of tag accesses +system.cpu.icache.tags.data_accesses 782221404 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 391108717 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391108717 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391108717 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391108717 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391108717 # number of overall hits +system.cpu.icache.overall_hits::total 391108717 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1503 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1503 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1503 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1503 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1503 # number of overall misses +system.cpu.icache.overall_misses::total 1503 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108284500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108284500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108284500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108284500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108284500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108284500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391110220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391110220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391110220 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391110220 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391110220 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391110220 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72053.630913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72053.630913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72053.630913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72053.630913 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 156 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72045.575516 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72045.575516 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72045.575516 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72045.575516 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72045.575516 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72045.575516 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 78 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75095000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75095000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75095000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75095000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75095000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75095000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 539 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 539 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 539 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 539 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 539 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 539 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 964 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 964 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 964 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 964 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 964 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75722000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75722000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75722000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75722000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75722000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75722000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77818.652850 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77818.652850 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77818.652850 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77818.652850 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77818.652850 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77818.652850 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78549.792531 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78549.792531 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78549.792531 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78549.792531 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78549.792531 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78549.792531 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1933762 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31423.393947 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9058762 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1963540 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.613485 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28354220250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14586.517425 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.834239 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.042284 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.445145 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958966 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29778 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 1933885 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31421.269549 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9058254 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1963664 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.612935 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28359986250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14571.956791 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.815575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.497182 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.444701 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000818 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.513382 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958901 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29779 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 978 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17297 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10763 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908752 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107098856 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107098856 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6106330 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106330 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3725230 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3725230 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108435 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108435 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214765 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214765 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214765 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214765 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190308 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191273 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775193 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775193 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 965 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965501 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966466 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 965 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965501 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966466 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74125000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 102633894750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 102708019750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67309627250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 67309627250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 74125000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169943522000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 170017647000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 74125000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169943522000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 170017647000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296638 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297603 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3725230 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3725230 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883628 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883628 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181231 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181231 # number of overall (read+write) accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 974 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 593 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17299 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10767 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86463.208108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86458.472712 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76813.471503 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86463.208108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86458.472712 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214114 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214196 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77543.568465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83921.683992 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83916.523423 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84086.378009 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84086.378009 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77543.568465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83986.631613 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83983.473296 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77543.568465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83986.631613 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83983.473296 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,188 +807,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965501 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966466 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 61971000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 87692417750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 87754388750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57554177250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57554177250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61971000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145246595000 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62625000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140427779250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 140490404250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62625000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140427779250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 140490404250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163131 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163242 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411543 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163263 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411534 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411534 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214101 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214183 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214114 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214196 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214101 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214183 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64218.652850 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73672.039296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73664.381506 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74244.965125 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74244.965125 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64218.652850 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73898.001069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73893.251142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64218.652850 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73898.001069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73893.251142 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214114 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214196 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64963.692946 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71386.027216 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71380.830869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71527.352090 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71527.352090 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64963.692946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71441.759139 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71438.583665 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64963.692946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71441.759139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71438.583665 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9176170 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.561673 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694256138 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9180266 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 75.624839 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9176183 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.522150 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694277633 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180279 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.627073 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5178034250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.561673 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997940 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997940 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.522150 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997930 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 690 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2994 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 705 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2966 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1430860164 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1430860164 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 538716411 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538716411 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155539725 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155539725 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694256136 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694256136 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694256136 # number of overall hits -system.cpu.dcache.overall_hits::total 694256136 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11395033 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11395033 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5188777 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5188777 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1430905565 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1430905565 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 538740047 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538740047 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155537583 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155537583 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694277630 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694277630 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694277630 # number of overall hits +system.cpu.dcache.overall_hits::total 694277630 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11394090 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11394090 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5190919 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5190919 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16583810 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16583810 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16583810 # number of overall misses -system.cpu.dcache.overall_misses::total 16583810 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 343354515500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 343354515500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 296317441834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 296317441834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 639671957334 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 639671957334 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 639671957334 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 639671957334 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550111444 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550111444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16585009 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16585009 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16585009 # number of overall misses +system.cpu.dcache.overall_misses::total 16585009 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 335805939499 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 335805939499 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289123962439 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289123962439 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 201500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 201500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 624929901938 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 624929901938 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 624929901938 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 624929901938 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550134137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550134137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710839946 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710839946 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710839946 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710839946 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020714 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020714 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032283 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032283 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023330 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023330 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30131.945691 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30131.945691 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57107.376523 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57107.376523 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38572.074652 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38572.074652 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12375504 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8646342 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 745563 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710862639 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710862639 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710862639 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710862639 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020711 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020711 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032296 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032296 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023331 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023331 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29471.940234 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 29471.940234 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55698.030048 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55698.030048 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 201500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 201500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37680.407767 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37680.407767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37680.407767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37680.407767 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11880802 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8587513 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 745209 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.598871 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.744945 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.942913 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 131.841759 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725230 # number of writebacks -system.cpu.dcache.writebacks::total 3725230 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4098384 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4098384 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305161 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3305161 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7403545 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7403545 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7403545 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7403545 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296649 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296649 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883616 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883616 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3724768 # number of writebacks +system.cpu.dcache.writebacks::total 3724768 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4097367 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4097367 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307364 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3307364 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7404731 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7404731 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7404731 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7404731 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296723 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296723 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180265 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180265 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180265 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180265 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171833895250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171833895250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80710616128 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 80710616128 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 89750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 89750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252544511378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 252544511378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252544511378 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 252544511378 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180278 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180278 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180278 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180278 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 169103281751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 169103281751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78582140948 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 78582140948 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 247685422699 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 247685422699 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 247685422699 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 247685422699 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23549.700040 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23549.700040 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42848.763298 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42848.763298 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012914 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012914 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23175.236576 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23175.236576 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41720.120171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41720.120171 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 199500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 199500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26980.165818 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26980.165818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26980.165818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26980.165818 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |