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author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
commit | f3585c841e964c98911784a187fc4f081a02a0a6 (patch) | |
tree | 2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf /tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing | |
parent | cfc4a999828a5b51f4c514e3a7c47b4eebc450b9 (diff) | |
download | gem5-f3585c841e964c98911784a187fc4f081a02a0a6.tar.xz |
stats: update stats for cache occupancy and clock domain changes
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing')
4 files changed, 44 insertions, 13 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 3e178e75c..20db05a32 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,6 +533,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -550,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -566,6 +572,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -592,7 +599,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 3d7fe8a25..b7f8b903e 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 15 2013 19:07:40 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:30:51 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 694171131000 because target called exit() +Exiting @ tick 685386545000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 29e4de429..09d12ecba 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.685387 # Nu sim_ticks 685386545000 # Number of ticks simulated final_tick 685386545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111182 # Simulator instruction rate (inst/s) -host_op_rate 111182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43894428 # Simulator tick rate (ticks/s) -host_mem_usage 276060 # Number of bytes of host memory used -host_seconds 15614.43 # Real time elapsed on the host +host_inst_rate 166100 # Simulator instruction rate (inst/s) +host_op_rate 166100 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65575812 # Simulator tick rate (ticks/s) +host_mem_usage 231660 # Number of bytes of host memory used +host_seconds 10451.82 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125792064 # Number of bytes read from this memory system.physmem.bytes_read::total 125853824 # Number of bytes read from this memory @@ -326,6 +328,7 @@ system.membus.reqLayer0.occupancy 11873404000 # La system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) system.membus.respLayer1.occupancy 18493738500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 381642976 # Number of BP lookups system.cpu.branchPred.condPredicted 296606399 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 16082111 # Number of conditional branches incorrect @@ -657,6 +660,13 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 773.100738 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.377491 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.377491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 782110757 # Number of tag accesses +system.cpu.icache.tags.data_accesses 782110757 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 391053395 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 391053395 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 391053395 # number of demand (read+write) hits @@ -745,6 +755,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.445145 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.513002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.958966 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29778 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 978 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17297 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10763 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908752 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 107098856 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107098856 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.data 6106330 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6106330 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3725230 # number of Writeback hits @@ -876,6 +895,14 @@ system.cpu.dcache.tags.warmup_cycle 5178034250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4087.561673 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997940 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997940 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 690 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2994 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1430860164 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1430860164 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 538716411 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 538716411 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 155539725 # number of WriteReq hits |