diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt | |
parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt')
-rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 4fe8387b5..72597a7eb 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 5246772452 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.458646 # Cycle average of tags in use -system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926937 # number of replacements -system.cpu.l2cache.tagsinuse 30535.257456 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8959453 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1956729 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.578791 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926937 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits @@ -318,15 +318,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use -system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9107638 # number of replacements +system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits |