Stats: Update stats for new default L1-to-L2 bus clock and width

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

1 files changed, 139 insertions, 139 deletions

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 15b5a360c..78e7b43f1 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.642008                       # Number of seconds simulated
-sim_ticks                                2642007987000                       # Number of ticks simulated
-final_tick                               2642007987000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.631385                       # Number of seconds simulated
+sim_ticks                                2631384990000                       # Number of ticks simulated
+final_tick                               2631384990000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1913242                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1913242                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2777698581                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217920                       # Number of bytes of host memory used
-host_seconds                                   951.15                       # Real time elapsed on the host
+host_inst_rate                                1011793                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1011793                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1463043658                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219388                       # Number of bytes of host memory used
+host_seconds                                  1798.57                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             51328                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data            2149692                       # Nu
 system.physmem.num_reads::total               2150494                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1048525                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1048525                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                19428                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             52074138                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52093565                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           19428                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              19428                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          25399469                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               25399469                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          25399469                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               19428                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            52074138                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               77493034                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                19506                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             52284363                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52303869                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           19506                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              19506                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          25502008                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               25502008                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          25502008                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               19506                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            52284363                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               77805877                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -67,7 +67,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       5284015974                       # number of cpu cycles simulated
+system.cpu.numCycles                       5262769980                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1819780127                       # Number of instructions committed
@@ -86,18 +86,18 @@ system.cpu.num_mem_refs                     611922547                       # nu
 system.cpu.num_load_insts                   449492741                       # Number of load instructions
 system.cpu.num_store_insts                  162429806                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 5284015974                       # Number of busy cycles
+system.cpu.num_busy_cycles                 5262769980                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.tagsinuse                612.519467                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                612.470356                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1826377708                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    802                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               2277278.937656                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     612.519467                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.299082                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.299082                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     612.470356                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.299058                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.299058                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1826377708                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1826377708                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1826377708                       # number of demand (read+write) hits
@@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst          802                       # n
 system.cpu.icache.demand_misses::total            802                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          802                       # number of overall misses
 system.cpu.icache.overall_misses::total           802                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     45149000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     45149000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     45149000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     45149000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     45149000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     45149000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     44120000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     44120000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     44120000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     44120000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     44120000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     44120000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1826378510                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1826378510                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1826378510                       # number of demand (read+write) accesses
@@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56295.511222                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56295.511222                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56295.511222                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56295.511222                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56295.511222                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56295.511222                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55012.468828                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55012.468828                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55012.468828                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55012.468828                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55012.468828                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55012.468828                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          802
 system.cpu.icache.demand_mshr_misses::total          802                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          802                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42743000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     42743000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42743000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     42743000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42743000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     42743000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42516000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     42516000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     42516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42516000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     42516000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53295.511222                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53295.511222                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53295.511222                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53295.511222                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53295.511222                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53295.511222                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53012.468828                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53012.468828                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53012.468828                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53012.468828                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53012.468828                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53012.468828                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9107638                       # number of replacements
-system.cpu.dcache.tagsinuse               4079.366966                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4079.313701                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                596212431                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                9111734                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  65.433476                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            40989979000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4079.366966                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.995939                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.995939                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle            40977019000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4079.313701                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995926                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995926                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    437373249                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       437373249                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    158839182                       # number of WriteReq hits
@@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data      9111734                       # n
 system.cpu.dcache.demand_misses::total        9111734                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9111734                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9111734                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 158759423000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 158759423000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  59584620000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  59584620000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 218344043000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 218344043000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 218344043000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 218344043000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 151059345000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 151059345000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  57691387000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  57691387000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 208750732000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 208750732000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 208750732000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 208750732000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
@@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.015053
 system.cpu.dcache.demand_miss_rate::total     0.015053                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015053                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015053                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21981.490261                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21981.490261                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31537.600830                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31537.600830                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23962.951838                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23962.951838                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23962.951838                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23962.951838                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20915.353925                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20915.353925                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30535.529714                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30535.529714                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22910.099439                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22910.099439                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22910.099439                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22910.099439                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9111734
 system.cpu.dcache.demand_mshr_misses::total      9111734                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9111734                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9111734                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137092181000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 137092181000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53916660000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  53916660000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191008841000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 191008841000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191008841000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 191008841000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136614517000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 136614517000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53912747000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53912747000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190527264000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 190527264000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190527264000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 190527264000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011755                       # mshr miss rate for WriteReq accesses
@@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015053
 system.cpu.dcache.demand_mshr_miss_rate::total     0.015053                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015053                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.015053                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18981.490261                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18981.490261                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28537.600830                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28537.600830                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20962.951838                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20962.951838                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20962.951838                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20962.951838                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18915.353925                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18915.353925                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.529714                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.529714                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20910.099439                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20910.099439                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20910.099439                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20910.099439                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2133721                       # number of replacements
-system.cpu.l2cache.tagsinuse             30166.534681                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             30159.988647                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 8449191                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               2163414                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  3.905490                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          498438853000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14372.614424                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     37.649566                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  15756.270691                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.438617                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.001149                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.480843                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.920610                       # Average percentage of cache occupancy
+system.cpu.l2cache.warmup_cycle          496965874000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14375.657027                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     37.778500                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  15746.553119                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.438710                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001153                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.480547                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.920410                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.data      5861531                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        5861531                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3389919                       # number of Writeback hits
@@ -301,17 +301,17 @@ system.cpu.l2cache.demand_misses::total       2150494                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          802                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data      2149692                       # number of overall misses
 system.cpu.l2cache.overall_misses::total      2150494                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     41704000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  70765916000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  70807620000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41018068000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  41018068000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     41704000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 111783984000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 111825688000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     41704000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 111783984000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 111825688000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     41714000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  70776793000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  70818507000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41018317000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  41018317000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     41714000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 111795110000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 111836824000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     41714000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 111795110000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 111836824000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          802                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data      7222414                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total      7223216                       # number of ReadReq accesses(hits+misses)
@@ -336,17 +336,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.235993                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.235926                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.235993                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52012.468828                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.992605                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52007.995241                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.315666                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.315666                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52012.468828                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.175625                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52005.178345                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52012.468828                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.175625                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52005.178345                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -368,17 +368,17 @@ system.cpu.l2cache.demand_mshr_misses::total      2150494
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data      2149692                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total      2150494                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     32080000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  54435320000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  54467400000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31552360000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31552360000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     32080000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  85987680000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  86019760000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     32080000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  85987680000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  86019760000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     32090000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  54446197000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  54478287000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31552609000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31552609000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     32090000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  85998806000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  86030896000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     32090000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  85998806000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  86030896000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.188425                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.188515                       # mshr miss rate for ReadReq accesses
@@ -390,17 +390,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.235993
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.235926                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.235993                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40012.468828                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.992605                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40007.995241                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.315666                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.315666                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40012.468828                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.175625                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.178345                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40012.468828                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.175625                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.178345                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------