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authorAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:36 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:36 -0400
commitb63631536d974f31cf99ee280271dc0f7b4c746f (patch)
treeff83820d8dd75de8238e4b7ddaf3b91e4cf8374f /tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
parent646c4a23ca44aab5468c896034288151c89be782 (diff)
downloadgem5-b63631536d974f31cf99ee280271dc0f7b4c746f.tar.xz
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt')
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt84
1 files changed, 42 insertions, 42 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 72597a7eb..27c712d4a 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu
sim_ticks 2623386226000 # Number of ticks simulated
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 781919 # Simulator instruction rate (inst/s)
-host_op_rate 781919 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1127211275 # Simulator tick rate (ticks/s)
-host_mem_usage 225028 # Number of bytes of host memory used
-host_seconds 2327.32 # Real time elapsed on the host
+host_inst_rate 1731328 # Simulator instruction rate (inst/s)
+host_op_rate 1731328 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2495874089 # Simulator tick rate (ticks/s)
+host_mem_usage 225024 # Number of bytes of host memory used
+host_seconds 1051.09 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
@@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp 1178362 # Tr
system.membus.trans_dist::Writeback 1018077 # Transaction distribution
system.membus.trans_dist::ReadExReq 781301 # Transaction distribution
system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 4937403 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 4937403 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575360 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 190575360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 190575360 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks)
@@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 5246772452 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.tags.replacements 1 # number of replacements
-system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 1 # number of replacements
+system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
@@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 1926937 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements 1926937 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits
@@ -318,15 +318,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 9107638 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 9107638 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
@@ -424,12 +424,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Tr
system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1604 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916965 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 21918569 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51328 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819534784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 819586112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks)