diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-11-17 04:54:14 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-11-17 04:54:14 -0500 |
| commit | 6ed567d6002df081dd6cf2db6685d3e66c11272b (patch) | |
| tree | d6df4c0abaf10391c9ca9fb9dfc833737c979e37 /tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing | |
| parent | 74249f80df4e6128da38dfb5dbf5f61285c673a2 (diff) | |
| download | gem5-6ed567d6002df081dd6cf2db6685d3e66c11272b.tar.xz | |
alpha: Remove ALPHA tru64 support and associated tests
No one appears to be using it, and it is causing build issues
and increases the development and maintenance effort.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing')
4 files changed, 0 insertions, 967 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index b0859ad68..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 96524c915..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index eae87e351..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4312 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 2636719559500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index 6af37cfb2..000000000 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,566 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.639614 # Number of seconds simulated -sim_ticks 2639613874500 # Number of ticks simulated -final_tick 2639613874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2013574 # Simulator instruction rate (inst/s) -host_op_rate 2013574 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2920714569 # Simulator tick rate (ticks/s) -host_mem_usage 253500 # Number of bytes of host memory used -host_seconds 903.76 # Real time elapsed on the host -sim_insts 1819780127 # Number of instructions simulated -sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126106432 # Number of bytes read from this memory -system.physmem.bytes_read::total 126157760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66087296 # Number of bytes written to this memory -system.physmem.bytes_written::total 66087296 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1970413 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1971215 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1032614 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1032614 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47774575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47794021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25036729 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25036729 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25036729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47774575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72830749 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444595663 # DTB read hits -system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.write_hits 160728502 # DTB write hits -system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.data_hits 605324165 # DTB hits -system.cpu.dtb.data_misses 6598382 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 611922547 # DTB accesses -system.cpu.itb.fetch_hits 1826378510 # ITB hits -system.cpu.itb.fetch_misses 18 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1826378528 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5279227749 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1819780127 # Number of instructions committed -system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses -system.cpu.num_func_calls 33534877 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls -system.cpu.num_int_insts 1725565901 # number of integer instructions -system.cpu.num_fp_insts 805526 # number of float instructions -system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read -system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written -system.cpu.num_fp_register_reads 357 # number of times the floating registers were read -system.cpu.num_fp_register_writes 345 # number of times the floating registers were written -system.cpu.num_mem_refs 611922547 # number of memory refs -system.cpu.num_load_insts 449492741 # Number of load instructions -system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5279227749 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 214632552 # Number of branches fetched -system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction -system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction -system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction -system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction -system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1826378509 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.303630 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41048093500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.303630 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2646 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits -system.cpu.dcache.overall_hits::total 596212431 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses -system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152711735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152711735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64261460000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64261460000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 216973195000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 216973195000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 216973195000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 216973195000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21144.140311 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21144.140311 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34013.009972 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34013.009972 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23812.503196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23812.503196 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3664823 # number of writebacks -system.cpu.dcache.writebacks::total 3664823 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145489321000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 145489321000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62372140000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 62372140000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207861461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 207861461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207861461000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 207861461000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20144.140311 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20144.140311 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33013.009972 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33013.009972 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.633318 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.633318 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.299137 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.299137 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses -system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1826377708 # number of overall hits -system.cpu.icache.overall_hits::total 1826377708 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses -system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50541500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50541500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50541500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50541500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50541500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50541500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63019.326683 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63019.326683 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63019.326683 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63019.326683 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49739500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49739500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49739500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49739500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49739500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49739500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62019.326683 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62019.326683 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1938767 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31260.683710 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16248398 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1971535 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.241496 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 217871689000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8.109026 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.419408 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31214.155276 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000247 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001172 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.952580 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.954000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 664 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27794 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147732935 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147732935 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3664823 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3664823 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095314 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095314 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046007 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6046007 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7141321 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7141321 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7141321 # number of overall hits -system.cpu.l2cache.overall_hits::total 7141321 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 794006 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 794006 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 802 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 802 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176407 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1176407 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1970413 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1971215 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1970413 # number of overall misses -system.cpu.l2cache.overall_misses::total 1971215 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48037363000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 48037363000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48529000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 48529000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71172626500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 71172626500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 48529000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 119209989500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 119258518500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 48529000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 119209989500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 119258518500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3664823 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3664823 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222414 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7222414 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111734 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420260 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.420260 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162883 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162883 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216250 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216319 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216250 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216319 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60509.975062 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60509.975062 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.002550 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.002550 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60509.975062 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.001523 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.005580 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60509.975062 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.001523 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.005580 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1032614 # number of writebacks -system.cpu.l2cache.writebacks::total 1032614 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 794006 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 794006 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 802 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176407 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176407 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1970413 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1971215 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1970413 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1971215 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40097303000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40097303000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40509000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40509000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59408556500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59408556500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40509000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99505859500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 99546368500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40509000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99505859500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 99546368500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420260 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420260 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162883 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162883 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216319 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216319 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50509.975062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50509.975062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.002550 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.002550 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1292 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1292 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4697437 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6348968 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 817699648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 817751040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1938767 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66087296 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11051303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000117 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010812 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11050011 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1292 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11051303 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12774911500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3908932 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1937717 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1177209 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1032614 # Transaction distribution -system.membus.trans_dist::CleanEvict 905103 # Transaction distribution -system.membus.trans_dist::ReadExReq 794006 # Transaction distribution -system.membus.trans_dist::ReadExResp 794006 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1177209 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5880147 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5880147 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192245056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192245056 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1971215 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1971215 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1971215 # Request fanout histogram -system.membus.reqLayer0.occupancy 8039396000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9856075000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |