diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing')
3 files changed, 256 insertions, 181 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index b74c06509..70d2dba0c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout index 5e40861f7..91c7dc82f 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:52:43 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:35:09 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 99a911858..52ac717c2 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.663444 # Nu sim_ticks 2663443716000 # Number of ticks simulated final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1948044 # Simulator instruction rate (inst/s) -host_tick_rate 2851171142 # Simulator tick rate (ticks/s) -host_mem_usage 207608 # Number of bytes of host memory used -host_seconds 934.16 # Real time elapsed on the host +host_inst_rate 2433308 # Simulator instruction rate (inst/s) +host_op_rate 2433308 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3561407770 # Simulator tick rate (ticks/s) +host_mem_usage 209524 # Number of bytes of host memory used +host_seconds 747.86 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated +sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172614208 # Number of bytes read from this memory system.physmem.bytes_inst_read 51328 # Number of instructions bytes read from this memory system.physmem.bytes_written 74939072 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 29 # Nu system.cpu.numCycles 5326887432 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 1819780127 # Number of instructions executed +system.cpu.committedInsts 1819780127 # Number of instructions committed +system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses system.cpu.num_func_calls 33534877 # number of times a function call or return occured @@ -79,26 +82,39 @@ system.cpu.icache.total_refs 1826377708 # To system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits -system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1826377708 # number of overall hits -system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.demand_misses 802 # number of demand (read+write) misses -system.cpu.icache.overall_misses 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 612.356766 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.299002 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.299002 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1826377708 # number of overall hits +system.cpu.icache.overall_hits::total 1826377708 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses +system.cpu.icache.overall_misses::total 802 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44912000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44912000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44912000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44912000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44912000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44912000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42506000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42506000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42506000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42506000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use @@ -134,32 +148,49 @@ system.cpu.dcache.total_refs 596212431 # To system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995973 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits -system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 596212431 # number of overall hits -system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses -system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 177010400000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63798266000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 240808666000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 240808666000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 26428.412638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4079.504248 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995973 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995973 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits +system.cpu.dcache.overall_hits::total 596212431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses +system.cpu.dcache.overall_misses::total 9111734 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177010400000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177010400000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63798266000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63798266000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 240808666000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 240808666000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 240808666000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 240808666000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24508.481513 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33767.845574 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3058802 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 58130306000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 213473464000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 213473464000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 3058802 # number of writebacks +system.cpu.dcache.writebacks::total 3058802 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155343158000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 155343158000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58130306000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58130306000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213473464000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 213473464000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213473464000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 213473464000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21508.481513 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30767.845574 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2686269 # number of replacements system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use @@ -199,36 +232,72 @@ system.cpu.l2cache.total_refs 7565346 # To system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5415352 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3058802 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 1000087 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6415439 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6415439 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1807864 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 889233 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2697097 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2697097 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 94008928000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 46240116000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 140249044000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 140249044000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3058802 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.250285 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.470663 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.295977 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.295977 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 10727.578894 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 29.806952 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15282.701350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.327380 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000910 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.466391 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.794680 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5415352 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5415352 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3058802 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3058802 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1000087 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1000087 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6415439 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6415439 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6415439 # number of overall hits +system.cpu.l2cache.overall_hits::total 6415439 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1807062 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1807864 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 889233 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 889233 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2696295 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2697097 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2696295 # number of overall misses +system.cpu.l2cache.overall_misses::total 2697097 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41704000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 93967224000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94008928000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46240116000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46240116000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41704000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 140207340000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 140249044000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41704000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 140207340000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 140249044000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3058802 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3058802 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111734 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112536 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250202 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470663 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.295915 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.295915 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,30 +306,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1170923 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1807864 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 889233 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2697097 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2697097 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72314560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 107883880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 107883880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250285 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470663 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.295977 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.295977 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 1170923 # number of writebacks +system.cpu.l2cache.writebacks::total 1170923 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807062 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1807864 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889233 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 889233 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2696295 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2697097 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2696295 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2697097 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72282480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72314560000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35569320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35569320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107851800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 107883880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107851800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 107883880000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250202 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470663 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |