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authorAndreas Hansson <andreas.hansson@arm.com>2015-07-03 10:15:03 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-07-03 10:15:03 -0400
commit25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch)
tree36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se/60.bzip2/ref/alpha/tru64
parent7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff)
downloadgem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64')
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt1032
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt1512
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt500
3 files changed, 1552 insertions, 1492 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index 959bae132..baff53399 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,104 +1,104 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.211096 # Number of seconds simulated
-sim_ticks 1211096219500 # Number of ticks simulated
-final_tick 1211096219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.209315 # Number of seconds simulated
+sim_ticks 1209314565500 # Number of ticks simulated
+final_tick 1209314565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 325701 # Simulator instruction rate (inst/s)
-host_op_rate 325701 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 215976885 # Simulator tick rate (ticks/s)
-host_mem_usage 296636 # Number of bytes of host memory used
-host_seconds 5607.53 # Real time elapsed on the host
+host_inst_rate 310001 # Simulator instruction rate (inst/s)
+host_op_rate 310001 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 205263152 # Simulator tick rate (ticks/s)
+host_mem_usage 296916 # Number of bytes of host memory used
+host_seconds 5891.53 # Real time elapsed on the host
sim_insts 1826378509 # Number of instructions simulated
sim_ops 1826378509 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125445568 # Number of bytes read from this memory
-system.physmem.bytes_read::total 125506880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 124968128 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125029440 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65168832 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65168832 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 65415808 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65415808 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1960087 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1961045 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1018263 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1018263 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 50625 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 103580183 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 103630808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 50625 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 50625 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 53809789 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 53809789 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 53809789 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 50625 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 103580183 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 157440597 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1961045 # Number of read requests accepted
-system.physmem.writeReqs 1018263 # Number of write requests accepted
-system.physmem.readBursts 1961045 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1018263 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 125425280 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 81600 # Total number of bytes read from write queue
-system.physmem.bytesWritten 65167232 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 125506880 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 65168832 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1275 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu.data 1952627 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1953585 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1022122 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1022122 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 50700 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 103337983 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 103388683 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 50700 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 50700 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 54093294 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 54093294 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 54093294 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 50700 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 103337983 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 157481977 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1953585 # Number of read requests accepted
+system.physmem.writeReqs 1022122 # Number of write requests accepted
+system.physmem.readBursts 1953585 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1022122 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 124947328 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 82112 # Total number of bytes read from write queue
+system.physmem.bytesWritten 65414528 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 125029440 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 65415808 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1283 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 118758 # Per bank write bursts
-system.physmem.perBankRdBursts::1 114090 # Per bank write bursts
-system.physmem.perBankRdBursts::2 116233 # Per bank write bursts
-system.physmem.perBankRdBursts::3 117775 # Per bank write bursts
-system.physmem.perBankRdBursts::4 117826 # Per bank write bursts
-system.physmem.perBankRdBursts::5 117520 # Per bank write bursts
-system.physmem.perBankRdBursts::6 119879 # Per bank write bursts
-system.physmem.perBankRdBursts::7 124540 # Per bank write bursts
-system.physmem.perBankRdBursts::8 126979 # Per bank write bursts
-system.physmem.perBankRdBursts::9 130098 # Per bank write bursts
-system.physmem.perBankRdBursts::10 128644 # Per bank write bursts
-system.physmem.perBankRdBursts::11 130342 # Per bank write bursts
-system.physmem.perBankRdBursts::12 126070 # Per bank write bursts
-system.physmem.perBankRdBursts::13 125249 # Per bank write bursts
-system.physmem.perBankRdBursts::14 122589 # Per bank write bursts
-system.physmem.perBankRdBursts::15 123178 # Per bank write bursts
-system.physmem.perBankWrBursts::0 61223 # Per bank write bursts
-system.physmem.perBankWrBursts::1 61482 # Per bank write bursts
-system.physmem.perBankWrBursts::2 60569 # Per bank write bursts
-system.physmem.perBankWrBursts::3 61241 # Per bank write bursts
-system.physmem.perBankWrBursts::4 61665 # Per bank write bursts
-system.physmem.perBankWrBursts::5 63100 # Per bank write bursts
-system.physmem.perBankWrBursts::6 64149 # Per bank write bursts
-system.physmem.perBankWrBursts::7 65619 # Per bank write bursts
-system.physmem.perBankWrBursts::8 65334 # Per bank write bursts
-system.physmem.perBankWrBursts::9 65779 # Per bank write bursts
-system.physmem.perBankWrBursts::10 65299 # Per bank write bursts
-system.physmem.perBankWrBursts::11 65645 # Per bank write bursts
-system.physmem.perBankWrBursts::12 64166 # Per bank write bursts
-system.physmem.perBankWrBursts::13 64211 # Per bank write bursts
-system.physmem.perBankWrBursts::14 64570 # Per bank write bursts
-system.physmem.perBankWrBursts::15 64186 # Per bank write bursts
+system.physmem.perBankRdBursts::0 118324 # Per bank write bursts
+system.physmem.perBankRdBursts::1 113533 # Per bank write bursts
+system.physmem.perBankRdBursts::2 115739 # Per bank write bursts
+system.physmem.perBankRdBursts::3 117256 # Per bank write bursts
+system.physmem.perBankRdBursts::4 117310 # Per bank write bursts
+system.physmem.perBankRdBursts::5 117130 # Per bank write bursts
+system.physmem.perBankRdBursts::6 119399 # Per bank write bursts
+system.physmem.perBankRdBursts::7 124116 # Per bank write bursts
+system.physmem.perBankRdBursts::8 126631 # Per bank write bursts
+system.physmem.perBankRdBursts::9 129581 # Per bank write bursts
+system.physmem.perBankRdBursts::10 128158 # Per bank write bursts
+system.physmem.perBankRdBursts::11 129926 # Per bank write bursts
+system.physmem.perBankRdBursts::12 125582 # Per bank write bursts
+system.physmem.perBankRdBursts::13 124841 # Per bank write bursts
+system.physmem.perBankRdBursts::14 122135 # Per bank write bursts
+system.physmem.perBankRdBursts::15 122641 # Per bank write bursts
+system.physmem.perBankWrBursts::0 61422 # Per bank write bursts
+system.physmem.perBankWrBursts::1 61664 # Per bank write bursts
+system.physmem.perBankWrBursts::2 60721 # Per bank write bursts
+system.physmem.perBankWrBursts::3 61393 # Per bank write bursts
+system.physmem.perBankWrBursts::4 61822 # Per bank write bursts
+system.physmem.perBankWrBursts::5 63305 # Per bank write bursts
+system.physmem.perBankWrBursts::6 64352 # Per bank write bursts
+system.physmem.perBankWrBursts::7 65861 # Per bank write bursts
+system.physmem.perBankWrBursts::8 65572 # Per bank write bursts
+system.physmem.perBankWrBursts::9 66032 # Per bank write bursts
+system.physmem.perBankWrBursts::10 65638 # Per bank write bursts
+system.physmem.perBankWrBursts::11 65947 # Per bank write bursts
+system.physmem.perBankWrBursts::12 64508 # Per bank write bursts
+system.physmem.perBankWrBursts::13 64525 # Per bank write bursts
+system.physmem.perBankWrBursts::14 64898 # Per bank write bursts
+system.physmem.perBankWrBursts::15 64442 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 1211096102000 # Total gap between requests
+system.physmem.totGap 1209314463000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1961045 # Read request sizes (log2)
+system.physmem.readPktSize::6 1953585 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1018263 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1837965 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 121788 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1022122 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1829869 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 122416 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 30162 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 31578 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 55235 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 59406 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 59927 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 59993 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 59990 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 59955 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 59988 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 60013 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 59992 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 60054 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 60794 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 60336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 60363 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 61179 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 59712 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 59449 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 103 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 30602 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 31995 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 55357 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 59692 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 60130 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 60217 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 60162 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 60163 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 60176 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 60194 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 60206 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 60194 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 60705 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 61077 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 60633 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 61039 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 59828 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 59628 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
@@ -193,129 +193,136 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1839625 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 103.602019 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 81.031630 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 129.543213 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 1461173 79.43% 79.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 261967 14.24% 93.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 48998 2.66% 96.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 20657 1.12% 97.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 13124 0.71% 98.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 7476 0.41% 98.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5272 0.29% 98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 4494 0.24% 99.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16464 0.89% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1839625 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 59444 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 32.966456 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 164.214090 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 59406 99.94% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 59444 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 59444 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.129365 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.093444 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.113658 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 27743 46.67% 46.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1259 2.12% 48.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 26068 43.85% 92.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 3874 6.52% 99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 419 0.70% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 52 0.09% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 24 0.04% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 4 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 59444 # Writes before turning the bus around for reads
-system.physmem.totQLat 36839321750 # Total ticks spent queuing
-system.physmem.totMemAccLat 73585009250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 9798850000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 18797.78 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1831684 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 103.926852 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 81.136404 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 130.467751 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 1453241 79.34% 79.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 261868 14.30% 93.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 48841 2.67% 96.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 20589 1.12% 97.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 13172 0.72% 98.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 7181 0.39% 98.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5391 0.29% 98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 4514 0.25% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16887 0.92% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1831684 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 59621 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 32.743530 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 149.210927 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 59467 99.74% 99.74% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023 109 0.18% 99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559 6 0.01% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071 6 0.01% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095 3 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-13823 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 59621 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 59621 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.143322 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.107211 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.116873 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 27512 46.14% 46.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 1216 2.04% 48.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 26386 44.26% 92.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 3971 6.66% 99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 453 0.76% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 62 0.10% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 10 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 9 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 59621 # Writes before turning the bus around for reads
+system.physmem.totQLat 36542895500 # Total ticks spent queuing
+system.physmem.totMemAccLat 73148558000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 9761510000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 18717.85 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 37547.78 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 103.56 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 53.81 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 103.63 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 53.81 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 37467.85 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 103.32 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 54.09 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 103.39 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 54.09 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.23 # Data bus utilization in percentage
system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.96 # Average write queue length when enqueuing
-system.physmem.readRowHits 725244 # Number of row buffer hits during reads
-system.physmem.writeRowHits 413130 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 37.01 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 40.57 # Row buffer hit rate for writes
-system.physmem.avgGap 406502.48 # Average gap between requests
-system.physmem.pageHitRate 38.23 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 6747186600 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 3681500625 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 7383597000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3233831040 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 79102439520 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 416789244855 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 361048893750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 877986693390 # Total energy per rank (pJ)
-system.physmem_0.averagePower 724.956282 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 597858043000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 40440920000 # Time in different power states
+system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing
+system.physmem.readRowHits 723569 # Number of row buffer hits during reads
+system.physmem.writeRowHits 419148 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 37.06 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 41.01 # Row buffer hit rate for writes
+system.physmem.avgGap 406395.68 # Average gap between requests
+system.physmem.pageHitRate 38.42 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 6717619440 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 3665367750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 7353894600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3243499200 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 78986487840 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 416110602285 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 360579035250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 876656506365 # Total energy per rank (pJ)
+system.physmem_0.averagePower 724.920562 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 597088834750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 40381640000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 572793401000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 571843431500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 7160348160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 3906936000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 7901891400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3364351200 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 79102439520 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 428401624860 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 350862595500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 880700186640 # Total energy per rank (pJ)
-system.physmem_1.averagePower 727.196822 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 580834507250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 40440920000 # Time in different power states
+system.physmem_1.actEnergy 7129911600 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 3890328750 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 7873975200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3379721760 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 78986487840 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 426511213875 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 351455691750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 879227330775 # Total energy per rank (pJ)
+system.physmem_1.averagePower 727.046416 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 581836550250 # Time in different power states
+system.physmem_1.memoryStateTime::REF 40381640000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 589813744000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 587095716000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 246195404 # Number of BP lookups
-system.cpu.branchPred.condPredicted 186411563 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 15682149 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 167682775 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 165241760 # Number of BTB hits
+system.cpu.branchPred.lookups 246216332 # Number of BP lookups
+system.cpu.branchPred.condPredicted 186427958 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15694657 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 167633562 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 165258832 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.544266 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 18427120 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 104306 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 98.583380 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 18428300 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 104795 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 452923392 # DTB read hits
-system.cpu.dtb.read_misses 4979932 # DTB read misses
+system.cpu.dtb.read_hits 452931478 # DTB read hits
+system.cpu.dtb.read_misses 4979966 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 457903324 # DTB read accesses
-system.cpu.dtb.write_hits 161377581 # DTB write hits
-system.cpu.dtb.write_misses 1710142 # DTB write misses
+system.cpu.dtb.read_accesses 457911444 # DTB read accesses
+system.cpu.dtb.write_hits 161379324 # DTB write hits
+system.cpu.dtb.write_misses 1710368 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 163087723 # DTB write accesses
-system.cpu.dtb.data_hits 614300973 # DTB hits
-system.cpu.dtb.data_misses 6690074 # DTB misses
+system.cpu.dtb.write_accesses 163089692 # DTB write accesses
+system.cpu.dtb.data_hits 614310802 # DTB hits
+system.cpu.dtb.data_misses 6690334 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 620991047 # DTB accesses
-system.cpu.itb.fetch_hits 598257344 # ITB hits
+system.cpu.dtb.data_accesses 621001136 # DTB accesses
+system.cpu.itb.fetch_hits 598312460 # ITB hits
system.cpu.itb.fetch_misses 19 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 598257363 # ITB accesses
+system.cpu.itb.fetch_accesses 598312479 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -329,82 +336,82 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 2422192439 # number of cpu cycles simulated
+system.cpu.numCycles 2418629131 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1826378509 # Number of instructions committed
system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 52052944 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 52090489 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.326227 # CPI: cycles per instruction
-system.cpu.ipc 0.754019 # IPC: instructions per cycle
-system.cpu.tickCycles 2076133627 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 346058812 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 9121955 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4080.744039 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 601604629 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9126051 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 65.921682 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 16824784000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4080.744039 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.996275 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.996275 # Average percentage of cache occupancy
+system.cpu.cpi 1.324276 # CPI: cycles per instruction
+system.cpu.ipc 0.755130 # IPC: instructions per cycle
+system.cpu.tickCycles 2076311536 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 342317595 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 9121994 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4080.733344 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 601608000 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 9126090 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 65.921769 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 16821289500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4080.733344 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.996273 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.996273 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1544 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2417 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 1558 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 2405 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1231402079 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1231402079 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 443119981 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 443119981 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 158484648 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 158484648 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 601604629 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 601604629 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 601604629 # number of overall hits
-system.cpu.dcache.overall_hits::total 601604629 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7289531 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7289531 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2243854 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2243854 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 9533385 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9533385 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9533385 # number of overall misses
-system.cpu.dcache.overall_misses::total 9533385 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 186817706000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 186817706000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 108924057250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 108924057250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 295741763250 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 295741763250 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 295741763250 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 295741763250 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 450409512 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 450409512 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 1231414126 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1231414126 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 443125970 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 443125970 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 158482030 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 158482030 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 601608000 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 601608000 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 601608000 # number of overall hits
+system.cpu.dcache.overall_hits::total 601608000 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 7289546 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 7289546 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2246472 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2246472 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 9536018 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9536018 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9536018 # number of overall misses
+system.cpu.dcache.overall_misses::total 9536018 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 185444020000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 185444020000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 108463697500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 108463697500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 293907717500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 293907717500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 293907717500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 293907717500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 450415516 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 450415516 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 611138014 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 611138014 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 611138014 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 611138014 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 611144018 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 611144018 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 611144018 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 611144018 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016184 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016184 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013961 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.013961 # miss rate for WriteReq accesses
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -413,32 +420,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75266.480263 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75261.317563 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64698.329854 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75266.480263 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75261.317563 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213961 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.214043 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78108.328059 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78108.328059 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67687.369520 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67687.369520 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77358.078899 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77358.078899 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67687.369520 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77657.973848 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77653.084458 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67687.369520 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77657.973848 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.084458 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 7239691 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 7239691 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 3700563 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1887318 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1887318 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952665 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 21954581 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp 7239709 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 4708782 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 6334073 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1887339 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1887339 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 958 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238751 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374174 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 27376093 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820903296 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 820964608 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 12827572 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820016000 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 820077312 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 1920858 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 20169903 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.095234 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.293538 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 12827572 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 18249045 90.48% 90.48% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 1920858 9.52% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 12827572 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 10114349000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1637500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 20169903 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 12811182500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1437000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 14015266250 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 1181606 # Transaction distribution
-system.membus.trans_dist::ReadResp 1181606 # Transaction distribution
-system.membus.trans_dist::Writeback 1018263 # Transaction distribution
-system.membus.trans_dist::ReadExReq 779439 # Transaction distribution
-system.membus.trans_dist::ReadExResp 779439 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940353 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4940353 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675712 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 190675712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy 13689135000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
+system.membus.trans_dist::ReadResp 1173067 # Transaction distribution
+system.membus.trans_dist::Writeback 1022122 # Transaction distribution
+system.membus.trans_dist::CleanEvict 897712 # Transaction distribution
+system.membus.trans_dist::ReadExReq 780518 # Transaction distribution
+system.membus.trans_dist::ReadExResp 780518 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 1173067 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827004 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5827004 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190445248 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 190445248 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 2979308 # Request fanout histogram
+system.membus.snoop_fanout::samples 3873419 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2979308 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3873419 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 2979308 # Request fanout histogram
-system.membus.reqLayer0.occupancy 7754390500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 10727987500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3873419 # Request fanout histogram
+system.membus.reqLayer0.occupancy 8427454000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 10685206000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 58eeef87c..fd8f8a2dd 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,108 +1,108 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.672882 # Number of seconds simulated
-sim_ticks 672881519500 # Number of ticks simulated
-final_tick 672881519500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.671755 # Number of seconds simulated
+sim_ticks 671754803000 # Number of ticks simulated
+final_tick 671754803000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 165835 # Simulator instruction rate (inst/s)
-host_op_rate 165835 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64276745 # Simulator tick rate (ticks/s)
-host_mem_usage 226308 # Number of bytes of host memory used
-host_seconds 10468.51 # Real time elapsed on the host
+host_inst_rate 168955 # Simulator instruction rate (inst/s)
+host_op_rate 168955 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 65376371 # Simulator tick rate (ticks/s)
+host_mem_usage 298196 # Number of bytes of host memory used
+host_seconds 10275.19 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 62400 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125964544 # Number of bytes read from this memory
-system.physmem.bytes_read::total 126026944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125486976 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125549376 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 62400 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 62400 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65296192 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65296192 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 65552256 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65552256 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 975 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1968196 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1969171 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1020253 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1020253 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 92735 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 187201670 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 187294405 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 92735 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 92735 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 97039657 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 97039657 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 97039657 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 92735 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 187201670 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 284334062 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1969171 # Number of read requests accepted
-system.physmem.writeReqs 1020253 # Number of write requests accepted
-system.physmem.readBursts 1969171 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1020253 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 125945600 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue
-system.physmem.bytesWritten 65294336 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 126026944 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 65296192 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu.data 1960734 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1961709 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1024254 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1024254 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 92891 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 186804732 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 186897623 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 92891 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 92891 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 97583606 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 97583606 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 97583606 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 92891 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 186804732 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 284481229 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1961709 # Number of read requests accepted
+system.physmem.writeReqs 1024254 # Number of write requests accepted
+system.physmem.readBursts 1961709 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1024254 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 125464000 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 85376 # Total number of bytes read from write queue
+system.physmem.bytesWritten 65551040 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 125549376 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 65552256 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1334 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 119102 # Per bank write bursts
-system.physmem.perBankRdBursts::1 114505 # Per bank write bursts
-system.physmem.perBankRdBursts::2 116613 # Per bank write bursts
-system.physmem.perBankRdBursts::3 118153 # Per bank write bursts
-system.physmem.perBankRdBursts::4 118234 # Per bank write bursts
-system.physmem.perBankRdBursts::5 117885 # Per bank write bursts
-system.physmem.perBankRdBursts::6 120369 # Per bank write bursts
-system.physmem.perBankRdBursts::7 125035 # Per bank write bursts
-system.physmem.perBankRdBursts::8 127648 # Per bank write bursts
-system.physmem.perBankRdBursts::9 130593 # Per bank write bursts
-system.physmem.perBankRdBursts::10 129299 # Per bank write bursts
-system.physmem.perBankRdBursts::11 130947 # Per bank write bursts
-system.physmem.perBankRdBursts::12 126747 # Per bank write bursts
-system.physmem.perBankRdBursts::13 125863 # Per bank write bursts
-system.physmem.perBankRdBursts::14 123089 # Per bank write bursts
-system.physmem.perBankRdBursts::15 123818 # Per bank write bursts
-system.physmem.perBankWrBursts::0 61291 # Per bank write bursts
-system.physmem.perBankWrBursts::1 61585 # Per bank write bursts
-system.physmem.perBankWrBursts::2 60661 # Per bank write bursts
-system.physmem.perBankWrBursts::3 61360 # Per bank write bursts
-system.physmem.perBankWrBursts::4 61790 # Per bank write bursts
-system.physmem.perBankWrBursts::5 63221 # Per bank write bursts
-system.physmem.perBankWrBursts::6 64275 # Per bank write bursts
-system.physmem.perBankWrBursts::7 65726 # Per bank write bursts
-system.physmem.perBankWrBursts::8 65508 # Per bank write bursts
-system.physmem.perBankWrBursts::9 65914 # Per bank write bursts
-system.physmem.perBankWrBursts::10 65448 # Per bank write bursts
-system.physmem.perBankWrBursts::11 65777 # Per bank write bursts
-system.physmem.perBankWrBursts::12 64328 # Per bank write bursts
-system.physmem.perBankWrBursts::13 64347 # Per bank write bursts
-system.physmem.perBankWrBursts::14 64660 # Per bank write bursts
-system.physmem.perBankWrBursts::15 64333 # Per bank write bursts
+system.physmem.perBankRdBursts::0 118672 # Per bank write bursts
+system.physmem.perBankRdBursts::1 113926 # Per bank write bursts
+system.physmem.perBankRdBursts::2 116092 # Per bank write bursts
+system.physmem.perBankRdBursts::3 117630 # Per bank write bursts
+system.physmem.perBankRdBursts::4 117777 # Per bank write bursts
+system.physmem.perBankRdBursts::5 117495 # Per bank write bursts
+system.physmem.perBankRdBursts::6 119900 # Per bank write bursts
+system.physmem.perBankRdBursts::7 124641 # Per bank write bursts
+system.physmem.perBankRdBursts::8 127326 # Per bank write bursts
+system.physmem.perBankRdBursts::9 130085 # Per bank write bursts
+system.physmem.perBankRdBursts::10 128786 # Per bank write bursts
+system.physmem.perBankRdBursts::11 130484 # Per bank write bursts
+system.physmem.perBankRdBursts::12 126296 # Per bank write bursts
+system.physmem.perBankRdBursts::13 125416 # Per bank write bursts
+system.physmem.perBankRdBursts::14 122597 # Per bank write bursts
+system.physmem.perBankRdBursts::15 123252 # Per bank write bursts
+system.physmem.perBankWrBursts::0 61496 # Per bank write bursts
+system.physmem.perBankWrBursts::1 61762 # Per bank write bursts
+system.physmem.perBankWrBursts::2 60827 # Per bank write bursts
+system.physmem.perBankWrBursts::3 61508 # Per bank write bursts
+system.physmem.perBankWrBursts::4 61962 # Per bank write bursts
+system.physmem.perBankWrBursts::5 63415 # Per bank write bursts
+system.physmem.perBankWrBursts::6 64494 # Per bank write bursts
+system.physmem.perBankWrBursts::7 65970 # Per bank write bursts
+system.physmem.perBankWrBursts::8 65774 # Per bank write bursts
+system.physmem.perBankWrBursts::9 66157 # Per bank write bursts
+system.physmem.perBankWrBursts::10 65800 # Per bank write bursts
+system.physmem.perBankWrBursts::11 66076 # Per bank write bursts
+system.physmem.perBankWrBursts::12 64701 # Per bank write bursts
+system.physmem.perBankWrBursts::13 64671 # Per bank write bursts
+system.physmem.perBankWrBursts::14 65003 # Per bank write bursts
+system.physmem.perBankWrBursts::15 64619 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 672881423000 # Total gap between requests
+system.physmem.totGap 671754707500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1969171 # Read request sizes (log2)
+system.physmem.readPktSize::6 1961709 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1020253 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1621016 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 243733 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 72507 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 30617 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1024254 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1618535 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 241019 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 69861 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 30932 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
@@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 26054 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 27728 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 49537 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 56799 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 59190 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 60318 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 60638 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 60909 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 61008 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 61063 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 61159 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 61512 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 62241 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 62489 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::30 63055 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 61830 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 60052 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 173 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 26136 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
@@ -193,143 +193,150 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1777587 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 107.583217 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 82.835342 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 136.553801 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 1382839 77.79% 77.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 271264 15.26% 93.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 53815 3.03% 96.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 21128 1.19% 97.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 12924 0.73% 98.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 6598 0.37% 98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5024 0.28% 98.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3881 0.22% 98.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 20114 1.13% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1777587 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 59878 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 32.821905 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 161.087941 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 59840 99.94% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 59878 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 59878 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.038378 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.996376 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.234472 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 31771 53.06% 53.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1453 2.43% 55.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 20992 35.06% 90.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 4585 7.66% 98.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 809 1.35% 99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 191 0.32% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 14 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 5 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 2 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 5 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.bytesPerActivate::samples 1769993 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 107.917046 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 82.949504 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 137.477186 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 1374954 77.68% 77.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 271630 15.35% 93.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 53313 3.01% 96.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 21496 1.21% 97.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 12783 0.72% 97.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 6453 0.36% 98.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4820 0.27% 98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3869 0.22% 98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 20675 1.17% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1769993 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 60112 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 32.611592 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 146.109791 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 59940 99.71% 99.71% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023 128 0.21% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559 7 0.01% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071 6 0.01% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583 4 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 60112 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 60112 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.038778 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.996488 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.239516 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 31933 53.12% 53.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 1463 2.43% 55.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 20988 34.91% 90.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 4635 7.71% 98.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 815 1.36% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 185 0.31% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 40 0.07% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 14 0.02% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 10 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 4 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 3 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 3 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35 5 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39 3 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 59878 # Writes before turning the bus around for reads
-system.physmem.totQLat 40967898000 # Total ticks spent queuing
-system.physmem.totMemAccLat 77866023000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 9839500000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 20818.08 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::35 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 60112 # Writes before turning the bus around for reads
+system.physmem.totQLat 40612494250 # Total ticks spent queuing
+system.physmem.totMemAccLat 77369525500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 9801875000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 20716.70 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 39568.08 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 187.17 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 97.04 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 187.29 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 97.04 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 39466.70 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 186.77 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 97.58 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 186.90 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 97.58 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.22 # Data bus utilization in percentage
system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing
-system.physmem.readRowHits 794560 # Number of row buffer hits during reads
-system.physmem.writeRowHits 415972 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 40.38 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes
-system.physmem.avgGap 225087.32 # Average gap between requests
-system.physmem.pageHitRate 40.51 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 6515684280 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 3555184875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 7409165400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3239410320 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 305964835695 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 135337912500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 505971439710 # Total energy per rank (pJ)
-system.physmem_0.averagePower 751.948773 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 223158478000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 22468940000 # Time in different power states
+system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing
+system.physmem.readRowHits 792670 # Number of row buffer hits during reads
+system.physmem.writeRowHits 421939 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 41.19 # Row buffer hit rate for writes
+system.physmem.avgGap 224970.87 # Average gap between requests
+system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 6484688280 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 3538272375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 7379814000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3249285840 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 43875505440 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 305078205825 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 135438254250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 505044026010 # Total energy per rank (pJ)
+system.physmem_0.averagePower 751.831975 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 223329404750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 22431240000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 427253308500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 425992710250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 6922850760 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 3777349125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 7940244000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3371641200 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 312976099035 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 129187681500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 508125112260 # Total energy per rank (pJ)
-system.physmem_1.averagePower 755.149450 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 212887456750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 22468940000 # Time in different power states
+system.physmem_1.actEnergy 6896405880 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 3762919875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 7910526000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3387653280 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 43875505440 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 312108901605 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 129270987000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 507212899080 # Total energy per rank (pJ)
+system.physmem_1.averagePower 755.060642 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 213031369750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 22431240000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 437523815750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 436288612000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 410709882 # Number of BP lookups
-system.cpu.branchPred.condPredicted 318998342 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 16277823 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 282986544 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 279468528 # Number of BTB hits
+system.cpu.branchPred.lookups 410738673 # Number of BP lookups
+system.cpu.branchPred.condPredicted 319032195 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 16276977 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 282876736 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 279471264 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.756826 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 26379180 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 98.796129 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 26377862 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 646309229 # DTB read hits
-system.cpu.dtb.read_misses 12154225 # DTB read misses
+system.cpu.dtb.read_hits 646528255 # DTB read hits
+system.cpu.dtb.read_misses 12150594 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 658463454 # DTB read accesses
-system.cpu.dtb.write_hits 218201258 # DTB write hits
-system.cpu.dtb.write_misses 7510092 # DTB write misses
+system.cpu.dtb.read_accesses 658678849 # DTB read accesses
+system.cpu.dtb.write_hits 218209856 # DTB write hits
+system.cpu.dtb.write_misses 7511426 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 225711350 # DTB write accesses
-system.cpu.dtb.data_hits 864510487 # DTB hits
-system.cpu.dtb.data_misses 19664317 # DTB misses
+system.cpu.dtb.write_accesses 225721282 # DTB write accesses
+system.cpu.dtb.data_hits 864738111 # DTB hits
+system.cpu.dtb.data_misses 19662020 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 884174804 # DTB accesses
-system.cpu.itb.fetch_hits 422619736 # ITB hits
-system.cpu.itb.fetch_misses 46 # ITB misses
+system.cpu.dtb.data_accesses 884400131 # DTB accesses
+system.cpu.itb.fetch_hits 422614397 # ITB hits
+system.cpu.itb.fetch_misses 44 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 422619782 # ITB accesses
+system.cpu.itb.fetch_accesses 422614441 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -343,139 +350,139 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1345763040 # number of cpu cycles simulated
+system.cpu.numCycles 1343509607 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 433914332 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3420599858 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 410709882 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 305847708 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 888768265 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 46015780 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 433913722 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3420789895 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 410738673 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 305849126 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 886512749 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 46016020 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1748 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 422619736 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 8427195 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1345692377 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.541888 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.149351 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 1692 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 422614397 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 8419525 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1343436257 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.546299 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.150257 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 718495980 53.39% 53.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 48031633 3.57% 56.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 24393578 1.81% 58.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 45267643 3.36% 62.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 143041045 10.63% 72.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 66223895 4.92% 77.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 43793513 3.25% 80.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 29627313 2.20% 83.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 226817777 16.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 716181443 53.31% 53.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 48040729 3.58% 56.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 24412482 1.82% 58.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 45272149 3.37% 62.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 143062816 10.65% 72.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 66221905 4.93% 77.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 43789018 3.26% 80.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 29632862 2.21% 83.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 226822853 16.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1345692377 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.305187 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.541755 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 355603714 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 406294583 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 525817435 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 34969591 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 23007054 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 62310888 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 895 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3264812656 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2282 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 23007054 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 373973816 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 212778142 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7997 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 538797541 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 197127827 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3181847820 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1862600 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 20249864 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 150635497 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 31416943 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2377870821 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 4127617004 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 4127447466 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 169537 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1343436257 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.305721 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.546160 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 355607674 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 404003493 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 525762782 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 35055109 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 23007199 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 62310513 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 875 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3265200378 # Number of instructions handled by decode
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+system.cpu.rename.SquashCycles 23007199 # Number of cycles rename is squashing
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+system.cpu.rename.IQFullEvents 20271739 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 149993150 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 30859152 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2378179455 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 4128151916 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 4127979405 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 172510 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 1001667858 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 209 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 206 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 99280769 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 719325488 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 272942348 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 90808423 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 59047660 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2890368727 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2624396643 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1584497 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 1154325126 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 506084435 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed
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-system.cpu.iq.issued_per_cycle::mean 1.950220 # Number of insts issued each cycle
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+system.cpu.rename.UndoneMaps 1001976492 # Number of HB maps that are undone due to squashing
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+system.cpu.rename.tempSerializingInsts 195 # count of temporary serializing insts renamed
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+system.cpu.memDep0.conflictingStores 58783416 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2890757443 # Number of instructions added to the IQ (excludes non-spec)
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+system.cpu.iq.iqSquashedOperandsExamined 506306579 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::3 149383051 11.10% 75.68% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::4 126330762 9.40% 85.04% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1345692377 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1343436257 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 13165371 35.79% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 19036657 51.75% 87.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4585623 12.47% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 13176390 35.76% 35.76% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.76% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.76% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 19068779 51.75% 87.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4600766 12.49% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1719509054 65.52% 65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1719677353 65.52% 65.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 114 0.00% 65.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 896832 0.03% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 164 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 25 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 897887 0.03% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 158 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 22 0.00% 65.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued
@@ -497,84 +504,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 673114194 25.65% 91.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 230876222 8.80% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 673327193 25.65% 91.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 230890880 8.80% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2624396643 # Type of FU issued
-system.cpu.iq.rate 1.950118 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 36787651 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014018 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6630876089 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 4043543263 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2522176401 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1981722 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1297099 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 893189 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2660200136 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 984158 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 69569005 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2624793649 # Type of FU issued
+system.cpu.iq.rate 1.953684 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 36845935 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014038 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6629473751 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 4044314699 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2522399915 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1985727 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1304235 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 894550 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2660653801 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 985783 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 69567792 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 274729825 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 379855 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 148630 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 112213846 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 274803836 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 379517 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 149864 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 112236034 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 321 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 6130129 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 312 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 6300661 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 23007054 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 150994559 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 20053347 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 3041642230 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 6687101 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 719325488 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 272942348 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 819254 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 19491023 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 148630 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 10888571 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8843177 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 19731748 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2578706854 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 658463458 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 45689789 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 23007199 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 150535686 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 19606000 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 3042042837 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 6687461 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 719399499 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 272964536 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 174 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 810054 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 19058140 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 149864 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 10895731 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8841524 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 19737255 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2579092054 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 658678856 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 45701595 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 151273322 # number of nop insts executed
-system.cpu.iew.exec_refs 884174883 # number of memory reference insts executed
-system.cpu.iew.exec_branches 315972780 # Number of branches executed
-system.cpu.iew.exec_stores 225711425 # Number of stores executed
-system.cpu.iew.exec_rate 1.916167 # Inst execution rate
-system.cpu.iew.wb_sent 2553063246 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2523069590 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1489308587 # num instructions producing a value
-system.cpu.iew.wb_consumers 1920703402 # num instructions consuming a value
+system.cpu.iew.exec_nop 151285220 # number of nop insts executed
+system.cpu.iew.exec_refs 884400225 # number of memory reference insts executed
+system.cpu.iew.exec_branches 315980786 # Number of branches executed
+system.cpu.iew.exec_stores 225721369 # Number of stores executed
+system.cpu.iew.exec_rate 1.919668 # Inst execution rate
+system.cpu.iew.wb_sent 2553280591 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2523294465 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1489396348 # num instructions producing a value
+system.cpu.iew.wb_consumers 1920808747 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.874825 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.775397 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.878137 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.775401 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 1005912526 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1006176660 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16276987 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1206693157 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.508072 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.543192 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 16276166 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1204408845 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.510932 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.544476 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 717446911 59.46% 59.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 159887401 13.25% 72.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 79830197 6.62% 79.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 52027392 4.31% 83.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 28503242 2.36% 85.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 19553290 1.62% 87.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 20023421 1.66% 89.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 23140213 1.92% 91.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106281090 8.81% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 715098033 59.37% 59.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 159881136 13.27% 72.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 79829015 6.63% 79.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 52096588 4.33% 83.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 28578407 2.37% 85.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 19544658 1.62% 87.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 20010855 1.66% 89.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 23112076 1.92% 91.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106258077 8.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1206693157 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1204408845 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -620,340 +627,344 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
-system.cpu.commit.bw_lim_events 106281090 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 3840325519 # The number of ROB reads
-system.cpu.rob.rob_writes 5790523687 # The number of ROB writes
-system.cpu.timesIdled 690 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 70663 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 106258077 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 3838328354 # The number of ROB reads
+system.cpu.rob.rob_writes 5791077348 # The number of ROB writes
+system.cpu.timesIdled 692 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 73350 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.775190 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.775190 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.290007 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.290007 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3468053564 # number of integer regfile reads
-system.cpu.int_regfile_writes 2022530151 # number of integer regfile writes
-system.cpu.fp_regfile_reads 45442 # number of floating regfile reads
-system.cpu.fp_regfile_writes 563 # number of floating regfile writes
+system.cpu.cpi 0.773892 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.773892 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.292171 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.292171 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3468538615 # number of integer regfile reads
+system.cpu.int_regfile_writes 2022734233 # number of integer regfile writes
+system.cpu.fp_regfile_reads 46009 # number of floating regfile reads
+system.cpu.fp_regfile_writes 540 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 9208756 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4087.479772 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 713775439 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9212852 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 77.476056 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 5132407000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4087.479772 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.997920 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.997920 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 9208722 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4087.471997 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 713777147 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 9212818 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 77.476527 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 5130746500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4087.471997 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.997918 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.997918 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 697 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 2970 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 709 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 2958 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1472909430 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1472909430 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 558274718 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 558274718 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 155500717 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 155500717 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 713775435 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 713775435 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 713775435 # number of overall hits
-system.cpu.dcache.overall_hits::total 713775435 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 12845064 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 12845064 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5227785 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5227785 # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses 1473023486 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1473023486 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 558278644 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 558278644 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 155498498 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 155498498 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data 713777142 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 713777142 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 713777142 # number of overall hits
+system.cpu.dcache.overall_hits::total 713777142 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 12898182 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 12898182 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 5230004 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 5230004 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 18072849 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 18072849 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 18072849 # number of overall misses
-system.cpu.dcache.overall_misses::total 18072849 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 414536288750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 414536288750 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 316664843212 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 316664843212 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 18128186 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 18128186 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 18128186 # number of overall misses
+system.cpu.dcache.overall_misses::total 18128186 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 411532558500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 411532558500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 315240579886 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 315240579886 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 731201131962 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 731201131962 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 731201131962 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 731201131962 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 571119782 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 571119782 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 726773138386 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 726773138386 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 726773138386 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 726773138386 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 571176826 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
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-system.cpu.l2cache.writebacks::total 1020253 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196875 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1197850 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771321 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 771321 # number of ReadExReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks 1024254 # number of writebacks
+system.cpu.l2cache.writebacks::total 1024254 # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 241 # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total 241 # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772262 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 772262 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 975 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 975 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188472 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1188472 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1968196 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 1969171 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1960734 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 1961709 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1968196 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 1969171 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66029500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 92659024750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92725054250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59593481750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59593481750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66029500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 152252506500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 152318536000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66029500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 152252506500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 152318536000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163199 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163311 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410489 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410489 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1960734 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 1961709 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61629949000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61629949000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 71646500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 71646500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94648969500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94648969500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71646500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156278918500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 156350565000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71646500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156278918500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 156350565000 # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410986 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410986 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162055 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162055 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.213719 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212827 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.212910 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.213719 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67722.564103 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77417.461932 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77409.570689 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77261.583374 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77261.583374 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212827 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.212910 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79804.456260 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79804.456260 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73483.589744 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73483.589744 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79639.208580 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79639.208580 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73483.589744 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79704.293647 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79701.201860 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73483.589744 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79704.293647 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79701.201860 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 7334797 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 7334797 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 3742849 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1879030 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1879030 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1950 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168553 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 22170503 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp 7334745 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 4752776 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 6384952 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1879048 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1879048 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 975 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333770 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1951 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27634358 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 27636309 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829164864 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 829227264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 12956676 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828245760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 828308160 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 1929005 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 20351521 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.094784 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.292917 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 12956676 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 18422516 90.52% 90.52% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 1929005 9.48% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 12956676 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 10221187000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1642000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 20351521 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 12939780000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1462500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 14136511250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 13819227000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 1197850 # Transaction distribution
-system.membus.trans_dist::ReadResp 1197850 # Transaction distribution
-system.membus.trans_dist::Writeback 1020253 # Transaction distribution
-system.membus.trans_dist::ReadExReq 771321 # Transaction distribution
-system.membus.trans_dist::ReadExResp 771321 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958595 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4958595 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191323136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 191323136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 1189447 # Transaction distribution
+system.membus.trans_dist::Writeback 1024254 # Transaction distribution
+system.membus.trans_dist::CleanEvict 903687 # Transaction distribution
+system.membus.trans_dist::ReadExReq 772262 # Transaction distribution
+system.membus.trans_dist::ReadExResp 772262 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 1189447 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851359 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5851359 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191101632 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 191101632 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 2989424 # Request fanout histogram
+system.membus.snoop_fanout::samples 3889650 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2989424 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3889650 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 2989424 # Request fanout histogram
-system.membus.reqLayer0.occupancy 7771933000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 10726595500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3889650 # Request fanout histogram
+system.membus.reqLayer0.occupancy 8475841500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
+system.membus.respLayer1.occupancy 10684260000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 6346aa78f..018ebe8b0 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.623365 # Number of seconds simulated
-sim_ticks 2623365440500 # Number of ticks simulated
-final_tick 2623365440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.623057 # Number of seconds simulated
+sim_ticks 2623057163500 # Number of ticks simulated
+final_tick 2623057163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1411989 # Simulator instruction rate (inst/s)
-host_op_rate 1411989 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2035500124 # Simulator tick rate (ticks/s)
-host_mem_usage 294160 # Number of bytes of host memory used
-host_seconds 1288.81 # Real time elapsed on the host
+host_inst_rate 1251674 # Simulator instruction rate (inst/s)
+host_op_rate 1251674 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1804181213 # Simulator tick rate (ticks/s)
+host_mem_usage 294596 # Number of bytes of host memory used
+host_seconds 1453.88 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125367104 # Number of bytes read from this memory
-system.physmem.bytes_read::total 125418432 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory
+system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65156928 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65156928 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 65405568 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65405568 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1958861 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1959663 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 47788654 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 47808220 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 24837153 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 24837153 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 24837153 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 47788654 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 72645373 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 1951440 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 19568 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 47613206 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 47632774 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 19568 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 19568 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 24934862 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 24934862 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 24934862 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 19568 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 47613206 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 72567635 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 5246730881 # number of cpu cycles simulated
+system.cpu.numCycles 5246114327 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1819780127 # Number of instructions committed
@@ -89,7 +89,7 @@ system.cpu.num_mem_refs 611922547 # nu
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 5246730881 # Number of busy cycles
+system.cpu.num_busy_cycles 5246114327 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 214632552 # Number of branches fetched
@@ -129,14 +129,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1826378509 # Class of executed instruction
system.cpu.dcache.tags.replacements 9107638 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4079.262739 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 4079.260769 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 40977437000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262739 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle 40977438500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4079.260769 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.995913 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.995913 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id
@@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143355355000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143355355000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 57375808000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 57375808000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200731163000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200731163000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200731163000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200731163000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 143001525000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 143001525000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 57421337000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 57421337000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 200422862000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 200422862000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200422862000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200422862000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
@@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19848.675941 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19848.675941 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30368.496602 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30368.496602 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22029.963013 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22029.963013 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19799.685396 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19799.685396 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30392.594690 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30392.594690 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21996.127411 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21996.127411 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -202,8 +202,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks
-system.cpu.dcache.writebacks::total 3693497 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks
+system.cpu.dcache.writebacks::total 3679426 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
@@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132521734000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 132521734000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54541828000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 54541828000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187063562000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 187063562000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187063562000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 187063562000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135779111000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 135779111000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55532017000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 55532017000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191311128000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 191311128000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191311128000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191311128000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
@@ -228,24 +228,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18348.675941 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18348.675941 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28868.496602 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28868.496602 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18799.685396 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18799.685396 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29392.594690 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29392.594690 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1 # number of replacements
-system.cpu.icache.tags.tagsinuse 612.458786 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 612.447387 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 612.458786 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 612.447387 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.299047 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.299047 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id
@@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
system.cpu.icache.overall_misses::total 802 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 44139500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 44139500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 44139500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 44139500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 44139500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 44139500 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 44163500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 44163500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 44163500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 44163500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 44163500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 44163500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses
@@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55036.783042 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55036.783042 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55036.783042 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55036.783042 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.708229 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55066.708229 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55066.708229 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -302,114 +302,119 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 42936500 # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total 42936500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42936500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.783042 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53536.783042 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 1926937 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 30535.253333 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 218167126000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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@@ -418,105 +423,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 12806033 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 818685568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 1919524 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 20139699 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.095310 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.293643 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 12806033 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 18220175 90.47% 90.47% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 1919524 9.53% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 12806033 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 20139699 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 12789513500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 1178362 # Transaction distribution
-system.membus.trans_dist::ReadResp 1178362 # Transaction distribution
-system.membus.trans_dist::Writeback 1018077 # Transaction distribution
-system.membus.trans_dist::ReadExReq 781301 # Transaction distribution
-system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 1169857 # Transaction distribution
+system.membus.trans_dist::Writeback 1021962 # Transaction distribution
+system.membus.trans_dist::CleanEvict 896683 # Transaction distribution
+system.membus.trans_dist::ReadExReq 782385 # Transaction distribution
+system.membus.trans_dist::ReadExResp 782385 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 1169857 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5823129 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5823129 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 2977740 # Request fanout histogram
+system.membus.snoop_fanout::samples 3872712 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3872712 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 2977740 # Request fanout histogram
-system.membus.reqLayer0.occupancy 7156873500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3872712 # Request fanout histogram
+system.membus.reqLayer0.occupancy 7960873524 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 9798315500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 9761522024 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------