diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/60.bzip2/ref/alpha | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha')
3 files changed, 1523 insertions, 1519 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 0dacf1436..520a2b090 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.199774 # Number of seconds simulated -sim_ticks 1199774280000 # Number of ticks simulated -final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.211624 # Number of seconds simulated +sim_ticks 1211624479500 # Number of ticks simulated +final_tick 1211624479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216625 # Simulator instruction rate (inst/s) -host_op_rate 216625 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 142303871 # Simulator tick rate (ticks/s) -host_mem_usage 282608 # Number of bytes of host memory used -host_seconds 8431.08 # Real time elapsed on the host +host_inst_rate 333436 # Simulator instruction rate (inst/s) +host_op_rate 333436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 221202175 # Simulator tick rate (ticks/s) +host_mem_usage 295444 # Number of bytes of host memory used +host_seconds 5477.45 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125444608 # Number of bytes read from this memory -system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory -system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960072 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 51156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 104556840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 51156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 104556840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961031 # Number of read requests accepted -system.physmem.writeReqs 1018242 # Number of write requests accepted -system.physmem.readBursts 1961031 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018242 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125423808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82176 # Total number of bytes read from write queue -system.physmem.bytesWritten 65166208 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125505984 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65167488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1284 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125444544 # Number of bytes read from this memory +system.physmem.bytes_read::total 125505792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65167616 # Number of bytes written to this memory +system.physmem.bytes_written::total 65167616 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960071 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961028 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018244 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018244 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103534178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103584728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 53785325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 53785325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 53785325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103534178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157370053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961028 # Number of read requests accepted +system.physmem.writeReqs 1018244 # Number of write requests accepted +system.physmem.readBursts 1961028 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018244 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125424064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81728 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125505792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65167616 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1277 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118757 # Per bank write bursts -system.physmem.perBankRdBursts::1 114096 # Per bank write bursts -system.physmem.perBankRdBursts::2 116226 # Per bank write bursts -system.physmem.perBankRdBursts::3 117770 # Per bank write bursts -system.physmem.perBankRdBursts::4 117824 # Per bank write bursts -system.physmem.perBankRdBursts::5 117523 # Per bank write bursts -system.physmem.perBankRdBursts::6 119882 # Per bank write bursts -system.physmem.perBankRdBursts::7 124516 # Per bank write bursts -system.physmem.perBankRdBursts::8 126973 # Per bank write bursts -system.physmem.perBankRdBursts::9 130090 # Per bank write bursts -system.physmem.perBankRdBursts::10 128654 # Per bank write bursts -system.physmem.perBankRdBursts::11 130347 # Per bank write bursts -system.physmem.perBankRdBursts::12 126055 # Per bank write bursts -system.physmem.perBankRdBursts::13 125249 # Per bank write bursts -system.physmem.perBankRdBursts::14 122591 # Per bank write bursts -system.physmem.perBankRdBursts::15 123194 # Per bank write bursts -system.physmem.perBankWrBursts::0 61222 # Per bank write bursts -system.physmem.perBankWrBursts::1 61485 # Per bank write bursts -system.physmem.perBankWrBursts::2 60564 # Per bank write bursts +system.physmem.perBankRdBursts::0 118746 # Per bank write bursts +system.physmem.perBankRdBursts::1 114093 # Per bank write bursts +system.physmem.perBankRdBursts::2 116238 # Per bank write bursts +system.physmem.perBankRdBursts::3 117765 # Per bank write bursts +system.physmem.perBankRdBursts::4 117832 # Per bank write bursts +system.physmem.perBankRdBursts::5 117522 # Per bank write bursts +system.physmem.perBankRdBursts::6 119888 # Per bank write bursts +system.physmem.perBankRdBursts::7 124523 # Per bank write bursts +system.physmem.perBankRdBursts::8 126979 # Per bank write bursts +system.physmem.perBankRdBursts::9 130092 # Per bank write bursts +system.physmem.perBankRdBursts::10 128645 # Per bank write bursts +system.physmem.perBankRdBursts::11 130343 # Per bank write bursts +system.physmem.perBankRdBursts::12 126054 # Per bank write bursts +system.physmem.perBankRdBursts::13 125251 # Per bank write bursts +system.physmem.perBankRdBursts::14 122593 # Per bank write bursts +system.physmem.perBankRdBursts::15 123187 # Per bank write bursts +system.physmem.perBankWrBursts::0 61219 # Per bank write bursts +system.physmem.perBankWrBursts::1 61484 # Per bank write bursts +system.physmem.perBankWrBursts::2 60571 # Per bank write bursts system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61658 # Per bank write bursts -system.physmem.perBankWrBursts::5 63101 # Per bank write bursts -system.physmem.perBankWrBursts::6 64148 # Per bank write bursts -system.physmem.perBankWrBursts::7 65617 # Per bank write bursts -system.physmem.perBankWrBursts::8 65332 # Per bank write bursts -system.physmem.perBankWrBursts::9 65778 # Per bank write bursts -system.physmem.perBankWrBursts::10 65295 # Per bank write bursts -system.physmem.perBankWrBursts::11 65646 # Per bank write bursts -system.physmem.perBankWrBursts::12 64171 # Per bank write bursts -system.physmem.perBankWrBursts::13 64211 # Per bank write bursts -system.physmem.perBankWrBursts::14 64568 # Per bank write bursts +system.physmem.perBankWrBursts::4 61659 # Per bank write bursts +system.physmem.perBankWrBursts::5 63100 # Per bank write bursts +system.physmem.perBankWrBursts::6 64152 # Per bank write bursts +system.physmem.perBankWrBursts::7 65616 # Per bank write bursts +system.physmem.perBankWrBursts::8 65335 # Per bank write bursts +system.physmem.perBankWrBursts::9 65774 # Per bank write bursts +system.physmem.perBankWrBursts::10 65298 # Per bank write bursts +system.physmem.perBankWrBursts::11 65641 # Per bank write bursts +system.physmem.perBankWrBursts::12 64170 # Per bank write bursts +system.physmem.perBankWrBursts::13 64210 # Per bank write bursts +system.physmem.perBankWrBursts::14 64569 # Per bank write bursts system.physmem.perBankWrBursts::15 64187 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1199774169500 # Total gap between requests +system.physmem.totGap 1211624362000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961031 # Read request sizes (log2) +system.physmem.readPktSize::6 1961028 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018242 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1834284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018244 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1838105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 59970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -193,129 +193,130 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1838370 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.671596 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.054008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.842659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1459678 79.40% 79.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 262161 14.26% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49287 2.68% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20645 1.12% 97.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12893 0.70% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7143 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5357 0.29% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4451 0.24% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16755 0.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1838370 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59429 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.975652 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.968947 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59388 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1839318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.618163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.033976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.636069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1460921 79.43% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261839 14.24% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49211 2.68% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20654 1.12% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12987 0.71% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7330 0.40% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5324 0.29% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4553 0.25% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16499 0.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1839318 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59419 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.981269 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 162.030420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59379 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59429 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59429 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.133420 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.097680 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.110939 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27565 46.38% 46.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1269 2.14% 48.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26249 44.17% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3908 6.58% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 362 0.61% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 56 0.09% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59429 # Writes before turning the bus around for reads -system.physmem.totQLat 36751953000 # Total ticks spent queuing -system.physmem.totMemAccLat 73497209250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798735000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18753.42 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59419 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.136337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.100269 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.116106 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27590 46.43% 46.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1250 2.10% 48.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26098 43.92% 92.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3967 6.68% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 431 0.73% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 63 0.11% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 13 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59419 # Writes before turning the bus around for reads +system.physmem.totQLat 36831870500 # Total ticks spent queuing +system.physmem.totMemAccLat 73577201750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18794.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37503.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 104.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 54.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 104.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 54.32 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37544.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 53.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 53.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.24 # Data bus utilization in percentage -system.physmem.busUtilRead 0.82 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing -system.physmem.readRowHits 726418 # Number of row buffer hits during reads -system.physmem.writeRowHits 413172 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.58 # Row buffer hit rate for writes -system.physmem.avgGap 402707.03 # Average gap between requests -system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6745500720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3680580750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7383386400 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing +system.physmem.readRowHits 725319 # Number of row buffer hits during reads +system.physmem.writeRowHits 413326 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.59 # Row buffer hit rate for writes +system.physmem.avgGap 406684.71 # Average gap between requests +system.physmem.pageHitRate 38.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6747405840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3681620250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7383487800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 3233733840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 409753789290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 360427621500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 869587605780 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.796496 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 596865139750 # Time in different power states -system.physmem_0.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_0.refreshEnergy 79137021600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416124660195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361949541750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 878257471275 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.862968 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 599359370250 # Time in different power states +system.physmem_0.memoryStateTime::REF 40458600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 562842538250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 571802499750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7152516000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3902662500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7901961600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3364241040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 422708761260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 349063611000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 872456746680 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.187909 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 577877428500 # Time in different power states -system.physmem_1.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_1.actEnergy 7157785320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3905537625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7902000600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3364254000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 79137021600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 427714080030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 351783384000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 880964063175 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.096833 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 582370760250 # Time in different power states +system.physmem_1.memoryStateTime::REF 40458600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 581827655250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 588789276000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 246222594 # Number of BP lookups -system.cpu.branchPred.condPredicted 186441188 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15682162 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 167748253 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165224895 # Number of BTB hits +system.cpu.branchPred.lookups 246245862 # Number of BP lookups +system.cpu.branchPred.condPredicted 186459693 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15680292 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167860438 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165233261 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.495747 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18427327 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104678 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.434904 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18428492 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104737 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452533853 # DTB read hits -system.cpu.dtb.read_misses 4979561 # DTB read misses +system.cpu.dtb.read_hits 452534136 # DTB read hits +system.cpu.dtb.read_misses 4979812 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457513414 # DTB read accesses -system.cpu.dtb.write_hits 161377742 # DTB write hits -system.cpu.dtb.write_misses 1710117 # DTB write misses +system.cpu.dtb.read_accesses 457513948 # DTB read accesses +system.cpu.dtb.write_hits 161377662 # DTB write hits +system.cpu.dtb.write_misses 1710258 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163087859 # DTB write accesses -system.cpu.dtb.data_hits 613911595 # DTB hits -system.cpu.dtb.data_misses 6689678 # DTB misses +system.cpu.dtb.write_accesses 163087920 # DTB write accesses +system.cpu.dtb.data_hits 613911798 # DTB hits +system.cpu.dtb.data_misses 6690070 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620601273 # DTB accesses -system.cpu.itb.fetch_hits 598493672 # ITB hits +system.cpu.dtb.data_accesses 620601868 # DTB accesses +system.cpu.itb.fetch_hits 598519306 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598493691 # ITB accesses +system.cpu.itb.fetch_accesses 598519325 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,82 +330,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2399548560 # number of cpu cycles simulated +system.cpu.numCycles 2423248959 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52395177 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52407440 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.313829 # CPI: cycles per instruction -system.cpu.ipc 0.761134 # IPC: instructions per cycle -system.cpu.tickCycles 2077217503 # Number of cycles that the object actually ticked -system.cpu.idleCycles 322331057 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121997 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.675710 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601828569 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.675710 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy +system.cpu.cpi 1.326805 # CPI: cycles per instruction +system.cpu.ipc 0.753690 # IPC: instructions per cycle +system.cpu.tickCycles 2077336659 # Number of cycles that the object actually ticked +system.cpu.idleCycles 345912300 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9122013 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.749026 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601822613 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126109 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.945148 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16826930000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.749026 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1613 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2310 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 443338834 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443338834 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158489735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158489735 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 601828569 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601828569 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 601828569 # number of overall hits -system.cpu.dcache.overall_hits::total 601828569 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7289569 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289569 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2238767 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238767 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9528336 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9528336 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9528336 # number of overall misses -system.cpu.dcache.overall_misses::total 9528336 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 178039686000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 178039686000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 100958450500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 100958450500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 278998136500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 278998136500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 278998136500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 278998136500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 450628403 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450628403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231838683 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231838683 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443338219 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443338219 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158484394 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158484394 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601822613 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601822613 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601822613 # number of overall hits +system.cpu.dcache.overall_hits::total 601822613 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289566 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289566 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2244108 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2244108 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9533674 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9533674 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9533674 # number of overall misses +system.cpu.dcache.overall_misses::total 9533674 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 186798880750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 186798880750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108940864000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108940864000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 295739744750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 295739744750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 295739744750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 295739744750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450627785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450627785 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 611356905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611356905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 611356905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611356905 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 611356287 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611356287 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611356287 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611356287 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013929 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013929 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015586 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015586 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24423.897490 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24423.897490 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45095.559520 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45095.559520 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29280.887712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013962 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013962 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015594 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015594 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.514708 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.514708 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48545.285699 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48545.285699 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31020.543051 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31020.543051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31020.543051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31020.543051 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,32 +414,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700624 # number of writebacks -system.cpu.dcache.writebacks::total 3700624 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50811 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 351432 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 351432 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 402243 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 402243 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 402243 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 402243 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238758 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238758 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887335 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887335 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126093 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126093 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126093 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126093 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162083992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162083992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75948494500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75948494500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 238032486500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 238032486500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 238032486500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 238032486500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700625 # number of writebacks +system.cpu.dcache.writebacks::total 3700625 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50791 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50791 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 356774 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 356774 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 407565 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 407565 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 407565 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 407565 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238775 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238775 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887334 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887334 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126109 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126109 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126109 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126109 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 174334776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 174334776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82397045250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 82397045250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256731821250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 256731821250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 256731821250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 256731821250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -447,66 +448,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014928 system.cpu.dcache.demand_mshr_miss_rate::total 0.014928 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014928 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014928 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22391.132844 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22391.132844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40241.130748 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40241.130748 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26082.627747 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26082.627747 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24083.463846 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24083.463846 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43657.903291 # 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Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 751.304686 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 598518349 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 625411.022989 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 752.081160 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.367227 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.367227 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 956 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 751.304686 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366848 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366848 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.466797 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1196988303 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1196988303 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 598492713 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 598492713 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 598492713 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 598492713 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 598492713 # number of overall hits -system.cpu.icache.overall_hits::total 598492713 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 959 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 959 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 959 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 959 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 959 # number of overall misses -system.cpu.icache.overall_misses::total 959 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 71027250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 71027250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 71027250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 71027250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 71027250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 71027250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 598493672 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 598493672 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 598493672 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 598493672 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 598493672 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 598493672 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1197039569 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1197039569 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 598518349 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 598518349 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 598518349 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 598518349 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 598518349 # number of overall hits +system.cpu.icache.overall_hits::total 598518349 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses +system.cpu.icache.overall_misses::total 957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 77501250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 77501250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 77501250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 77501250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 77501250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 77501250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 598519306 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 598519306 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 598519306 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 598519306 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 598519306 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 598519306 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74063.868613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74063.868613 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74063.868613 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74063.868613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74063.868613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74063.868613 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80983.542320 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80983.542320 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80983.542320 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80983.542320 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80983.542320 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80983.542320 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,120 +516,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 959 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 959 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 959 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68715750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68715750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68715750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68715750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68715750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68715750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75665250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75665250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75665250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75665250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75665250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75665250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71653.545360 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71653.545360 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71653.545360 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71653.545360 # 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number of replacements -system.cpu.l2cache.tags.tagsinuse 30756.810610 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8981713 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1958100 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.586953 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 89009074750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14951.890642 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 43.293989 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15761.625979 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.456295 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001321 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.481007 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62720750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147510180000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 147572900750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163097 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163208 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412990 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214776 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.214859 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214776 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58081.074035 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67267.837631 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67260.381430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68154.174097 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68154.174097 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65538.923720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74998.570670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74990.908995 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75649.873372 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75649.873372 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65538.923720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75257.569751 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75252.826961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65538.923720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75257.569751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75252.826961 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7239717 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239717 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887335 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952810 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954728 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820909888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820971264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7239732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887334 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952843 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954757 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820910976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820972224 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12827676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12827691 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12827676 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827691 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12827676 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10114462000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12827691 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114470500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1635250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1635750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14011262000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14015207750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1181581 # Transaction distribution -system.membus.trans_dist::ReadResp 1181581 # Transaction distribution -system.membus.trans_dist::Writeback 1018242 # Transaction distribution -system.membus.trans_dist::ReadExReq 779450 # Transaction distribution -system.membus.trans_dist::ReadExResp 779450 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940304 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190673472 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1181580 # Transaction distribution +system.membus.trans_dist::ReadResp 1181580 # Transaction distribution +system.membus.trans_dist::Writeback 1018244 # Transaction distribution +system.membus.trans_dist::ReadExReq 779448 # Transaction distribution +system.membus.trans_dist::ReadExResp 779448 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940300 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190673408 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979273 # Request fanout histogram +system.membus.snoop_fanout::samples 2979272 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979273 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979272 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979273 # Request fanout histogram -system.membus.reqLayer0.occupancy 11833185000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18446289250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.5 # Layer utilization (%) +system.membus.snoop_fanout::total 2979272 # Request fanout histogram +system.membus.reqLayer0.occupancy 7744840000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 10727612750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 9b6ff7bd3..47b73b46e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.662030 # Number of seconds simulated -sim_ticks 662030381000 # Number of ticks simulated -final_tick 662030381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.672882 # Number of seconds simulated +sim_ticks 672881519500 # Number of ticks simulated +final_tick 672881519500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173779 # Simulator instruction rate (inst/s) -host_op_rate 173779 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66269486 # Simulator tick rate (ticks/s) -host_mem_usage 296312 # Number of bytes of host memory used -host_seconds 9989.97 # Real time elapsed on the host +host_inst_rate 171066 # Simulator instruction rate (inst/s) +host_op_rate 171066 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66304234 # Simulator tick rate (ticks/s) +host_mem_usage 296744 # Number of bytes of host memory used +host_seconds 10148.39 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125964224 # Number of bytes read from this memory -system.physmem.bytes_read::total 126026048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65301568 # Number of bytes written to this memory -system.physmem.bytes_written::total 65301568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1968191 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1969157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1020337 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1020337 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 190269552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 190362937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93385 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93385 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98638325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98638325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98638325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 190269552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 289001263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1969157 # Number of read requests accepted -system.physmem.writeReqs 1020337 # Number of write requests accepted -system.physmem.readBursts 1969157 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1020337 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125945216 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 80832 # Total number of bytes read from write queue -system.physmem.bytesWritten 65299584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126026048 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65301568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1263 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 62400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125964544 # Number of bytes read from this memory +system.physmem.bytes_read::total 126026944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65296192 # Number of bytes written to this memory +system.physmem.bytes_written::total 65296192 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 975 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968196 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969171 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020253 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020253 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 187201670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 187294405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97039657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97039657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97039657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 187201670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 284334062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969171 # Number of read requests accepted +system.physmem.writeReqs 1020253 # Number of write requests accepted +system.physmem.readBursts 1969171 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020253 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125945600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue +system.physmem.bytesWritten 65294336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126026944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65296192 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119107 # Per bank write bursts -system.physmem.perBankRdBursts::1 114513 # Per bank write bursts -system.physmem.perBankRdBursts::2 116588 # Per bank write bursts -system.physmem.perBankRdBursts::3 118130 # Per bank write bursts -system.physmem.perBankRdBursts::4 118281 # Per bank write bursts -system.physmem.perBankRdBursts::5 117894 # Per bank write bursts -system.physmem.perBankRdBursts::6 120372 # Per bank write bursts -system.physmem.perBankRdBursts::7 125027 # Per bank write bursts -system.physmem.perBankRdBursts::8 127642 # Per bank write bursts -system.physmem.perBankRdBursts::9 130604 # Per bank write bursts -system.physmem.perBankRdBursts::10 129295 # Per bank write bursts -system.physmem.perBankRdBursts::11 130929 # Per bank write bursts -system.physmem.perBankRdBursts::12 126770 # Per bank write bursts -system.physmem.perBankRdBursts::13 125862 # Per bank write bursts -system.physmem.perBankRdBursts::14 123081 # Per bank write bursts -system.physmem.perBankRdBursts::15 123799 # Per bank write bursts -system.physmem.perBankWrBursts::0 61289 # Per bank write bursts -system.physmem.perBankWrBursts::1 61597 # Per bank write bursts -system.physmem.perBankWrBursts::2 60658 # Per bank write bursts -system.physmem.perBankWrBursts::3 61339 # Per bank write bursts -system.physmem.perBankWrBursts::4 61821 # Per bank write bursts -system.physmem.perBankWrBursts::5 63209 # Per bank write bursts -system.physmem.perBankWrBursts::6 64289 # Per bank write bursts -system.physmem.perBankWrBursts::7 65739 # Per bank write bursts -system.physmem.perBankWrBursts::8 65503 # Per bank write bursts -system.physmem.perBankWrBursts::9 65920 # Per bank write bursts -system.physmem.perBankWrBursts::10 65439 # Per bank write bursts -system.physmem.perBankWrBursts::11 65771 # Per bank write bursts -system.physmem.perBankWrBursts::12 64363 # Per bank write bursts -system.physmem.perBankWrBursts::13 64352 # Per bank write bursts -system.physmem.perBankWrBursts::14 64685 # Per bank write bursts -system.physmem.perBankWrBursts::15 64332 # Per bank write bursts +system.physmem.perBankRdBursts::0 119102 # Per bank write bursts +system.physmem.perBankRdBursts::1 114505 # Per bank write bursts +system.physmem.perBankRdBursts::2 116613 # Per bank write bursts +system.physmem.perBankRdBursts::3 118153 # Per bank write bursts +system.physmem.perBankRdBursts::4 118234 # Per bank write bursts +system.physmem.perBankRdBursts::5 117885 # Per bank write bursts +system.physmem.perBankRdBursts::6 120369 # Per bank write bursts +system.physmem.perBankRdBursts::7 125035 # Per bank write bursts +system.physmem.perBankRdBursts::8 127648 # Per bank write bursts +system.physmem.perBankRdBursts::9 130593 # Per bank write bursts +system.physmem.perBankRdBursts::10 129299 # Per bank write bursts +system.physmem.perBankRdBursts::11 130947 # Per bank write bursts +system.physmem.perBankRdBursts::12 126747 # Per bank write bursts +system.physmem.perBankRdBursts::13 125863 # Per bank write bursts +system.physmem.perBankRdBursts::14 123089 # Per bank write bursts +system.physmem.perBankRdBursts::15 123818 # Per bank write bursts +system.physmem.perBankWrBursts::0 61291 # Per bank write bursts +system.physmem.perBankWrBursts::1 61585 # Per bank write bursts +system.physmem.perBankWrBursts::2 60661 # Per bank write bursts +system.physmem.perBankWrBursts::3 61360 # Per bank write bursts +system.physmem.perBankWrBursts::4 61790 # Per bank write bursts +system.physmem.perBankWrBursts::5 63221 # Per bank write bursts +system.physmem.perBankWrBursts::6 64275 # Per bank write bursts +system.physmem.perBankWrBursts::7 65726 # Per bank write bursts +system.physmem.perBankWrBursts::8 65508 # Per bank write bursts +system.physmem.perBankWrBursts::9 65914 # Per bank write bursts +system.physmem.perBankWrBursts::10 65448 # Per bank write bursts +system.physmem.perBankWrBursts::11 65777 # Per bank write bursts +system.physmem.perBankWrBursts::12 64328 # Per bank write bursts +system.physmem.perBankWrBursts::13 64347 # Per bank write bursts +system.physmem.perBankWrBursts::14 64660 # Per bank write bursts +system.physmem.perBankWrBursts::15 64333 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 662030291500 # Total gap between requests +system.physmem.totGap 672881423000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1969157 # Read request sizes (log2) +system.physmem.readPktSize::6 1969171 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1020337 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1619145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 248303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 76115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020253 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1621016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 243733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 72507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 63086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 64414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,142 +193,143 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1776224 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.667141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.863857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 136.742577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1381396 77.77% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271071 15.26% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53950 3.04% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21226 1.20% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12955 0.73% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6597 0.37% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5003 0.28% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3759 0.21% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20267 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1776224 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59925 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.795728 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 163.660245 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59887 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1777587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.583217 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.835342 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 136.553801 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1382839 77.79% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271264 15.26% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53815 3.03% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21128 1.19% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12924 0.73% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6598 0.37% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5024 0.28% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3881 0.22% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20114 1.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1777587 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59878 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.821905 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.087941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59840 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59925 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59925 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.026383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.985304 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.212732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 31950 53.32% 53.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1595 2.66% 55.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 20819 34.74% 90.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4577 7.64% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 750 1.25% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 154 0.26% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 27 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 19 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 59878 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.038378 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.996376 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.234472 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31771 53.06% 53.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1453 2.43% 55.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20992 35.06% 90.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4585 7.66% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 809 1.35% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 191 0.32% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 14 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59925 # Writes before turning the bus around for reads -system.physmem.totQLat 40790268000 # Total ticks spent queuing -system.physmem.totMemAccLat 77688280500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9839470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20727.88 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::52 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59878 # Writes before turning the bus around for reads +system.physmem.totQLat 40967898000 # Total ticks spent queuing +system.physmem.totMemAccLat 77866023000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9839500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20818.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39477.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 190.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 98.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 190.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 98.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39568.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 187.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 97.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 187.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 97.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.26 # Data bus utilization in percentage -system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.22 # Data bus utilization in percentage +system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing -system.physmem.readRowHits 795786 # Number of row buffer hits during reads -system.physmem.writeRowHits 416180 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.79 # Row buffer hit rate for writes -system.physmem.avgGap 221452.29 # Average gap between requests -system.physmem.pageHitRate 40.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6511261680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3552771750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7409259000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3239617680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 299928124440 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134120853750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 498002202300 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.239455 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 221171423750 # Time in different power states -system.physmem_0.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing +system.physmem.readRowHits 794560 # Number of row buffer hits during reads +system.physmem.writeRowHits 415972 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes +system.physmem.avgGap 225087.32 # Average gap between requests +system.physmem.pageHitRate 40.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6515684280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3555184875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7409165400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3239410320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 305964835695 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 135337912500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 505971439710 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.948773 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 223158478000 # Time in different power states +system.physmem_0.memoryStateTime::REF 22468940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 418748256250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 427253308500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6916946400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3774127500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7939518600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3371965200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 306633623535 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 128238837000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 500115332235 # Total energy per rank (pJ) -system.physmem_1.averagePower 755.431368 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 211341940750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_1.actEnergy 6922850760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3777349125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7940244000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3371641200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 312976099035 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 129187681500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 508125112260 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.149450 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 212887456750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22468940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 428577885750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 437523815750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 410531758 # Number of BP lookups -system.cpu.branchPred.condPredicted 318847451 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16269165 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 283137932 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279377578 # Number of BTB hits +system.cpu.branchPred.lookups 410709882 # Number of BP lookups +system.cpu.branchPred.condPredicted 318998342 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16277823 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282986544 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279468528 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.671900 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26373623 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.756826 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26379180 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646133385 # DTB read hits -system.cpu.dtb.read_misses 12154937 # DTB read misses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 658288322 # DTB read accesses -system.cpu.dtb.write_hits 218173916 # DTB write hits -system.cpu.dtb.write_misses 7514058 # DTB write misses +system.cpu.dtb.read_hits 646309229 # DTB read hits +system.cpu.dtb.read_misses 12154225 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 658463454 # DTB read accesses +system.cpu.dtb.write_hits 218201258 # DTB write hits +system.cpu.dtb.write_misses 7510092 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225687974 # DTB write accesses -system.cpu.dtb.data_hits 864307301 # DTB hits -system.cpu.dtb.data_misses 19668995 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 883976296 # DTB accesses -system.cpu.itb.fetch_hits 422458110 # ITB hits -system.cpu.itb.fetch_misses 45 # ITB misses +system.cpu.dtb.write_accesses 225711350 # DTB write accesses +system.cpu.dtb.data_hits 864510487 # DTB hits +system.cpu.dtb.data_misses 19664317 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 884174804 # DTB accesses +system.cpu.itb.fetch_hits 422619736 # ITB hits +system.cpu.itb.fetch_misses 46 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422458155 # ITB accesses +system.cpu.itb.fetch_accesses 422619782 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -342,238 +343,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1324060763 # number of cpu cycles simulated +system.cpu.numCycles 1345763040 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433748906 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3419441963 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410531758 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305751201 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 867248304 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45995858 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1804 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422458110 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8422260 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1323997070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582666 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.157790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433914332 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3420599858 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410709882 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305847708 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 888768265 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 46015780 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1748 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422619736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8427195 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1345692377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.541888 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.149351 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 696991073 52.64% 52.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48002120 3.63% 56.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24407254 1.84% 58.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45263157 3.42% 61.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142993214 10.80% 72.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66222276 5.00% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43788088 3.31% 80.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29616004 2.24% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226713884 17.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 718495980 53.39% 53.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48031633 3.57% 56.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24393578 1.81% 58.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45267643 3.36% 62.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 143041045 10.63% 72.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66223895 4.92% 77.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43793513 3.25% 80.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29627313 2.20% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226817777 16.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1323997070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310055 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.582542 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355597650 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 384696746 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525812607 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34892959 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22997108 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62293389 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 869 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3264034948 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2192 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22997108 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373957968 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 205165673 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7731 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538730067 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183138523 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3181033284 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1755579 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18983042 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 140285341 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27927823 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2377354751 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4126620289 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4126448707 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 171581 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1345692377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305187 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.541755 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355603714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 406294583 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525817435 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34969591 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23007054 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62310888 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 895 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3264812656 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2282 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 23007054 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373973816 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212778142 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7997 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538797541 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 197127827 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181847820 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1862600 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20249864 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 150635497 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 31416943 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377870821 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4127617004 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4127447466 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 169537 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001151788 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 192 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 191 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99207749 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719206023 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272877739 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90880933 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 59162115 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2889782486 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 178 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624016708 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1570062 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1139342915 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 505618557 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 149 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1323997070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981890 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.151111 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001667858 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 209 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99280769 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719325488 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272942348 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90808423 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 59047660 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2890368727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624396643 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1584497 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1140831193 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 506084435 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1345692377 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.950220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.146970 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 519747645 39.26% 39.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169377682 12.79% 52.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158338012 11.96% 64.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149173722 11.27% 75.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126185648 9.53% 84.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84437665 6.38% 91.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68199937 5.15% 96.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33982775 2.57% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14553984 1.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 540762104 40.18% 40.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169795677 12.62% 52.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158437148 11.77% 64.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149383051 11.10% 75.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126329288 9.39% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84501883 6.28% 91.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68040537 5.06% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34033784 2.53% 98.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14408905 1.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1323997070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1345692377 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13171575 35.70% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19111155 51.80% 87.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4612971 12.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13165371 35.79% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19036657 51.75% 87.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4585623 12.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719329788 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 125 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719509054 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 895316 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 672939161 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230852080 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896832 0.03% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 164 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 25 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 673114194 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230876222 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624016708 # Type of FU issued -system.cpu.iq.rate 1.981795 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36895701 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014061 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6608517036 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4027973051 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2521923586 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1979213 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1297888 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 892539 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2659929620 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 982789 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69543206 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624396643 # Type of FU issued +system.cpu.iq.rate 1.950118 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36787651 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014018 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6630876089 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4030049566 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2522176401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1981722 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1296863 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 893189 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2660200136 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 984158 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69569005 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274610360 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379362 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 147727 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112149237 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274729825 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379855 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 148630 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112213846 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6023017 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 321 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6130129 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22997108 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 147758887 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18474565 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3040988458 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6691344 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719206023 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272877739 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 178 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 822290 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17921565 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 147727 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10901488 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8843129 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19744617 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2578330269 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658288327 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45686439 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23007054 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 150994559 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20053347 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3041642230 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6687101 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719325488 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272942348 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 819254 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19491023 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 148630 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10888571 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8843177 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19731748 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578706854 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658463458 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45689789 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151205794 # number of nop insts executed -system.cpu.iew.exec_refs 883976375 # number of memory reference insts executed -system.cpu.iew.exec_branches 315983093 # Number of branches executed -system.cpu.iew.exec_stores 225688048 # Number of stores executed -system.cpu.iew.exec_rate 1.947290 # Inst execution rate -system.cpu.iew.wb_sent 2552817971 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2522816125 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489246506 # num instructions producing a value -system.cpu.iew.wb_consumers 1920479792 # num instructions consuming a value +system.cpu.iew.exec_nop 151273322 # number of nop insts executed +system.cpu.iew.exec_refs 884174883 # number of memory reference insts executed +system.cpu.iew.exec_branches 315972780 # Number of branches executed +system.cpu.iew.exec_stores 225711425 # Number of stores executed +system.cpu.iew.exec_rate 1.916167 # Inst execution rate +system.cpu.iew.wb_sent 2553063246 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2523069590 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489308587 # num instructions producing a value +system.cpu.iew.wb_consumers 1920703402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.905363 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775455 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874825 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775397 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005136223 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005912526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16268344 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1185116972 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.535528 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.558449 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16276987 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1206693157 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.508072 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.543192 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 695949152 58.72% 58.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159874809 13.49% 72.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79784402 6.73% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52116706 4.40% 83.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28440614 2.40% 85.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19407125 1.64% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20027045 1.69% 89.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23110908 1.95% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106406211 8.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 717446911 59.46% 59.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159887401 13.25% 72.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79830197 6.62% 79.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52027392 4.31% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28503242 2.36% 85.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19553290 1.62% 87.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20023421 1.66% 89.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23140213 1.92% 91.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106281090 8.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1185116972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1206693157 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -619,339 +620,341 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106406211 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106281090 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3817847910 # The number of ROB reads -system.cpu.rob.rob_writes 5788846951 # The number of ROB writes -system.cpu.timesIdled 724 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 63693 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3840325519 # The number of ROB reads +system.cpu.rob.rob_writes 5790523687 # The number of ROB writes +system.cpu.timesIdled 690 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 70663 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.762689 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.762689 # CPI: Total CPI of All Threads -system.cpu.ipc 1.311151 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.311151 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3467581476 # number of integer regfile reads -system.cpu.int_regfile_writes 2022302956 # number of integer regfile writes -system.cpu.fp_regfile_reads 46080 # number of floating regfile reads -system.cpu.fp_regfile_writes 592 # number of floating regfile writes +system.cpu.cpi 0.775190 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.775190 # CPI: Total CPI of All Threads +system.cpu.ipc 1.290007 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.290007 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3468053564 # number of integer regfile reads +system.cpu.int_regfile_writes 2022530151 # number of integer regfile writes +system.cpu.fp_regfile_reads 45442 # number of floating regfile reads +system.cpu.fp_regfile_writes 563 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9209012 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.412521 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 713854428 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9213108 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.482477 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.412521 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997903 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9208756 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.479772 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713775439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9212852 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.476056 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5132407000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.479772 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997920 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 751 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2935 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 697 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2970 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1472845170 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1472845170 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 558341279 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 558341279 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155513145 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155513145 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1472909430 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472909430 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558274718 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558274718 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155500717 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155500717 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 713854424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 713854424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 713854424 # number of overall hits -system.cpu.dcache.overall_hits::total 713854424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12746245 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12746245 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5215357 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5215357 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 713775435 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713775435 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713775435 # number of overall hits +system.cpu.dcache.overall_hits::total 713775435 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12845064 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12845064 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5227785 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5227785 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17961602 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17961602 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17961602 # number of overall misses -system.cpu.dcache.overall_misses::total 17961602 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 384451562750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 384451562750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289305166008 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289305166008 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 673756728758 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 673756728758 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 673756728758 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 673756728758 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 571087524 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 18072849 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18072849 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18072849 # number of overall misses +system.cpu.dcache.overall_misses::total 18072849 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 414536288750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 414536288750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 316664843212 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 316664843212 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 731201131962 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 731201131962 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 731201131962 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 731201131962 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571119782 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571119782 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 731816026 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 731816026 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 731816026 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 731816026 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032448 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 731848284 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731848284 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731848284 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731848284 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022491 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022491 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032526 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032526 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024544 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024544 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024544 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024544 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30161.946734 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30161.946734 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55471.785730 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55471.785730 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37510.948564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37510.948564 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14120110 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8634302 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1055091 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67341 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.382836 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 128.217609 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.024695 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024695 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024695 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024695 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32272.029844 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32272.029844 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60573.425114 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60573.425114 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40458.542644 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40458.542644 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40458.542644 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40458.542644 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15275634 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9588635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1068737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67992 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.293165 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 141.025930 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3742780 # number of writebacks -system.cpu.dcache.writebacks::total 3742780 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412238 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5412238 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3336257 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3336257 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8748495 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8748495 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8748495 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8748495 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334007 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334007 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879100 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3742849 # number of writebacks +system.cpu.dcache.writebacks::total 3742849 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5511228 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5511228 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3348770 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3348770 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8859998 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8859998 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8859998 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8859998 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333836 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333836 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879015 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879015 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9213107 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9213107 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9213107 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9213107 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168659488250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168659488250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77208966781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77208966781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245868455031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245868455031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245868455031 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245868455031 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9212851 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9212851 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9212851 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9212851 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180521790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 180521790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83364623703 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83364623703 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263886414453 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 263886414453 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263886414453 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 263886414453 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012841 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012841 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22996.908545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22996.908545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41088.269268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41088.269268 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012588 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012588 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012588 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012588 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24614.920589 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24614.920589 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.129969 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.129969 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28643.295594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28643.295594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28643.295594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28643.295594 # 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Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376054 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376054 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 773.497223 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377684 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377684 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 974 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 899 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 844917184 # Number of tag accesses -system.cpu.icache.tags.data_accesses 844917184 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422456585 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422456585 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422456585 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422456585 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422456585 # number of overall hits -system.cpu.icache.overall_hits::total 422456585 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1524 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1524 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1524 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1524 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1524 # number of overall misses -system.cpu.icache.overall_misses::total 1524 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 107000999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 107000999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 107000999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 107000999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 107000999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 107000999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 422458109 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422458109 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422458109 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422458109 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422458109 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422458109 # 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number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1542 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1542 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1542 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1542 # number of overall misses +system.cpu.icache.overall_misses::total 1542 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 116278500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 116278500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 116278500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 116278500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 116278500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 116278500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 422619736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 422619736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 422619736 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 422619736 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 422619736 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 422619736 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70210.629265 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70210.629265 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70210.629265 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70210.629265 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 469 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75407.587549 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75407.587549 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75407.587549 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75407.587549 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75407.587549 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75407.587549 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 435 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.142857 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 558 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 558 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 558 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 558 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 558 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 558 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72141249 # 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number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 975 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 975 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79199000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 79199000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79199000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 79199000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79199000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 79199000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74680.381988 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74680.381988 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81229.743590 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81229.743590 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81229.743590 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 81229.743590 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81229.743590 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 81229.743590 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1936441 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31406.538176 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9110982 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1966231 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.633729 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 27876136750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14557.398525 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.847630 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.292021 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.444257 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513376 # 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number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3742780 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3742780 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1107826 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107826 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7244917 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7244917 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7244917 # number of overall hits -system.cpu.l2cache.overall_hits::total 7244917 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1196905 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1197871 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 771286 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 771286 # 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average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82599.592755 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82599.592755 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82608.467353 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82608.467353 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.213636 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.213719 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80220.512821 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 90035.906632 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 90027.917310 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89856.827119 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89856.827119 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80220.512821 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89965.726737 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89960.901567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80220.512821 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89965.726737 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89960.901567 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -960,105 +963,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1020337 # number of writebacks -system.cpu.l2cache.writebacks::total 1020337 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196905 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1197871 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771286 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 771286 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1968191 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1969157 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1968191 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1969157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58998750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83895775000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83954773750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54083955498 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54083955498 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58998750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137979730498 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138038729248 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58998750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137979730498 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138038729248 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1020253 # number of writebacks +system.cpu.l2cache.writebacks::total 1020253 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196875 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1197850 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59593481750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59593481750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 152252506500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 152318536000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66029500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 152252506500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 152318536000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163310 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410452 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410452 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163199 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163311 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410489 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410489 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.213712 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213636 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.213719 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67722.564103 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77417.461932 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77409.570689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77261.583374 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77261.583374 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7334962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7334962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3742780 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879112 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879112 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22170928 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829176832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 829238656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7334797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7334797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879030 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1950 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22170503 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829164864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 829227264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12957003 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12956676 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12957003 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12956676 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12957003 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10221354853 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12956676 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10221187000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1610750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14117356000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14136511250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1197871 # Transaction distribution -system.membus.trans_dist::ReadResp 1197871 # Transaction distribution -system.membus.trans_dist::Writeback 1020337 # Transaction distribution -system.membus.trans_dist::ReadExReq 771286 # Transaction distribution -system.membus.trans_dist::ReadExResp 771286 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4958651 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191327616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1197850 # Transaction distribution +system.membus.trans_dist::ReadResp 1197850 # Transaction distribution +system.membus.trans_dist::Writeback 1020253 # Transaction distribution +system.membus.trans_dist::ReadExReq 771321 # Transaction distribution +system.membus.trans_dist::ReadExResp 771321 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958595 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4958595 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191323136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191323136 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2989494 # Request fanout histogram +system.membus.snoop_fanout::samples 2989424 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2989494 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2989424 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2989494 # Request fanout histogram -system.membus.reqLayer0.occupancy 11823428000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 18423304250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.8 # Layer utilization (%) +system.membus.snoop_fanout::total 2989424 # Request fanout histogram +system.membus.reqLayer0.occupancy 7771933000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 10726595500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 2d7afdf8e..6346aa78f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.623386 # Number of seconds simulated -sim_ticks 2623386226000 # Number of ticks simulated -final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.623365 # Number of seconds simulated +sim_ticks 2623365440500 # Number of ticks simulated +final_tick 2623365440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1656263 # Simulator instruction rate (inst/s) -host_op_rate 1656263 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2387660297 # Simulator tick rate (ticks/s) -host_mem_usage 289632 # Number of bytes of host memory used -host_seconds 1098.73 # Real time elapsed on the host +host_inst_rate 1411989 # Simulator instruction rate (inst/s) +host_op_rate 1411989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2035500124 # Simulator tick rate (ticks/s) +host_mem_usage 294160 # Number of bytes of host memory used +host_seconds 1288.81 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,40 +26,16 @@ system.physmem.num_reads::total 1959663 # Nu system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47788276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47807841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47788654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47808220 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24836956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24836956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24836956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 24837153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24837153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24837153 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1178362 # Transaction distribution -system.membus.trans_dist::ReadResp 1178362 # Transaction distribution -system.membus.trans_dist::Writeback 1018077 # Transaction distribution -system.membus.trans_dist::ReadExReq 781301 # Transaction distribution -system.membus.trans_dist::ReadExResp 781301 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2977740 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2977740 # Request fanout histogram -system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.physmem.bw_total::cpu.data 47788654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72645373 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5246772452 # number of cpu cycles simulated +system.cpu.numCycles 5246730881 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -113,7 +89,7 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5246772452 # Number of busy cycles +system.cpu.num_busy_cycles 5246730881 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched @@ -152,13 +128,122 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.cpu.dcache.tags.replacements 9107638 # number of replacements +system.cpu.dcache.tags.tagsinuse 4079.262739 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40977437000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262739 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits +system.cpu.dcache.overall_hits::total 596212431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses +system.cpu.dcache.overall_misses::total 9111734 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143355355000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143355355000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57375808000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57375808000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200731163000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200731163000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200731163000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200731163000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19848.675941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19848.675941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30368.496602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30368.496602 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22029.963013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22029.963013 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks +system.cpu.dcache.writebacks::total 3693497 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132521734000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 132521734000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54541828000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 54541828000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187063562000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 187063562000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187063562000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187063562000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18348.675941 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18348.675941 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28868.496602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28868.496602 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 612.458786 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 612.458786 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id @@ -179,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44182000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44182000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44182000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44182000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44182000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44182000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44139500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44139500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44139500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44139500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44139500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44139500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -197,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55089.775561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55089.775561 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55089.775561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55089.775561 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55036.783042 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55036.783042 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55036.783042 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55036.783042 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,43 +302,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42578000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42578000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42936500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42936500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42936500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42936500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42936500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42936500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53089.775561 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53089.775561 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.783042 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53536.783042 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53536.783042 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53536.783042 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926937 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30535.253333 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 218167126000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15221.864156 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064589 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.324589 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.464534 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1059 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1253 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27303 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 106294313 # Number of tag accesses @@ -279,17 +364,17 @@ system.cpu.l2cache.demand_misses::total 1959663 # nu system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958861 # number of overall misses system.cpu.l2cache.overall_misses::total 1959663 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41776000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61258944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61300720000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40629030000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40629030000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41776000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101887974000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101929750000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41776000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101887974000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101929750000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42134500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61828353000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61870487500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018308500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41018308500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42134500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102846661500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102888796000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42134500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102846661500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102888796000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses) @@ -314,17 +399,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215051 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214982 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215051 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52089.775561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52021.930093 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52021.976269 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.763725 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.763725 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52013.917699 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52013.917699 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52536.783042 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52505.479976 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52505.501281 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007679 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007679 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52536.783042 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52503.297324 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52503.311028 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52536.783042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52503.297324 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52503.311028 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,17 +431,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959663 system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958861 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1959663 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32152000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47128224000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47160376000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31253418000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31253418000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32152000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78381642000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78413794000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32152000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78381642000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78413794000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32510000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47697633000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47730143000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31642696500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31642696500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32510000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79340329500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 79372839500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32510000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79340329500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 79372839500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163042 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163135 # mshr miss rate for ReadReq accesses @@ -368,127 +453,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215051 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215051 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40089.775561 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.930093 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.976269 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.763725 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.763725 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40536.159601 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40505.479976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40505.500856 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007679 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007679 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40536.159601 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40503.297324 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.310773 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40536.159601 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40503.297324 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.310773 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1238 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits -system.cpu.dcache.overall_hits::total 596212431 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses -system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks -system.cpu.dcache.writebacks::total 3693497 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution @@ -518,5 +494,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 1203000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1178362 # Transaction distribution +system.membus.trans_dist::ReadResp 1178362 # Transaction distribution +system.membus.trans_dist::Writeback 1018077 # Transaction distribution +system.membus.trans_dist::ReadExReq 781301 # Transaction distribution +system.membus.trans_dist::ReadExResp 781301 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2977740 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2977740 # Request fanout histogram +system.membus.reqLayer0.occupancy 7156873500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9798315500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |