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authorCurtis Dunham <Curtis.Dunham@arm.com>2016-07-21 17:19:18 +0100
committerCurtis Dunham <Curtis.Dunham@arm.com>2016-07-21 17:19:18 +0100
commit84f138ba96201431513eb2ae5f847389ac731aa2 (patch)
tree3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/se/60.bzip2/ref/alpha
parenta288c94387b110112461ff5686fa727a43ddbe9c (diff)
downloadgem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz
stats: update references
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha')
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini90
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr2
-rwxr-xr-x[-rw-r--r--]tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout11
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt1118
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini89
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr1
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout10
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt12
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini27
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr1
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout11
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt11
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini82
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr1
-rwxr-xr-xtests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout13
-rw-r--r--tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt12
16 files changed, 882 insertions, 609 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
index dc295a8fa..10131fd38 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
@@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +26,16 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -55,6 +64,7 @@ decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -97,12 +107,17 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
+threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -118,11 +133,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
@@ -130,13 +152,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -146,6 +173,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -154,8 +182,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -553,13 +586,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -569,6 +607,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -577,8 +616,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -602,13 +646,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -618,6 +667,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -626,19 +676,31 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -646,6 +708,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@@ -660,7 +729,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
kvmInSE=false
@@ -692,9 +761,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -738,6 +813,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -749,7 +825,11 @@ max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
page_policy=open_adaptive
+power_model=Null
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr
index de77515a1..e0bca4e4e 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr
@@ -1,4 +1,6 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout
index f1d88cff2..cd35cd53a 100644..100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout
@@ -3,10 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-t
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:41:53
-gem5 started May 7 2014 12:11:11
-gem5 executing on cz3212c2d7
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:29
+gem5 executing on e108600-lin, pid 4307
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/minor-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -25,4 +26,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1184839137500 because target called exit()
+Exiting @ tick 1219570622500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index e74f79662..096e1a113 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,106 +1,106 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.208778 # Number of seconds simulated
-sim_ticks 1208777694500 # Number of ticks simulated
-final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.219571 # Number of seconds simulated
+sim_ticks 1219570622500 # Number of ticks simulated
+final_tick 1219570622500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 530685 # Simulator instruction rate (inst/s)
-host_op_rate 530685 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 351230785 # Simulator tick rate (ticks/s)
-host_mem_usage 297332 # Number of bytes of host memory used
-host_seconds 3441.55 # Real time elapsed on the host
+host_inst_rate 313924 # Simulator instruction rate (inst/s)
+host_op_rate 313924 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 209623743 # Simulator tick rate (ticks/s)
+host_mem_usage 249764 # Number of bytes of host memory used
+host_seconds 5817.90 # Real time elapsed on the host
sim_insts 1826378509 # Number of instructions simulated
sim_ops 1826378509 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 124970112 # Number of bytes read from this memory
-system.physmem.bytes_read::total 125031424 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65416896 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65416896 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1952658 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1953616 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1022139 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1022139 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 50722 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 103385521 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 103436244 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 50722 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 50722 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 54118219 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 54118219 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 54118219 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 50722 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 103385521 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 157554463 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1953616 # Number of read requests accepted
-system.physmem.writeReqs 1022139 # Number of write requests accepted
-system.physmem.readBursts 1953616 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1022139 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 124948416 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 83008 # Total number of bytes read from write queue
-system.physmem.bytesWritten 65415616 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 125031424 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 65416896 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 1297 # Number of DRAM read bursts serviced by the write queue
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 124970496 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125032128 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65417280 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65417280 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1952664 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1953627 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1022145 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1022145 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 50536 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 102470897 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 102521433 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 50536 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 50536 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 53639600 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 53639600 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 53639600 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 50536 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 102470897 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 156161033 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1953627 # Number of read requests accepted
+system.physmem.writeReqs 1022145 # Number of write requests accepted
+system.physmem.readBursts 1953627 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1022145 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 124950016 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 82112 # Total number of bytes read from write queue
+system.physmem.bytesWritten 65416064 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 125032128 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 65417280 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1283 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 118316 # Per bank write bursts
-system.physmem.perBankRdBursts::1 113525 # Per bank write bursts
-system.physmem.perBankRdBursts::2 115740 # Per bank write bursts
-system.physmem.perBankRdBursts::3 117258 # Per bank write bursts
-system.physmem.perBankRdBursts::4 117310 # Per bank write bursts
-system.physmem.perBankRdBursts::5 117126 # Per bank write bursts
-system.physmem.perBankRdBursts::6 119402 # Per bank write bursts
-system.physmem.perBankRdBursts::7 124113 # Per bank write bursts
-system.physmem.perBankRdBursts::8 126650 # Per bank write bursts
+system.physmem.perBankRdBursts::0 118315 # Per bank write bursts
+system.physmem.perBankRdBursts::1 113533 # Per bank write bursts
+system.physmem.perBankRdBursts::2 115749 # Per bank write bursts
+system.physmem.perBankRdBursts::3 117256 # Per bank write bursts
+system.physmem.perBankRdBursts::4 117296 # Per bank write bursts
+system.physmem.perBankRdBursts::5 117124 # Per bank write bursts
+system.physmem.perBankRdBursts::6 119398 # Per bank write bursts
+system.physmem.perBankRdBursts::7 124125 # Per bank write bursts
+system.physmem.perBankRdBursts::8 126652 # Per bank write bursts
system.physmem.perBankRdBursts::9 129582 # Per bank write bursts
-system.physmem.perBankRdBursts::10 128169 # Per bank write bursts
-system.physmem.perBankRdBursts::11 129917 # Per bank write bursts
-system.physmem.perBankRdBursts::12 125580 # Per bank write bursts
-system.physmem.perBankRdBursts::13 124837 # Per bank write bursts
-system.physmem.perBankRdBursts::14 122150 # Per bank write bursts
-system.physmem.perBankRdBursts::15 122644 # Per bank write bursts
-system.physmem.perBankWrBursts::0 61421 # Per bank write bursts
-system.physmem.perBankWrBursts::1 61661 # Per bank write bursts
-system.physmem.perBankWrBursts::2 60724 # Per bank write bursts
-system.physmem.perBankWrBursts::3 61398 # Per bank write bursts
-system.physmem.perBankWrBursts::4 61819 # Per bank write bursts
-system.physmem.perBankWrBursts::5 63309 # Per bank write bursts
-system.physmem.perBankWrBursts::6 64356 # Per bank write bursts
-system.physmem.perBankWrBursts::7 65855 # Per bank write bursts
-system.physmem.perBankWrBursts::8 65577 # Per bank write bursts
-system.physmem.perBankWrBursts::9 66031 # Per bank write bursts
-system.physmem.perBankWrBursts::10 65643 # Per bank write bursts
-system.physmem.perBankWrBursts::11 65945 # Per bank write bursts
-system.physmem.perBankWrBursts::12 64508 # Per bank write bursts
-system.physmem.perBankWrBursts::13 64526 # Per bank write bursts
+system.physmem.perBankRdBursts::10 128170 # Per bank write bursts
+system.physmem.perBankRdBursts::11 129930 # Per bank write bursts
+system.physmem.perBankRdBursts::12 125581 # Per bank write bursts
+system.physmem.perBankRdBursts::13 124839 # Per bank write bursts
+system.physmem.perBankRdBursts::14 122149 # Per bank write bursts
+system.physmem.perBankRdBursts::15 122645 # Per bank write bursts
+system.physmem.perBankWrBursts::0 61422 # Per bank write bursts
+system.physmem.perBankWrBursts::1 61664 # Per bank write bursts
+system.physmem.perBankWrBursts::2 60725 # Per bank write bursts
+system.physmem.perBankWrBursts::3 61395 # Per bank write bursts
+system.physmem.perBankWrBursts::4 61816 # Per bank write bursts
+system.physmem.perBankWrBursts::5 63307 # Per bank write bursts
+system.physmem.perBankWrBursts::6 64357 # Per bank write bursts
+system.physmem.perBankWrBursts::7 65854 # Per bank write bursts
+system.physmem.perBankWrBursts::8 65580 # Per bank write bursts
+system.physmem.perBankWrBursts::9 66032 # Per bank write bursts
+system.physmem.perBankWrBursts::10 65645 # Per bank write bursts
+system.physmem.perBankWrBursts::11 65946 # Per bank write bursts
+system.physmem.perBankWrBursts::12 64510 # Per bank write bursts
+system.physmem.perBankWrBursts::13 64527 # Per bank write bursts
system.physmem.perBankWrBursts::14 64900 # Per bank write bursts
system.physmem.perBankWrBursts::15 64446 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 1208777578000 # Total gap between requests
+system.physmem.totGap 1219570506500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1953616 # Read request sizes (log2)
+system.physmem.readPktSize::6 1953627 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1022139 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1830097 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 122205 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1022145 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1833407 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 118928 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -145,35 +145,35 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 30602 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 32045 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 55307 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 59695 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 60116 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 60223 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 60190 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 60196 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 60182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 60140 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 60199 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 60169 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 60684 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 61042 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 60657 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 61101 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 59828 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 59617 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 30664 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 32017 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 55394 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 59725 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 60150 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 60160 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 60171 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 60164 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 60165 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 60205 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 60270 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 60241 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 60697 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 61009 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 60531 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 61008 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 59822 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 59630 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 89 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
@@ -194,31 +194,31 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1831457 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 103.940817 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 81.136003 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 130.529919 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 1452947 79.33% 79.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 261995 14.31% 93.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 48664 2.66% 96.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 20593 1.12% 97.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 13175 0.72% 98.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 7238 0.40% 98.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5438 0.30% 98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 4580 0.25% 99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16827 0.92% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1831457 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 59614 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 32.747643 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 146.947369 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511 59453 99.73% 99.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023 115 0.19% 99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535 9 0.02% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047 9 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-3071 3 0.01% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095 3 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 1832533 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 103.880589 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 81.106196 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 130.417770 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 1454670 79.38% 79.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 261169 14.25% 93.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 48917 2.67% 96.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 20611 1.12% 97.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 13239 0.72% 98.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 7059 0.39% 98.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5499 0.30% 98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 4584 0.25% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16785 0.92% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1832533 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 59623 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 32.744209 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 148.154914 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 59464 99.73% 99.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023 114 0.19% 99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559 6 0.01% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071 5 0.01% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095 4 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
@@ -226,109 +226,107 @@ system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # R
system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 59614 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 59614 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.145620 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.109391 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.119268 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 27453 46.05% 46.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1268 2.13% 48.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 26337 44.18% 92.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 4007 6.72% 99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 455 0.76% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 71 0.12% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 15 0.03% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 59614 # Writes before turning the bus around for reads
-system.physmem.totQLat 36537628750 # Total ticks spent queuing
-system.physmem.totMemAccLat 73143610000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 9761595000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 18714.99 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 59623 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 59623 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.143149 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.107238 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.113236 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 27459 46.05% 46.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 1251 2.10% 48.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 26456 44.37% 92.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 3936 6.60% 99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 436 0.73% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 70 0.12% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 3 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 59623 # Writes before turning the bus around for reads
+system.physmem.totQLat 36415699500 # Total ticks spent queuing
+system.physmem.totMemAccLat 73022149500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 9761720000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 18652.30 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 37464.99 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 103.37 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 54.12 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 103.44 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 54.12 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 37402.30 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 102.45 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 53.64 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 102.52 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 53.64 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 1.23 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads
+system.physmem.busUtil 1.22 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.80 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing
-system.physmem.readRowHits 723773 # Number of row buffer hits during reads
-system.physmem.writeRowHits 419204 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 41.01 # Row buffer hit rate for writes
-system.physmem.avgGap 406208.70 # Average gap between requests
-system.physmem.pageHitRate 38.43 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 6714376200 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 3663598125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 7353738600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3243518640 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 78951397200 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 415074736440 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 361165338750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 876166703955 # Total energy per rank (pJ)
-system.physmem_0.averagePower 724.837554 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 598070170000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 40363700000 # Time in different power states
+system.physmem.avgWrQLen 24.66 # Average write queue length when enqueuing
+system.physmem.readRowHits 723035 # Number of row buffer hits during reads
+system.physmem.writeRowHits 418897 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 37.03 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 40.98 # Row buffer hit rate for writes
+system.physmem.avgGap 409833.32 # Average gap between requests
+system.physmem.pageHitRate 38.39 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 6719093640 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 3666172125 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 7353785400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3243499200 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 79656261360 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 415707006375 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 367085761500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 883431579600 # Total energy per rank (pJ)
+system.physmem_0.averagePower 724.380520 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 607907659750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 40724060000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 570342873000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 570937965250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 7131423600 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 3891153750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 7874224800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3379812480 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 78951397200 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 426560774805 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 351089866500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 878878653135 # Total energy per rank (pJ)
-system.physmem_1.averagePower 727.081103 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 581228871000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 40363700000 # Time in different power states
+system.physmem_1.actEnergy 7134833160 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 3893014125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 7874240400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3379877280 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 79656261360 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 426752022060 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 357397152750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 886087401135 # Total energy per rank (pJ)
+system.physmem_1.averagePower 726.558192 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 591710247250 # Time in different power states
+system.physmem_1.memoryStateTime::REF 40724060000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 587184084000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 587134092250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 246097965 # Number of BP lookups
-system.cpu.branchPred.condPredicted 186356162 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 15588061 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 167640085 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 165196337 # Number of BTB hits
+system.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 246937199 # Number of BP lookups
+system.cpu.branchPred.condPredicted 186891611 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15587043 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 168278704 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 165579614 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.542265 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 18413332 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 104391 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 297 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 67 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 230 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 98 # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct 98.396060 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 18556464 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 106119 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 314 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 63 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 251 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 452860657 # DTB read hits
-system.cpu.dtb.read_misses 4979867 # DTB read misses
+system.cpu.dtb.read_hits 453406129 # DTB read hits
+system.cpu.dtb.read_misses 5001511 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 457840524 # DTB read accesses
-system.cpu.dtb.write_hits 161378231 # DTB write hits
-system.cpu.dtb.write_misses 1709431 # DTB write misses
+system.cpu.dtb.read_accesses 458407640 # DTB read accesses
+system.cpu.dtb.write_hits 161376524 # DTB write hits
+system.cpu.dtb.write_misses 1709205 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 163087662 # DTB write accesses
-system.cpu.dtb.data_hits 614238888 # DTB hits
-system.cpu.dtb.data_misses 6689298 # DTB misses
+system.cpu.dtb.write_accesses 163085729 # DTB write accesses
+system.cpu.dtb.data_hits 614782653 # DTB hits
+system.cpu.dtb.data_misses 6710716 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 620928186 # DTB accesses
-system.cpu.itb.fetch_hits 597989612 # ITB hits
+system.cpu.dtb.data_accesses 621493369 # DTB accesses
+system.cpu.itb.fetch_hits 600073027 # ITB hits
system.cpu.itb.fetch_misses 19 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 597989631 # ITB accesses
+system.cpu.itb.fetch_accesses 600073046 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -342,16 +340,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 1208777694500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 2417555389 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 1219570622500 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 2439141245 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1826378509 # Number of instructions committed
system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 51811935 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 55113124 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.323688 # CPI: cycles per instruction
-system.cpu.ipc 0.755465 # IPC: instructions per cycle
+system.cpu.cpi 1.335507 # CPI: cycles per instruction
+system.cpu.ipc 0.748779 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction
system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction
system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction
@@ -387,176 +385,176 @@ system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 1826378509 # Class of committed instruction
-system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 9121974 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9126070 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 65.914337 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 16821281500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4080.726355 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.996271 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy
+system.cpu.tickCycles 2082121954 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 357019291 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements 9121976 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4080.816467 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 602780801 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 9126072 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 66.050410 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 16880243500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4080.816467 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.996293 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.996293 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1562 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2407 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 1561 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 2409 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 158481991 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 601538856 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 601538856 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 601538856 # number of overall hits
-system.cpu.dcache.overall_hits::total 601538856 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7289538 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7289538 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2246511 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2246511 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 9536049 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 9536049 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 185480529000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 185480529000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 108417025500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 108417025500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 293897554500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 293897554500 # number of demand (read+write) miss cycles
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-system.cpu.dcache.overall_miss_latency::total 293897554500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 450346403 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 450346403 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses 1233657814 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1233657814 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states
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system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 611074905 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 611074905 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016187 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013977 # miss rate for WriteReq accesses
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-system.cpu.dcache.overall_miss_rate::cpu.data 0.015605 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.015605 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25444.757816 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25444.757816 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48260.180119 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48260.180119 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30819.635522 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30819.635522 # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data 612265871 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 612265871 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 612265871 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 612265871 # number of overall (read+write) accesses
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+system.cpu.dcache.overall_miss_rate::total 0.015492 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25427.036955 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25427.036955 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48313.651536 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48313.651536 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30846.351846 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30846.351846 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30846.351846 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30846.351846 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 3686603 # number of writebacks
-system.cpu.dcache.writebacks::total 3686603 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50808 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 50808 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359171 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 359171 # number of WriteReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::total 409979 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 409979 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 409979 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238730 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7238730 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887340 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1887340 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9126070 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9126070 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9126070 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9126070 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 177011068000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 177011068000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83258719000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 83258719000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260269787000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 260269787000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260269787000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 260269787000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016074 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016074 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks 3686661 # number of writebacks
+system.cpu.dcache.writebacks::total 3686661 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 370 # number of ReadReq MSHR hits
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+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1272 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp 7239696 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 4708806 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 6334123 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1887340 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1887340 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 958 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238730 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374114 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 27376033 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61504 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820011072 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 820072576 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 1920891 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 11047919 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::CleanEvict 6334072 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1887339 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1887339 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 963 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238733 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1929 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374120 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 27376049 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820014912 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 820076736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 1920902 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 65417280 # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples 11047937 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.010713 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.010729 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 11046651 99.99% 99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 1268 0.01% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 11046665 99.99% 99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 1272 0.01% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 11047919 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 12811108500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 11047937 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 12811171000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1437000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1444500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 13689105000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 13689108000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 1173106 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1022139 # Transaction distribution
-system.membus.trans_dist::CleanEvict 897726 # Transaction distribution
-system.membus.trans_dist::ReadExReq 780510 # Transaction distribution
-system.membus.trans_dist::ReadExResp 780510 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1173106 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827097 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5827097 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190448320 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 190448320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp 1173115 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1022145 # Transaction distribution
+system.membus.trans_dist::CleanEvict 897727 # Transaction distribution
+system.membus.trans_dist::ReadExReq 780512 # Transaction distribution
+system.membus.trans_dist::ReadExResp 780512 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 1173115 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827126 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5827126 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190449408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 190449408 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3873481 # Request fanout histogram
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 3873499 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3873481 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3873499 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3873481 # Request fanout histogram
-system.membus.reqLayer0.occupancy 8428417500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3873499 # Request fanout histogram
+system.membus.reqLayer0.occupancy 8456520500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 10685410500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 10686565250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 88e337781..b191243cb 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +26,16 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -68,6 +77,7 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
+default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -104,6 +114,10 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -143,11 +157,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
@@ -155,13 +176,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -171,6 +197,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -179,8 +206,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -502,13 +534,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -518,6 +555,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -526,8 +564,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -551,13 +594,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -567,6 +615,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -575,19 +624,31 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -595,6 +656,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@@ -609,7 +677,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
kvmInSE=false
@@ -641,9 +709,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -687,6 +761,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -698,7 +773,11 @@ max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
page_policy=open_adaptive
+power_model=Null
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
index f0a9a7c93..e0bca4e4e 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
@@ -1,5 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index abe06b1e2..e33a21652 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 20:54:01
-gem5 started Sep 14 2015 21:26:54
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:29
+gem5 executing on e108600-lin, pid 4309
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -26,4 +26,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 669556582000 because target called exit()
+Exiting @ tick 669587683000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 6c06e7b34..cd08b0f17 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.669588 # Nu
sim_ticks 669587683000 # Number of ticks simulated
final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 268815 # Simulator instruction rate (inst/s)
-host_op_rate 268815 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 103681118 # Simulator tick rate (ticks/s)
-host_mem_usage 297332 # Number of bytes of host memory used
-host_seconds 6458.15 # Real time elapsed on the host
+host_inst_rate 209688 # Simulator instruction rate (inst/s)
+host_op_rate 209688 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 80876198 # Simulator tick rate (ticks/s)
+host_mem_usage 251300 # Number of bytes of host memory used
+host_seconds 8279.17 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -1059,6 +1059,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828099072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 828159872 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1929018 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 65555456 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 11141265 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000114 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.010697 # Request fanout histogram
@@ -1088,6 +1089,7 @@ system.membus.pkt_count::total 5851429 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191105728 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 191105728 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 3889706 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index d3c80bc18..346da75e3 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +26,16 @@ mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -51,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -67,6 +77,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -114,7 +128,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
kvmInSE=false
@@ -146,9 +160,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -163,11 +183,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
index de77515a1..96524c915 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 1dfd46cbe..d6f6a9638 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,13 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 18:36:30
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:29
+gem5 executing on e108600-lin, pid 4310
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/simple-atomic
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 1bae4420d..9e88e1d85 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3169811 # Simulator instruction rate (inst/s)
-host_op_rate 3169811 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1590652371 # Simulator tick rate (ticks/s)
-host_mem_usage 285272 # Number of bytes of host memory used
-host_seconds 574.10 # Real time elapsed on the host
+host_inst_rate 2010513 # Simulator instruction rate (inst/s)
+host_op_rate 2010513 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1008901575 # Simulator tick rate (ticks/s)
+host_mem_usage 239516 # Number of bytes of host memory used
+host_seconds 905.13 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -142,6 +142,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram
system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 97b7b2c5a..b0859ad68 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +26,16 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -51,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -66,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -83,13 +97,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -99,6 +118,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -107,8 +127,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -123,13 +148,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -139,6 +169,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -147,8 +178,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -172,13 +208,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -188,6 +229,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -196,19 +238,31 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -216,6 +270,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@@ -230,7 +291,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
kvmInSE=false
@@ -262,9 +323,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -279,11 +346,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
index de77515a1..96524c915 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 43eef16e9..eae87e351 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,13 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 18:44:35
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:29
+gem5 executing on e108600-lin, pid 4312
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/simple-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -23,4 +26,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2623386226000 because target called exit()
+Exiting @ tick 2636719559500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index d98d61e9c..6bd6eda32 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.636720 # Nu
sim_ticks 2636719559500 # Number of ticks simulated
final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1821657 # Simulator instruction rate (inst/s)
-host_op_rate 1821657 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2639438336 # Simulator tick rate (ticks/s)
-host_mem_usage 295280 # Number of bytes of host memory used
-host_seconds 998.97 # Real time elapsed on the host
+host_inst_rate 1223384 # Simulator instruction rate (inst/s)
+host_op_rate 1223384 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1772587765 # Simulator tick rate (ticks/s)
+host_mem_usage 249508 # Number of bytes of host memory used
+host_seconds 1487.50 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -507,6 +507,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1919525 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 65405568 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram
@@ -536,6 +537,7 @@ system.membus.pkt_count::total 5823129 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 3870887 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram