stats: Cumulative stats update

This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.

3 files changed, 136 insertions, 134 deletions

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index fe02977f3..b5eeb298e 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.017017                       # Nu
 sim_ticks                                1017016979500                       # Number of ticks simulated
 final_tick                               1017016979500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 113008                       # Simulator instruction rate (inst/s)
-host_op_rate                                   113008                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63156510                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225148                       # Number of bytes of host memory used
-host_seconds                                 16103.12                       # Real time elapsed on the host
+host_inst_rate                                  89946                       # Simulator instruction rate (inst/s)
+host_op_rate                                    89946                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               50268200                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224748                       # Number of bytes of host memory used
+host_seconds                                 20231.82                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             54976                       # Number of bytes read from this memory
@@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks          64065511                       # To
 system.physmem.bw_total::cpu.inst               54056                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data           123267606                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              187387172                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1959691                       # Total number of read requests seen
-system.physmem.writeReqs                      1018058                       # Total number of write requests seen
-system.physmem.cpureqs                        2977749                       # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs                       1959691                       # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs                      1018058                       # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts                     1959691                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts                    1018058                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
 system.physmem.bytesRead                    125420224                       # Total number of bytes read from memory
 system.physmem.bytesWritten                  65155712                       # Total number of bytes written to memory
 system.physmem.bytesConsumedRd              125420224                       # bytesRead derated as per pkt->getSize()
 system.physmem.bytesConsumedWr               65155712                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                      576                       # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ                      576                       # Number of DRAM read bursts serviced by write Q
 system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
 system.physmem.perBankRdReqs::0                118716                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::1                114074                       # Track reads on a per bank basis
@@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp            1178393                       # Tr
 system.membus.trans_dist::Writeback           1018058                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            781298                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           781298                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side      4937440                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                       4937440                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side    190575936                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                  190575936                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4937440                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4937440                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190575936                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           190575936                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus              190575936                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy         11803876500                       # Layer occupancy (ticks)
@@ -428,15 +429,15 @@ system.cpu.stage3.utilization               20.138673                       # Pe
 system.cpu.stage4.idleCycles               1012697898                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                1021336062                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage4.utilization               50.212341                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.tags.replacements                      1                       # number of replacements
-system.cpu.icache.tags.tagsinuse                668.751330                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                231946364                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    859                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs               270019.050058                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     668.751330                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.326539                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.326539                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 1                       # number of replacements
+system.cpu.icache.tags.tagsinuse           668.751330                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           231946364                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               859                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          270019.050058                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   668.751330                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.326539                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.326539                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    231946364                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       231946364                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     231946364                       # number of demand (read+write) hits
@@ -518,12 +519,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp       7222689                       # Tr
 system.cpu.toL2Bus.trans_dist::Writeback      3693279                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1889621                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1889621                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side         1718                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side     21916181                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                 21917899                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        54976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side    819502720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size             819557696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1718                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21916181                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          21917899                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819502720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      819557696                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus         819557696                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy    10096073500                       # Layer occupancy (ticks)
@@ -532,19 +533,19 @@ system.cpu.toL2Bus.respLayer0.occupancy       1466500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   14100129000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements               1926960                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse             30930.857959                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 8958684                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs               1956753                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  4.578342                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle           67691760750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements          1926960                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30930.857959                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            8958684                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1956753                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.578342                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      67691760750                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks 14923.938165                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst     34.347502                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  15972.572292                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    34.347502                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15972.572292                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.455442                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001048                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.487444                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.943935                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.943935                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.data      6044296                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6044296                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3693279                       # number of Writeback hits
@@ -667,15 +668,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62298.020955
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80904.545285                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80896.389405                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                9107355                       # number of replacements
-system.cpu.dcache.tags.tagsinuse               4082.476561                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                593297569                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                9111451                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  65.115597                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle            12681367250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    4082.476561                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.996698                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.996698                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9107355                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4082.476561                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           593297569                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9111451                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.115597                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       12681367250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4082.476561                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.996698                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.996698                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    437268765                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       437268765                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    156028804                       # number of WriteReq hits
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index b939ad0cc..82bf88993 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.694171                       # Nu
 sim_ticks                                694171131000                       # Number of ticks simulated
 final_tick                               694171131000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 169313                       # Simulator instruction rate (inst/s)
-host_op_rate                                   169313                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               67701038                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228220                       # Number of bytes of host memory used
-host_seconds                                 10253.48                       # Real time elapsed on the host
+host_inst_rate                                 178600                       # Simulator instruction rate (inst/s)
+host_op_rate                                   178600                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               71414604                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227828                       # Number of bytes of host memory used
+host_seconds                                  9720.30                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             61632                       # Number of bytes read from this memory
@@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks          94013475                       # To
 system.physmem.bw_total::cpu.inst               88785                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data           181209495                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              275311755                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1966438                       # Total number of read requests seen
-system.physmem.writeReqs                      1019710                       # Total number of write requests seen
-system.physmem.cpureqs                        2986156                       # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs                       1966438                       # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs                      1019710                       # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts                     1966438                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts                    1019710                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
 system.physmem.bytesRead                    125852032                       # Total number of bytes read from memory
 system.physmem.bytesWritten                  65261440                       # Total number of bytes written to memory
 system.physmem.bytesConsumedRd              125852032                       # bytesRead derated as per pkt->getSize()
 system.physmem.bytesConsumedWr               65261440                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                      561                       # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ                      561                       # Number of DRAM read bursts serviced by write Q
 system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
 system.physmem.perBankRdReqs::0                119011                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::1                114417                       # Track reads on a per bank basis
@@ -316,10 +317,10 @@ system.membus.trans_dist::ReadResp            1191259                       # Tr
 system.membus.trans_dist::Writeback           1019710                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            775179                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           775179                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side      4952586                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                       4952586                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side    191113472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                  191113472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4952586                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4952586                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191113472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           191113472                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus              191113472                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy         11881655250                       # Layer occupancy (ticks)
@@ -635,12 +636,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp       7297551                       # Tr
 system.cpu.toL2Bus.trans_dist::Writeback      3725037                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1883631                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1883631                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side         1926                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side     22085475                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                 22087401                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        61632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side    825936384                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size             825998016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1926                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22085475                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          22087401                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825936384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      825998016                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus         825998016                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy    10178230165                       # Layer occupancy (ticks)
@@ -649,15 +650,15 @@ system.cpu.toL2Bus.respLayer0.occupancy       1633750                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   14189007000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                      1                       # number of replacements
-system.cpu.icache.tags.tagsinuse                770.551884                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                391083687                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    963                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs               406109.747664                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     770.551884                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.376246                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.376246                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 1                       # number of replacements
+system.cpu.icache.tags.tagsinuse           770.551884                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           391083687                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               963                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          406109.747664                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   770.551884                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.376246                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.376246                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    391083687                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       391083687                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     391083687                       # number of demand (read+write) hits
@@ -733,19 +734,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 78020.508827
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78020.508827                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 78020.508827                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements               1933728                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse             31435.165334                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 9058547                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs               1963512                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  4.613441                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle           28123107250                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements          1933728                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31435.165334                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            9058547                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1963512                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.613441                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      28123107250                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks 14593.465528                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst     26.016964                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  16815.682842                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.016964                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 16815.682842                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.445357                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000794                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.513174                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.959325                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.959325                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.data      6106292                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6106292                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3725037                       # number of Writeback hits
@@ -868,15 +869,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64350.207684
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80652.401455                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80644.417978                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                9176123                       # number of replacements
-system.cpu.dcache.tags.tagsinuse               4087.719090                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                694209653                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                9180219                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  75.620163                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle             5145271250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    4087.719090                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.997978                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.997978                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9176123                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.719090                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           694209653                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9180219                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             75.620163                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        5145271250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.719090                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997978                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997978                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    538667558                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       538667558                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    155542093                       # number of WriteReq hits
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 72597a7eb..27c712d4a 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.623386                       # Nu
 sim_ticks                                2623386226000                       # Number of ticks simulated
 final_tick                               2623386226000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 781919                       # Simulator instruction rate (inst/s)
-host_op_rate                                   781919                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1127211275                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225028                       # Number of bytes of host memory used
-host_seconds                                  2327.32                       # Real time elapsed on the host
+host_inst_rate                                1731328                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1731328                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2495874089                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225024                       # Number of bytes of host memory used
+host_seconds                                  1051.09                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             51328                       # Number of bytes read from this memory
@@ -40,10 +40,10 @@ system.membus.trans_dist::ReadResp            1178362                       # Tr
 system.membus.trans_dist::Writeback           1018077                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            781301                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           781301                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side      4937403                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count                       4937403                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side    190575360                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size                  190575360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4937403                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4937403                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190575360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           190575360                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus              190575360                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy         11122356000                       # Layer occupancy (ticks)
@@ -105,15 +105,15 @@ system.cpu.num_idle_cycles                          0                       # Nu
 system.cpu.num_busy_cycles                 5246772452                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.icache.tags.replacements                      1                       # number of replacements
-system.cpu.icache.tags.tagsinuse                612.458646                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs               1826377708                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    802                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs               2277278.937656                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     612.458646                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.299052                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.299052                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 1                       # number of replacements
+system.cpu.icache.tags.tagsinuse           612.458646                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs          1826377708                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               802                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          2277278.937656                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   612.458646                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.299052                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.299052                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1826377708                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1826377708                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1826377708                       # number of demand (read+write) hits
@@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements               1926937                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse             30535.257456                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 8959453                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs               1956729                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  4.578791                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle          218167128000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements          1926937                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30535.257456                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            8959453                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1956729                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.578791                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     218167128000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst     39.064317                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  15274.302484                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    39.064317                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.464535                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001192                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.466135                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.931862                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.931862                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.data      6044854                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6044854                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3693497                       # number of Writeback hits
@@ -318,15 +318,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                9107638                       # number of replacements
-system.cpu.dcache.tags.tagsinuse               4079.262869                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                596212431                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                9111734                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  65.433476                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle            40977439000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    4079.262869                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.995914                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.995914                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9107638                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4079.262869                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           596212431                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9111734                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.433476                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       40977439000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4079.262869                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.995914                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.995914                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    437373249                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       437373249                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    158839182                       # number of WriteReq hits
@@ -424,12 +424,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp       7223216                       # Tr
 system.cpu.toL2Bus.trans_dist::Writeback      3693497                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1889320                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1889320                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side         1604                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side     21916965                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                 21918569                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        51328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side    819534784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size             819586112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1604                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21916965                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          21918569                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51328                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819534784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      819586112                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus         819586112                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy    10096513500                       # Layer occupancy (ticks)