diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/se/60.bzip2/ref/alpha | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt | 945 | ||||
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 1592 |
2 files changed, 1276 insertions, 1261 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 38d19f012..e7cd333d6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.200149 # Number of seconds simulated -sim_ticks 1200148658000 # Number of ticks simulated -final_tick 1200148658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.199774 # Number of seconds simulated +sim_ticks 1199774280000 # Number of ticks simulated +final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 401299 # Simulator instruction rate (inst/s) -host_op_rate 401299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 263701147 # Simulator tick rate (ticks/s) -host_mem_usage 236908 # Number of bytes of host memory used -host_seconds 4551.17 # Real time elapsed on the host +host_inst_rate 344306 # Simulator instruction rate (inst/s) +host_op_rate 344306 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 226179780 # Simulator tick rate (ticks/s) +host_mem_usage 294788 # Number of bytes of host memory used +host_seconds 5304.52 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125506304 # Number of bytes read from this memory -system.physmem.bytes_read::total 125506304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 125505984 # Number of bytes read from this memory +system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961036 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1961031 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 104575632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 104575632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54299513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54299513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54299513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 104575632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 158875145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961036 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 104607997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 104607997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961031 # Number of read requests accepted system.physmem.writeReqs 1018242 # Number of write requests accepted -system.physmem.readBursts 1961036 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 1961031 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1018242 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125423936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82368 # Total number of bytes read from write queue -system.physmem.bytesWritten 65165888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125506304 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 125423808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 82176 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166208 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125505984 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 65167488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1287 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 1284 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118759 # Per bank write bursts -system.physmem.perBankRdBursts::1 114099 # Per bank write bursts -system.physmem.perBankRdBursts::2 116224 # Per bank write bursts -system.physmem.perBankRdBursts::3 117761 # Per bank write bursts -system.physmem.perBankRdBursts::4 117826 # Per bank write bursts -system.physmem.perBankRdBursts::5 117519 # Per bank write bursts -system.physmem.perBankRdBursts::6 119878 # Per bank write bursts -system.physmem.perBankRdBursts::7 124524 # Per bank write bursts -system.physmem.perBankRdBursts::8 126972 # Per bank write bursts -system.physmem.perBankRdBursts::9 130092 # Per bank write bursts -system.physmem.perBankRdBursts::10 128660 # Per bank write bursts -system.physmem.perBankRdBursts::11 130342 # Per bank write bursts +system.physmem.perBankRdBursts::0 118757 # Per bank write bursts +system.physmem.perBankRdBursts::1 114096 # Per bank write bursts +system.physmem.perBankRdBursts::2 116226 # Per bank write bursts +system.physmem.perBankRdBursts::3 117770 # Per bank write bursts +system.physmem.perBankRdBursts::4 117824 # Per bank write bursts +system.physmem.perBankRdBursts::5 117523 # Per bank write bursts +system.physmem.perBankRdBursts::6 119882 # Per bank write bursts +system.physmem.perBankRdBursts::7 124516 # Per bank write bursts +system.physmem.perBankRdBursts::8 126973 # Per bank write bursts +system.physmem.perBankRdBursts::9 130090 # Per bank write bursts +system.physmem.perBankRdBursts::10 128654 # Per bank write bursts +system.physmem.perBankRdBursts::11 130347 # Per bank write bursts system.physmem.perBankRdBursts::12 126055 # Per bank write bursts -system.physmem.perBankRdBursts::13 125250 # Per bank write bursts -system.physmem.perBankRdBursts::14 122599 # Per bank write bursts -system.physmem.perBankRdBursts::15 123189 # Per bank write bursts +system.physmem.perBankRdBursts::13 125249 # Per bank write bursts +system.physmem.perBankRdBursts::14 122591 # Per bank write bursts +system.physmem.perBankRdBursts::15 123194 # Per bank write bursts system.physmem.perBankWrBursts::0 61222 # Per bank write bursts -system.physmem.perBankWrBursts::1 61486 # Per bank write bursts -system.physmem.perBankWrBursts::2 60565 # Per bank write bursts +system.physmem.perBankWrBursts::1 61485 # Per bank write bursts +system.physmem.perBankWrBursts::2 60564 # Per bank write bursts system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61662 # Per bank write bursts -system.physmem.perBankWrBursts::5 63103 # Per bank write bursts +system.physmem.perBankWrBursts::4 61658 # Per bank write bursts +system.physmem.perBankWrBursts::5 63101 # Per bank write bursts system.physmem.perBankWrBursts::6 64148 # Per bank write bursts -system.physmem.perBankWrBursts::7 65614 # Per bank write bursts -system.physmem.perBankWrBursts::8 65330 # Per bank write bursts -system.physmem.perBankWrBursts::9 65779 # Per bank write bursts -system.physmem.perBankWrBursts::10 65300 # Per bank write bursts -system.physmem.perBankWrBursts::11 65644 # Per bank write bursts -system.physmem.perBankWrBursts::12 64162 # Per bank write bursts -system.physmem.perBankWrBursts::13 64212 # Per bank write bursts -system.physmem.perBankWrBursts::14 64570 # Per bank write bursts -system.physmem.perBankWrBursts::15 64181 # Per bank write bursts +system.physmem.perBankWrBursts::7 65617 # Per bank write bursts +system.physmem.perBankWrBursts::8 65332 # Per bank write bursts +system.physmem.perBankWrBursts::9 65778 # Per bank write bursts +system.physmem.perBankWrBursts::10 65295 # Per bank write bursts +system.physmem.perBankWrBursts::11 65646 # Per bank write bursts +system.physmem.perBankWrBursts::12 64171 # Per bank write bursts +system.physmem.perBankWrBursts::13 64211 # Per bank write bursts +system.physmem.perBankWrBursts::14 64568 # Per bank write bursts +system.physmem.perBankWrBursts::15 64187 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1200148547500 # Total gap between requests +system.physmem.totGap 1199774169500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961036 # Read request sizes (log2) +system.physmem.readPktSize::6 1961031 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1018242 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1834284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125445 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,35 +140,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -189,128 +189,129 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1837714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.708116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.073776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.879385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1458610 79.37% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 262385 14.28% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49383 2.69% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20628 1.12% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12966 0.71% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7221 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5354 0.29% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4357 0.24% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16810 0.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1837714 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59460 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.957232 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.327917 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59419 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1838370 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.671596 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.054008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.842659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1459678 79.40% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 262161 14.26% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49287 2.68% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20645 1.12% 97.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12893 0.70% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7143 0.39% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5357 0.29% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4451 0.24% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16755 0.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1838370 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59429 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.975652 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.968947 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59388 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59460 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59460 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.124403 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.088362 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.116973 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27861 46.86% 46.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1344 2.26% 49.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 25901 43.56% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3838 6.45% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 438 0.74% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 56 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59460 # Writes before turning the bus around for reads -system.physmem.totQLat 37078229500 # Total ticks spent queuing -system.physmem.totMemAccLat 73823523250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18919.89 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59429 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59429 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.133420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.097680 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.110939 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27565 46.38% 46.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1269 2.14% 48.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26249 44.17% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3908 6.58% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 362 0.61% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 56 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59429 # Writes before turning the bus around for reads +system.physmem.totQLat 36751953000 # Total ticks spent queuing +system.physmem.totMemAccLat 73497209250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798735000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18753.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37669.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 104.51 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 54.30 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 104.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 54.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37503.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 104.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 54.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 104.61 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 54.32 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.24 # Data bus utilization in percentage system.physmem.busUtilRead 0.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 726316 # Number of row buffer hits during reads -system.physmem.writeRowHits 413927 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.65 # Row buffer hit rate for writes -system.physmem.avgGap 402832.01 # Average gap between requests -system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 393584177750 # Time in different power states -system.physmem.memoryStateTime::REF 40075360000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 766482185250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6742219680 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 7150867920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3678790500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3901763250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7383355200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7901907000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3233772720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3364273440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 78387404160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 78387404160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 410122352430 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 423496116225 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 360328576500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 348597204750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 869876471190 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 872799536745 # Total energy per rank (pJ) -system.physmem.averagePower::0 724.811465 # Core power per rank (mW) -system.physmem.averagePower::1 727.247065 # Core power per rank (mW) -system.cpu.branchPred.lookups 246247636 # Number of BP lookups -system.cpu.branchPred.condPredicted 186450048 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15699340 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 168260719 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165258168 # Number of BTB hits +system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing +system.physmem.readRowHits 726418 # Number of row buffer hits during reads +system.physmem.writeRowHits 413172 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.58 # Row buffer hit rate for writes +system.physmem.avgGap 402707.03 # Average gap between requests +system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6745500720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3680580750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7383386400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3233733840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 409753789290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 360427621500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 869587605780 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.796496 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 596865139750 # Time in different power states +system.physmem_0.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 562842538250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 7152516000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3902662500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7901961600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3364241040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 422708761260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 349063611000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 872456746680 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.187909 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 577877428500 # Time in different power states +system.physmem_1.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 581827655250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 246222594 # Number of BP lookups +system.cpu.branchPred.condPredicted 186441188 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15682162 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167748253 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165224895 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.215537 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18428845 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104881 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.495747 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18427327 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104678 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452532318 # DTB read hits -system.cpu.dtb.read_misses 4979776 # DTB read misses +system.cpu.dtb.read_hits 452533853 # DTB read hits +system.cpu.dtb.read_misses 4979561 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457512094 # DTB read accesses -system.cpu.dtb.write_hits 161379130 # DTB write hits -system.cpu.dtb.write_misses 1710165 # DTB write misses +system.cpu.dtb.read_accesses 457513414 # DTB read accesses +system.cpu.dtb.write_hits 161377742 # DTB write hits +system.cpu.dtb.write_misses 1710117 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163089295 # DTB write accesses -system.cpu.dtb.data_hits 613911448 # DTB hits -system.cpu.dtb.data_misses 6689941 # DTB misses +system.cpu.dtb.write_accesses 163087859 # DTB write accesses +system.cpu.dtb.data_hits 613911595 # DTB hits +system.cpu.dtb.data_misses 6689678 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620601389 # DTB accesses -system.cpu.itb.fetch_hits 598579568 # ITB hits +system.cpu.dtb.data_accesses 620601273 # DTB accesses +system.cpu.itb.fetch_hits 598493672 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598579587 # ITB accesses +system.cpu.itb.fetch_accesses 598493691 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,66 +325,66 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2400297316 # number of cpu cycles simulated +system.cpu.numCycles 2399548560 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52410829 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52395177 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.314239 # CPI: cycles per instruction -system.cpu.ipc 0.760897 # IPC: instructions per cycle -system.cpu.tickCycles 2077436531 # Number of cycles that the object actually ticked -system.cpu.idleCycles 322860785 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121980 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.680046 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601827690 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126076 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.945943 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16791074000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.680046 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.996260 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996260 # Average percentage of cache occupancy +system.cpu.cpi 1.313829 # CPI: cycles per instruction +system.cpu.ipc 0.761134 # IPC: instructions per cycle +system.cpu.tickCycles 2077217503 # Number of cycles that the object actually ticked +system.cpu.idleCycles 322331057 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121997 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.675710 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601828569 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.675710 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.996259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1617 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1613 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2310 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231838176 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231838176 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 443337984 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443337984 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 158489706 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158489706 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 601827690 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601827690 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 601827690 # number of overall hits -system.cpu.dcache.overall_hits::total 601827690 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7289564 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289564 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2238796 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238796 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9528360 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9528360 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9528360 # number of overall misses -system.cpu.dcache.overall_misses::total 9528360 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178244544500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 178244544500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101115441000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101115441000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 279359985500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 279359985500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 279359985500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 279359985500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 450627548 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450627548 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 443338834 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443338834 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 158489735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158489735 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 601828569 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601828569 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 601828569 # number of overall hits +system.cpu.dcache.overall_hits::total 601828569 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7289569 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289569 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2238767 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238767 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9528336 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9528336 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9528336 # number of overall misses +system.cpu.dcache.overall_misses::total 9528336 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178039686000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 178039686000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100958450500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 100958450500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 278998136500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 278998136500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 278998136500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 278998136500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 450628403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450628403 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 611356050 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611356050 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 611356050 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611356050 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 611356905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611356905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 611356905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611356905 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013929 # miss rate for WriteReq accesses @@ -392,14 +393,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.015586 system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.015586 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24452.017226 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24452.017226 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45165.098115 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45165.098115 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29318.789960 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29318.789960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29318.789960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29318.789960 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24423.897490 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24423.897490 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45095.559520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45095.559520 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29280.887712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,32 +409,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700593 # number of writebacks -system.cpu.dcache.writebacks::total 3700593 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50804 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50804 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 351480 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 351480 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 402284 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 402284 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 402284 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 402284 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238760 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238760 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887316 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887316 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126076 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126076 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126076 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126076 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162288114750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162288114750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76072677250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76072677250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238360792000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 238360792000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238360792000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 238360792000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700624 # number of writebacks +system.cpu.dcache.writebacks::total 3700624 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50811 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 351432 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 351432 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 402243 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 402243 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 402243 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 402243 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238758 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238758 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887335 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126093 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126093 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126093 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162083992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162083992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75948494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75948494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238032486500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 238032486500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238032486500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 238032486500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses @@ -442,66 +443,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014928 system.cpu.dcache.demand_mshr_miss_rate::total 0.014928 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014928 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014928 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22419.325237 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22419.325237 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40307.334463 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40307.334463 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26118.650776 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26118.650776 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26118.650776 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26118.650776 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22391.132844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22391.132844 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40241.130748 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40241.130748 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26082.627747 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26082.627747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 751.335570 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 598578610 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 624821.096033 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 752.081160 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 598492713 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 959 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 624079.992701 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 751.335570 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366863 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366863 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1197160094 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1197160094 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 598578610 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 598578610 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 598578610 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 598578610 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 598578610 # number of overall hits -system.cpu.icache.overall_hits::total 598578610 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses -system.cpu.icache.overall_misses::total 958 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 69954750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 69954750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 69954750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 69954750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69954750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69954750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 598579568 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 598579568 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 598579568 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 598579568 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 598579568 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 598579568 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 752.081160 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.367227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.367227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 956 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.466797 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1196988303 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1196988303 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 598492713 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 598492713 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 598492713 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 598492713 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 598492713 # number of overall hits +system.cpu.icache.overall_hits::total 598492713 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 959 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 959 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 959 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 959 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 959 # number of overall misses +system.cpu.icache.overall_misses::total 959 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 71027250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 71027250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 71027250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 71027250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 71027250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 71027250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 598493672 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 598493672 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 598493672 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 598493672 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 598493672 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 598493672 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73021.659708 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73021.659708 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73021.659708 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73021.659708 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73021.659708 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73021.659708 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74063.868613 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74063.868613 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74063.868613 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74063.868613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74063.868613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74063.868613 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,103 +511,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67649250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 67649250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67649250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 67649250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67649250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 67649250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 959 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 959 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 959 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68715750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 68715750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68715750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 68715750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68715750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 68715750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70615.083507 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70615.083507 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70615.083507 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70615.083507 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70615.083507 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70615.083507 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71653.545360 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71653.545360 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71653.545360 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71653.545360 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71653.545360 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71653.545360 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1928301 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30757.102119 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8981678 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1958105 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.586924 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 89010017750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14951.432619 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15805.669500 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.456282 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482351 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.938632 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1928296 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30756.810610 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8981713 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1958100 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.586953 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 89009074750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14951.890642 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15804.919969 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.456295 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482328 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938623 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29804 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1226 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12860 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15530 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15531 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106466437 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106466437 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6058126 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6058126 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3700593 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700593 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107872 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107872 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7165998 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7165998 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7165998 # number of overall hits -system.cpu.l2cache.overall_hits::total 7165998 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1181592 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1181592 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 779444 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 779444 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1961036 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1961036 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1961036 # number of overall misses -system.cpu.l2cache.overall_misses::total 1961036 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 94518452000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94518452000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 63058108000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 63058108000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 157576560000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 157576560000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 157576560000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 157576560000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7239718 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7239718 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3700593 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700593 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1887316 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1887316 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9127034 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9127034 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9127034 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9127034 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412991 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.412991 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214860 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214860 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214860 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214860 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79992.461019 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79992.461019 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80901.396380 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80901.396380 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80353.731395 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80353.731395 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80353.731395 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80353.731395 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 106466843 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106466843 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 6058136 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6058136 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700624 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700624 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107885 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107885 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7166021 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7166021 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7166021 # number of overall hits +system.cpu.l2cache.overall_hits::total 7166021 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1181581 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1181581 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 779450 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 779450 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1961031 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1961031 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1961031 # number of overall misses +system.cpu.l2cache.overall_misses::total 1961031 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 94315348250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94315348250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 62933867000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 62933867000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 157249215250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 157249215250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 157249215250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 157249215250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7239717 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7239717 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3700624 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3700624 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1887335 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1887335 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9127052 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9127052 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9127052 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9127052 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163208 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163208 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412990 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.412990 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214859 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214859 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214859 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214859 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79821.314197 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79821.314197 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80741.377895 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80741.377895 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80187.011450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80187.011450 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -617,91 +618,91 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1018242 # number of writebacks system.cpu.l2cache.writebacks::total 1018242 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1181592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779444 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 779444 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961036 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1961036 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961036 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1961036 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79676806000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79676806000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53247448000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53247448000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132924254000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 132924254000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132924254000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 132924254000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412991 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412991 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67431.741244 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67431.741244 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68314.655062 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68314.655062 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67782.668957 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779450 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 779450 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961031 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961031 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79473588750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79473588750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53122771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53122771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132596359750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 132596359750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67260.381430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67260.381430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68154.174097 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68154.174097 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7239718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700593 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887316 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887316 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954661 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820906816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820968128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7239717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887335 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887335 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1918 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952810 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954728 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820909888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820971264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12827627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12827676 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12827627 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827676 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12827627 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10114406500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12827676 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114462000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1631750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1635250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14010883500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14011262000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1181592 # Transaction distribution -system.membus.trans_dist::ReadResp 1181592 # Transaction distribution +system.membus.trans_dist::ReadReq 1181581 # Transaction distribution +system.membus.trans_dist::ReadResp 1181581 # Transaction distribution system.membus.trans_dist::Writeback 1018242 # Transaction distribution -system.membus.trans_dist::ReadExReq 779444 # Transaction distribution -system.membus.trans_dist::ReadExResp 779444 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940314 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940314 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190673792 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 779450 # Transaction distribution +system.membus.trans_dist::ReadExResp 779450 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940304 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190673472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979278 # Request fanout histogram +system.membus.snoop_fanout::samples 2979273 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979278 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979273 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979278 # Request fanout histogram -system.membus.reqLayer0.occupancy 11833253000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2979273 # Request fanout histogram +system.membus.reqLayer0.occupancy 11833185000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18446066000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18446289250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 704344325..9b6ff7bd3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.662267 # Number of seconds simulated -sim_ticks 662266942000 # Number of ticks simulated -final_tick 662266942000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.662030 # Number of seconds simulated +sim_ticks 662030381000 # Number of ticks simulated +final_tick 662030381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189043 # Simulator instruction rate (inst/s) -host_op_rate 189043 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72116099 # Simulator tick rate (ticks/s) -host_mem_usage 239436 # Number of bytes of host memory used -host_seconds 9183.34 # Real time elapsed on the host +host_inst_rate 173779 # Simulator instruction rate (inst/s) +host_op_rate 173779 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66269486 # Simulator tick rate (ticks/s) +host_mem_usage 296312 # Number of bytes of host memory used +host_seconds 9989.97 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 62272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125973696 # Number of bytes read from this memory -system.physmem.bytes_read::total 126035968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65304064 # Number of bytes written to this memory -system.physmem.bytes_written::total 65304064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1968339 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1969312 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1020376 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1020376 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 190215890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 190309919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94029 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94029 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98606861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98606861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98606861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 190215890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 288916779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1969312 # Number of read requests accepted -system.physmem.writeReqs 1020376 # Number of write requests accepted -system.physmem.readBursts 1969312 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1020376 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125955072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 80896 # Total number of bytes read from write queue -system.physmem.bytesWritten 65302080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126035968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65304064 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1264 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125964224 # Number of bytes read from this memory +system.physmem.bytes_read::total 126026048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65301568 # Number of bytes written to this memory +system.physmem.bytes_written::total 65301568 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968191 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020337 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020337 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 190269552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 190362937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98638325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98638325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98638325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 190269552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 289001263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969157 # Number of read requests accepted +system.physmem.writeReqs 1020337 # Number of write requests accepted +system.physmem.readBursts 1969157 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020337 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125945216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 80832 # Total number of bytes read from write queue +system.physmem.bytesWritten 65299584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126026048 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65301568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1263 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119151 # Per bank write bursts -system.physmem.perBankRdBursts::1 114520 # Per bank write bursts -system.physmem.perBankRdBursts::2 116626 # Per bank write bursts -system.physmem.perBankRdBursts::3 118169 # Per bank write bursts -system.physmem.perBankRdBursts::4 118249 # Per bank write bursts -system.physmem.perBankRdBursts::5 117904 # Per bank write bursts -system.physmem.perBankRdBursts::6 120341 # Per bank write bursts -system.physmem.perBankRdBursts::7 125053 # Per bank write bursts -system.physmem.perBankRdBursts::8 127649 # Per bank write bursts -system.physmem.perBankRdBursts::9 130602 # Per bank write bursts -system.physmem.perBankRdBursts::10 129289 # Per bank write bursts -system.physmem.perBankRdBursts::11 130962 # Per bank write bursts -system.physmem.perBankRdBursts::12 126769 # Per bank write bursts -system.physmem.perBankRdBursts::13 125905 # Per bank write bursts -system.physmem.perBankRdBursts::14 123070 # Per bank write bursts -system.physmem.perBankRdBursts::15 123789 # Per bank write bursts -system.physmem.perBankWrBursts::0 61320 # Per bank write bursts +system.physmem.perBankRdBursts::0 119107 # Per bank write bursts +system.physmem.perBankRdBursts::1 114513 # Per bank write bursts +system.physmem.perBankRdBursts::2 116588 # Per bank write bursts +system.physmem.perBankRdBursts::3 118130 # Per bank write bursts +system.physmem.perBankRdBursts::4 118281 # Per bank write bursts +system.physmem.perBankRdBursts::5 117894 # Per bank write bursts +system.physmem.perBankRdBursts::6 120372 # Per bank write bursts +system.physmem.perBankRdBursts::7 125027 # Per bank write bursts +system.physmem.perBankRdBursts::8 127642 # Per bank write bursts +system.physmem.perBankRdBursts::9 130604 # Per bank write bursts +system.physmem.perBankRdBursts::10 129295 # Per bank write bursts +system.physmem.perBankRdBursts::11 130929 # Per bank write bursts +system.physmem.perBankRdBursts::12 126770 # Per bank write bursts +system.physmem.perBankRdBursts::13 125862 # Per bank write bursts +system.physmem.perBankRdBursts::14 123081 # Per bank write bursts +system.physmem.perBankRdBursts::15 123799 # Per bank write bursts +system.physmem.perBankWrBursts::0 61289 # Per bank write bursts system.physmem.perBankWrBursts::1 61597 # Per bank write bursts -system.physmem.perBankWrBursts::2 60678 # Per bank write bursts -system.physmem.perBankWrBursts::3 61357 # Per bank write bursts -system.physmem.perBankWrBursts::4 61793 # Per bank write bursts -system.physmem.perBankWrBursts::5 63216 # Per bank write bursts -system.physmem.perBankWrBursts::6 64269 # Per bank write bursts -system.physmem.perBankWrBursts::7 65744 # Per bank write bursts -system.physmem.perBankWrBursts::8 65524 # Per bank write bursts -system.physmem.perBankWrBursts::9 65904 # Per bank write bursts -system.physmem.perBankWrBursts::10 65459 # Per bank write bursts -system.physmem.perBankWrBursts::11 65777 # Per bank write bursts -system.physmem.perBankWrBursts::12 64349 # Per bank write bursts -system.physmem.perBankWrBursts::13 64362 # Per bank write bursts -system.physmem.perBankWrBursts::14 64665 # Per bank write bursts -system.physmem.perBankWrBursts::15 64331 # Per bank write bursts +system.physmem.perBankWrBursts::2 60658 # Per bank write bursts +system.physmem.perBankWrBursts::3 61339 # Per bank write bursts +system.physmem.perBankWrBursts::4 61821 # Per bank write bursts +system.physmem.perBankWrBursts::5 63209 # Per bank write bursts +system.physmem.perBankWrBursts::6 64289 # Per bank write bursts +system.physmem.perBankWrBursts::7 65739 # Per bank write bursts +system.physmem.perBankWrBursts::8 65503 # Per bank write bursts +system.physmem.perBankWrBursts::9 65920 # Per bank write bursts +system.physmem.perBankWrBursts::10 65439 # Per bank write bursts +system.physmem.perBankWrBursts::11 65771 # Per bank write bursts +system.physmem.perBankWrBursts::12 64363 # Per bank write bursts +system.physmem.perBankWrBursts::13 64352 # Per bank write bursts +system.physmem.perBankWrBursts::14 64685 # Per bank write bursts +system.physmem.perBankWrBursts::15 64332 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 662266852500 # Total gap between requests +system.physmem.totGap 662030291500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1969312 # Read request sizes (log2) +system.physmem.readPktSize::6 1969157 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1020376 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1619195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 248434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 76068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020337 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1619145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 248303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 76115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,38 +144,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 63086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -193,151 +193,142 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1775882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.694867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.878503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 136.793796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1380775 77.75% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271356 15.28% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53913 3.04% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21326 1.20% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12854 0.72% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6480 0.36% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5132 0.29% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3787 0.21% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20259 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1775882 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59943 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.788466 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.189780 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59903 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 15 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 9 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1776224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.667141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.863857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 136.742577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1381396 77.77% 77.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271071 15.26% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53950 3.04% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21226 1.20% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12955 0.73% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6597 0.37% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5003 0.28% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3759 0.21% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20267 1.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1776224 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59925 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.795728 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 163.660245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59887 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59943 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59943 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.021921 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.980571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.225631 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 33661 56.16% 56.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 25267 42.15% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 929 1.55% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 52 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59943 # Writes before turning the bus around for reads -system.physmem.totQLat 41251747750 # Total ticks spent queuing -system.physmem.totMemAccLat 78152647750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9840240000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20960.74 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59925 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.026383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.985304 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.212732 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31950 53.32% 53.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1595 2.66% 55.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20819 34.74% 90.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4577 7.64% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 750 1.25% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 154 0.26% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 27 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 19 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59925 # Writes before turning the bus around for reads +system.physmem.totQLat 40790268000 # Total ticks spent queuing +system.physmem.totMemAccLat 77688280500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9839470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20727.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39710.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 190.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 98.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 190.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 98.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39477.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 190.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 98.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 190.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 98.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.26 # Data bus utilization in percentage system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 795732 # Number of row buffer hits during reads -system.physmem.writeRowHits 416769 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.84 # Row buffer hit rate for writes -system.physmem.avgGap 221517.05 # Average gap between requests -system.physmem.pageHitRate 40.57 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 126335534000 # Time in different power states -system.physmem.memoryStateTime::REF 22114300000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 513810229000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6510407400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 6915200040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3552305625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3773174625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7409890800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7939939800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3239831520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3372004080 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 43255570800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 43255570800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 299907401805 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 307252084365 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 134279187750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 127836483750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 498154595700 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 500344457460 # Total energy per rank (pJ) -system.physmem.averagePower::0 752.204234 # Core power per rank (mW) -system.physmem.averagePower::1 755.510885 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1197969 # Transaction distribution -system.membus.trans_dist::ReadResp 1197969 # Transaction distribution -system.membus.trans_dist::Writeback 1020376 # Transaction distribution -system.membus.trans_dist::ReadExReq 771343 # Transaction distribution -system.membus.trans_dist::ReadExResp 771343 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959000 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4959000 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191340032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191340032 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2989688 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2989688 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2989688 # Request fanout histogram -system.membus.reqLayer0.occupancy 11823557000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 18423875500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 410506798 # Number of BP lookups -system.cpu.branchPred.condPredicted 318826270 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16270103 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 283363020 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279346814 # Number of BTB hits +system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing +system.physmem.readRowHits 795786 # Number of row buffer hits during reads +system.physmem.writeRowHits 416180 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.79 # Row buffer hit rate for writes +system.physmem.avgGap 221452.29 # Average gap between requests +system.physmem.pageHitRate 40.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6511261680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3552771750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7409259000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3239617680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 299928124440 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134120853750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 498002202300 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.239455 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 221171423750 # Time in different power states +system.physmem_0.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 418748256250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6916946400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3774127500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7939518600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3371965200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 306633623535 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 128238837000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 500115332235 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.431368 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 211341940750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 428577885750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 410531758 # Number of BP lookups +system.cpu.branchPred.condPredicted 318847451 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16269165 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 283137932 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279377578 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.582664 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26372853 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.671900 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26373623 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646169518 # DTB read hits -system.cpu.dtb.read_misses 12159492 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 658329010 # DTB read accesses -system.cpu.dtb.write_hits 218199205 # DTB write hits -system.cpu.dtb.write_misses 7515385 # DTB write misses +system.cpu.dtb.read_hits 646133385 # DTB read hits +system.cpu.dtb.read_misses 12154937 # DTB read misses +system.cpu.dtb.read_acv 1 # DTB read access violations +system.cpu.dtb.read_accesses 658288322 # DTB read accesses +system.cpu.dtb.write_hits 218173916 # DTB write hits +system.cpu.dtb.write_misses 7514058 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225714590 # DTB write accesses -system.cpu.dtb.data_hits 864368723 # DTB hits -system.cpu.dtb.data_misses 19674877 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 884043600 # DTB accesses -system.cpu.itb.fetch_hits 422435766 # ITB hits -system.cpu.itb.fetch_misses 46 # ITB misses +system.cpu.dtb.write_accesses 225687974 # DTB write accesses +system.cpu.dtb.data_hits 864307301 # DTB hits +system.cpu.dtb.data_misses 19668995 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 883976296 # DTB accesses +system.cpu.itb.fetch_hits 422458110 # ITB hits +system.cpu.itb.fetch_misses 45 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422435812 # ITB accesses +system.cpu.itb.fetch_accesses 422458155 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,98 +342,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1324533885 # number of cpu cycles simulated +system.cpu.numCycles 1324060763 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433728129 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3419447982 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410506798 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305719667 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 867740174 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45999556 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 89 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1859 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 122 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422435766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8419815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1324470151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.581748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.157662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433748906 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3419441963 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410531758 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305751201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 867248304 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45995858 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1804 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422458110 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8422260 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1323997070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582666 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.157790 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 697483370 52.66% 52.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48005474 3.62% 56.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24395138 1.84% 58.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45249876 3.42% 61.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142980828 10.80% 72.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66219617 5.00% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43796288 3.31% 80.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29613001 2.24% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226726559 17.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 696991073 52.64% 52.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48002120 3.63% 56.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24407254 1.84% 58.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45263157 3.42% 61.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142993214 10.80% 72.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66222276 5.00% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43788088 3.31% 80.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29616004 2.24% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226713884 17.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1324470151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309925 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.581624 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355594570 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 385179518 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525809516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34887563 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22998984 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62292881 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3264034617 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2122 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22998984 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373946851 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 205483814 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7143 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538725666 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183307693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3181027912 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1764061 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19006533 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 140449897 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27939508 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2377346604 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4126580900 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4126409923 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 170976 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1323997070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310055 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.582542 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355597650 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 384696746 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525812607 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34892959 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22997108 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62293389 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 869 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3264034948 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2192 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22997108 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373957968 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 205165673 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7731 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538730067 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 183138523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181033284 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1755579 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18983042 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 140285341 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27927823 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377354751 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4126620289 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4126448707 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 171581 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001143641 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 182 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99171579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719206222 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272877842 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90853191 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58764648 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2889718435 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624030011 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1568714 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1139278450 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 505521247 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 134 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1324470151 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981192 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.151140 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001151788 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 192 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 191 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99207749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719206023 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272877739 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90880933 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 59162115 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2889782486 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 178 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624016708 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1570062 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1139342915 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 505618557 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 149 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1323997070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981890 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.151111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 520285766 39.28% 39.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169352294 12.79% 52.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158263377 11.95% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149147598 11.26% 75.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126214674 9.53% 84.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84460771 6.38% 91.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68224303 5.15% 96.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33971144 2.56% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14550224 1.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 519747645 39.26% 39.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169377682 12.79% 52.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158338012 11.96% 64.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149173722 11.27% 75.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126185648 9.53% 84.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84437665 6.38% 91.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68199937 5.15% 96.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33982775 2.57% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14553984 1.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1324470151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1323997070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13169928 35.70% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13171575 35.70% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available @@ -471,118 +462,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19111172 51.81% 87.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4608428 12.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19111155 51.80% 87.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4612971 12.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719281995 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719329788 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 125 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896550 0.03% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 672977290 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230873835 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 895316 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 672939161 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230852080 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624030011 # Type of FU issued -system.cpu.iq.rate 1.981097 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36889528 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014058 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6609007948 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4027844088 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2521909296 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1980467 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1299263 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 893137 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2659936163 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 983376 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69546745 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624016708 # Type of FU issued +system.cpu.iq.rate 1.981795 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36895701 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014061 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6608517036 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4027973051 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2521923586 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1979213 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1297888 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 892539 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2659929620 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 982789 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69543206 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274610559 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379781 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 148802 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112149340 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274610360 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379362 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 147727 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112149237 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6024507 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6023017 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22998984 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 147954834 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18526434 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3040938881 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6690511 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719206222 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272877842 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 163 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 822212 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17973283 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 148802 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10902941 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8845995 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19748936 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2578346915 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658329015 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45683096 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22997108 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 147758887 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18474565 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3040988458 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6691344 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719206023 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272877739 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 178 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 822290 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17921565 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 147727 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10901488 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8843129 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19744617 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578330269 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658288327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45686439 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151220283 # number of nop insts executed -system.cpu.iew.exec_refs 884043668 # number of memory reference insts executed -system.cpu.iew.exec_branches 315967801 # Number of branches executed -system.cpu.iew.exec_stores 225714653 # Number of stores executed -system.cpu.iew.exec_rate 1.946607 # Inst execution rate -system.cpu.iew.wb_sent 2552803336 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2522802433 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489230488 # num instructions producing a value -system.cpu.iew.wb_consumers 1920481156 # num instructions consuming a value +system.cpu.iew.exec_nop 151205794 # number of nop insts executed +system.cpu.iew.exec_refs 883976375 # number of memory reference insts executed +system.cpu.iew.exec_branches 315983093 # Number of branches executed +system.cpu.iew.exec_stores 225688048 # Number of stores executed +system.cpu.iew.exec_rate 1.947290 # Inst execution rate +system.cpu.iew.wb_sent 2552817971 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2522816125 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489246506 # num instructions producing a value +system.cpu.iew.wb_consumers 1920479792 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.904672 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775447 # average fanout of values written-back +system.cpu.iew.wb_rate 1.905363 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775455 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005079964 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005136223 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16269309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1185591559 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.534913 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.558094 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16268344 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1185116972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.535528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.558449 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 696399330 58.74% 58.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159901902 13.49% 72.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79790439 6.73% 78.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52118707 4.40% 83.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28427889 2.40% 85.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19400301 1.64% 87.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20045609 1.69% 89.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23104546 1.95% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106402836 8.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 695949152 58.72% 58.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159874809 13.49% 72.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79784402 6.73% 78.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52116706 4.40% 83.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28440614 2.40% 85.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19407125 1.64% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20027045 1.69% 89.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23110908 1.95% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106406211 8.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1185591559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1185116972 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -628,233 +619,339 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106402836 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106406211 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3818269613 # The number of ROB reads -system.cpu.rob.rob_writes 5788733936 # The number of ROB writes -system.cpu.timesIdled 729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 63734 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3817847910 # The number of ROB reads +system.cpu.rob.rob_writes 5788846951 # The number of ROB writes +system.cpu.timesIdled 724 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 63693 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.762961 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.762961 # CPI: Total CPI of All Threads -system.cpu.ipc 1.310683 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.310683 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3467602221 # number of integer regfile reads -system.cpu.int_regfile_writes 2022271322 # number of integer regfile writes -system.cpu.fp_regfile_reads 45596 # number of floating regfile reads -system.cpu.fp_regfile_writes 565 # number of floating regfile writes +system.cpu.cpi 0.762689 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.762689 # CPI: Total CPI of All Threads +system.cpu.ipc 1.311151 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.311151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3467581476 # number of integer regfile reads +system.cpu.int_regfile_writes 2022302956 # number of integer regfile writes +system.cpu.fp_regfile_reads 46080 # number of floating regfile reads +system.cpu.fp_regfile_writes 592 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 7335000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7335000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3742826 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879134 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879134 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1946 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22169148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22171094 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829183168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 829245440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12957100 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12957100 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12957100 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10221444363 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1621500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14117208750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 9209012 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.412521 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713854428 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9213108 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.482477 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.412521 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 751 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2935 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1472845170 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472845170 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558341279 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558341279 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155513145 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155513145 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 713854424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713854424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713854424 # number of overall hits +system.cpu.dcache.overall_hits::total 713854424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12746245 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12746245 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5215357 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5215357 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 17961602 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17961602 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17961602 # number of overall misses +system.cpu.dcache.overall_misses::total 17961602 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 384451562750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 384451562750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289305166008 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289305166008 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 673756728758 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 673756728758 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 673756728758 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 673756728758 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 731816026 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731816026 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731816026 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731816026 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024544 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024544 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024544 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024544 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30161.946734 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30161.946734 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55471.785730 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55471.785730 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37510.948564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37510.948564 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14120110 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8634302 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1055091 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67341 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.382836 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 128.217609 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3742780 # number of writebacks +system.cpu.dcache.writebacks::total 3742780 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412238 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5412238 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3336257 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3336257 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8748495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8748495 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8748495 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8748495 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334007 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334007 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9213107 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9213107 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9213107 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9213107 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168659488250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168659488250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77208966781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77208966781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245868455031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245868455031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245868455031 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245868455031 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22996.908545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22996.908545 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41088.269268 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41088.269268 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 772.533395 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 422434249 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 973 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 434156.473792 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 770.158211 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 422456585 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 437325.657350 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 772.533395 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 972 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 844872503 # Number of tag accesses -system.cpu.icache.tags.data_accesses 844872503 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422434249 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422434249 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422434249 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422434249 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422434249 # number of overall hits -system.cpu.icache.overall_hits::total 422434249 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1516 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1516 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1516 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1516 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1516 # number of overall misses -system.cpu.icache.overall_misses::total 1516 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 104441749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 104441749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 104441749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 104441749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 104441749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 104441749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 422435765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422435765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422435765 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422435765 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422435765 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422435765 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 770.158211 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376054 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376054 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 899 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 844917184 # Number of tag accesses +system.cpu.icache.tags.data_accesses 844917184 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 422456585 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 422456585 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 422456585 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 422456585 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 422456585 # number of overall hits +system.cpu.icache.overall_hits::total 422456585 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1524 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1524 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1524 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1524 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1524 # number of overall misses +system.cpu.icache.overall_misses::total 1524 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 107000999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 107000999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 107000999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 107000999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 107000999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 107000999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 422458109 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 422458109 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 422458109 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 422458109 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 422458109 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 422458109 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68892.974274 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68892.974274 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68892.974274 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68892.974274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68892.974274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68892.974274 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70210.629265 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70210.629265 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70210.629265 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70210.629265 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 469 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58.625000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 543 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 543 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 543 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 543 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 543 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 543 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 973 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 973 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 973 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 973 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 973 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72760499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 72760499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72760499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 72760499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72760499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 72760499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 558 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 558 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 558 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 558 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 558 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 558 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72141249 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 72141249 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72141249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 72141249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72141249 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 72141249 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74779.546763 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74779.546763 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74779.546763 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74779.546763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74779.546763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74779.546763 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74680.381988 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74680.381988 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1936599 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31406.671872 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9110908 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1966387 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.633324 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 27876757750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14558.085450 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.965177 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16821.621245 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.444278 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000823 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958456 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29788 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 1936441 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31406.538176 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9110982 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1966231 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.633729 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 27876136750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14557.398525 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.847630 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.292021 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.444257 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.513376 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958451 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29790 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 970 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17650 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10392 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909058 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107501201 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107501201 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6137031 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6137031 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3742826 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3742826 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1107791 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107791 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7244822 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7244822 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7244822 # number of overall hits -system.cpu.l2cache.overall_hits::total 7244822 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 973 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1196996 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1197969 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 771343 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 771343 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 973 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1968339 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1969312 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 973 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1968339 # number of overall misses -system.cpu.l2cache.overall_misses::total 1969312 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71780000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 99229016250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 99300796250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63837741749 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 63837741749 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 71780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 163066757999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 163138537999 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 71780000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 163066757999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 163138537999 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 973 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7334027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7335000 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3742826 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3742826 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879134 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1879134 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 973 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9213161 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9214134 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 973 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9213161 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9214134 # number of overall (read+write) accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17653 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10389 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909119 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 107500175 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107500175 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.data 6137091 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6137091 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3742780 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3742780 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1107826 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107826 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7244917 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7244917 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7244917 # number of overall hits +system.cpu.l2cache.overall_hits::total 7244917 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 966 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1196905 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1197871 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 771286 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 771286 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 966 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1968191 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1969157 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 966 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1968191 # number of overall misses +system.cpu.l2cache.overall_misses::total 1969157 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71167250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98889965000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98961132250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63707909498 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 63707909498 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 71167250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 162597874498 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 162669041748 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 71167250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 162597874498 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 162669041748 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 966 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7333996 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7334962 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3742780 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3742780 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879112 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1879112 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 966 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9213108 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9214074 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 966 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9213108 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9214074 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163211 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163322 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.410478 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.410478 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163200 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163310 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.410452 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.410452 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.213644 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.213727 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.213629 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.213712 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.213644 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.213727 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73771.839671 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82898.369126 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 82890.956486 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82761.808623 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82761.808623 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73771.839671 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82844.854468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82840.371662 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73771.839671 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82844.854468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82840.371662 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.213629 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.213712 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73672.101449 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82621.398524 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82614.181535 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82599.592755 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82599.592755 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82608.467353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82608.467353 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -863,188 +960,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1020376 # number of writebacks -system.cpu.l2cache.writebacks::total 1020376 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196996 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1197969 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771343 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 771343 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 973 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1968339 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1969312 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 973 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1968339 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1969312 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59531000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84234330750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84293861750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54213569749 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54213569749 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59531000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138447900499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138507431499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59531000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138447900499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138507431499 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1020337 # number of writebacks +system.cpu.l2cache.writebacks::total 1020337 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196905 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1197871 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771286 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 771286 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1968191 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1969157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1968191 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1969157 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58998750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83895775000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83954773750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54083955498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54083955498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58998750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137979730498 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138038729248 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58998750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137979730498 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138038729248 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163211 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163322 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410478 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410478 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163310 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410452 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410452 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213644 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.213727 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.213712 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213644 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.213727 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61182.939363 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70371.438793 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70363.975821 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70284.646064 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70284.646064 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61182.939363 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70337.426886 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70332.903826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61182.939363 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70337.426886 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70332.903826 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.213712 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61075.310559 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70093.929761 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70086.656869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70121.790747 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70121.790747 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9209065 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.415581 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 713883338 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9213161 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.485169 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.415581 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997904 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 748 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2938 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1472907715 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1472907715 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 558369192 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 558369192 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155514142 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155514142 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 713883334 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 713883334 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 713883334 # number of overall hits -system.cpu.dcache.overall_hits::total 713883334 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12749578 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12749578 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5214360 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5214360 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17963938 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17963938 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17963938 # number of overall misses -system.cpu.dcache.overall_misses::total 17963938 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 385716453000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 385716453000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289481531698 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289481531698 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 675197984698 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 675197984698 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 675197984698 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 675197984698 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 571118770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 571118770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 731847272 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 731847272 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 731847272 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 731847272 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022324 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022324 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032442 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032442 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024546 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024546 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024546 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024546 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30253.272148 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30253.272148 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55516.215163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55516.215163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37586.301216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37586.301216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37586.301216 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14206702 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8627771 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1055420 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67280 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.460709 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 128.236787 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3742826 # number of writebacks -system.cpu.dcache.writebacks::total 3742826 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5415535 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5415535 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3335243 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3335243 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8750778 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8750778 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8750778 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8750778 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334043 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334043 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879117 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879117 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9213160 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9213160 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9213160 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9213160 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168998137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168998137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77338215218 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77338215218 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 246336352218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 246336352218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 246336352218 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 246336352218 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23042.970569 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23042.970569 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41156.679024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41156.679024 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 7334962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7334962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742780 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879112 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879112 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22170928 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829176832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 829238656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12957003 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12957003 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12957003 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10221354853 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1610750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14117356000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1197871 # Transaction distribution +system.membus.trans_dist::ReadResp 1197871 # Transaction distribution +system.membus.trans_dist::Writeback 1020337 # Transaction distribution +system.membus.trans_dist::ReadExReq 771286 # Transaction distribution +system.membus.trans_dist::ReadExResp 771286 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4958651 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2989494 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2989494 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2989494 # Request fanout histogram +system.membus.reqLayer0.occupancy 11823428000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 18423304250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- |