diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
| commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
| tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/long/se/60.bzip2/ref/alpha | |
| parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
| download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz | |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha')
3 files changed, 1318 insertions, 1319 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 77212a74e..9335161f5 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.998096 # Number of seconds simulated -sim_ticks 998095972500 # Number of ticks simulated -final_tick 998095972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.987579 # Number of seconds simulated +sim_ticks 987579062500 # Number of ticks simulated +final_tick 987579062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135518 # Simulator instruction rate (inst/s) -host_op_rate 135518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74327611 # Simulator tick rate (ticks/s) -host_mem_usage 465236 # Number of bytes of host memory used -host_seconds 13428.33 # Real time elapsed on the host +host_inst_rate 79028 # Simulator instruction rate (inst/s) +host_op_rate 79028 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42888030 # Simulator tick rate (ticks/s) +host_mem_usage 458304 # Number of bytes of host memory used +host_seconds 23026.92 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137579264 # Number of bytes read from this memory -system.physmem.bytes_read::total 137634240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125364928 # Number of bytes read from this memory +system.physmem.bytes_read::total 125419904 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67104640 # Number of bytes written to this memory -system.physmem.bytes_written::total 67104640 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149676 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150535 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048510 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048510 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 137841718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 137896799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55081 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55081 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 67232653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 67232653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 67232653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 137841718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 205129452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2150535 # Total number of read requests seen -system.physmem.writeReqs 1048510 # Total number of write requests seen -system.physmem.cpureqs 3199045 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 137634240 # Total number of bytes read from memory -system.physmem.bytesWritten 67104640 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 137634240 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67104640 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1104 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 1958827 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959686 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 126941662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 126997330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55667 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55667 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 65974991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 65974991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 65974991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 126941662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 192972321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959686 # Total number of read requests seen +system.physmem.writeReqs 1018055 # Total number of write requests seen +system.physmem.cpureqs 2977741 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125419904 # Total number of bytes read from memory +system.physmem.bytesWritten 65155520 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125419904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 577 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 134750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 134519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 135461 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 133443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 134821 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 134519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 135107 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 134152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 133438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 134313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 134956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 130690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 131784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 134689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 137104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 135685 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 65615 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 65313 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 65943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 64961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 65149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 64711 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 65179 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 64600 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64486 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 65220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 66941 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 67682 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 66873 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 122432 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 122601 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 122611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123178 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63395 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 65307 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 998095934500 # Total gap between requests +system.physmem.totGap 987579010500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2150535 # Categorize read packet sizes +system.physmem.readPktSize::6 1959686 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1048510 # categorize write packet sizes +system.physmem.writePktSize::6 1018055 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1835130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 153641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 24246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 14808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1651837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 82006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 19730119710 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 92821713710 # Sum of mem lat for all requests -system.physmem.totBusLat 8597724000 # Total cycles spent in databus access -system.physmem.totBankLat 64493870000 # Total cycles spent in bank access -system.physmem.avgQLat 9179.23 # Average queueing delay per request -system.physmem.avgBankLat 30005.09 # Average bank access latency per request +system.physmem.totQLat 19599583947 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85189869947 # Sum of mem lat for all requests +system.physmem.totBusLat 7836436000 # Total cycles spent in databus access +system.physmem.totBankLat 57753850000 # Total cycles spent in bank access +system.physmem.avgQLat 10004.34 # Average queueing delay per request +system.physmem.avgBankLat 29479.65 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43184.32 # Average memory access latency -system.physmem.avgRdBW 137.90 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 67.23 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 137.90 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 67.23 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43483.99 # Average memory access latency +system.physmem.avgRdBW 127.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 65.97 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 127.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 65.97 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.28 # Data bus utilization in percentage +system.physmem.busUtil 1.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.09 # Average read queue length over time -system.physmem.avgWrQLen 11.29 # Average write queue length over time -system.physmem.readRowHits 884898 # Number of row buffer hits during reads -system.physmem.writeRowHits 338451 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.28 # Row buffer hit rate for writes -system.physmem.avgGap 311998.09 # Average gap between requests +system.physmem.avgWrQLen 10.28 # Average write queue length over time +system.physmem.readRowHits 834542 # Number of row buffer hits during reads +system.physmem.writeRowHits 194109 # Number of row buffer hits during writes +system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes +system.physmem.avgGap 331653.76 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444628016 # DTB read hits +system.cpu.dtb.read_hits 444784364 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449525094 # DTB read accesses -system.cpu.dtb.write_hits 160917908 # DTB write hits +system.cpu.dtb.read_accesses 449681442 # DTB read accesses +system.cpu.dtb.write_hits 160833165 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162619212 # DTB write accesses -system.cpu.dtb.data_hits 605545924 # DTB hits +system.cpu.dtb.write_accesses 162534469 # DTB write accesses +system.cpu.dtb.data_hits 605617529 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612144306 # DTB accesses -system.cpu.itb.fetch_hits 232077768 # ITB hits +system.cpu.dtb.data_accesses 612215911 # DTB accesses +system.cpu.itb.fetch_hits 232120860 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232077790 # ITB accesses +system.cpu.itb.fetch_accesses 232120882 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1996191946 # number of cpu cycles simulated +system.cpu.numCycles 1975158126 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328934492 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253834142 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140072594 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232648931 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138176846 # Number of BTB hits +system.cpu.branch_predictor.lookups 328916009 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253846257 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140045817 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232481413 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138136467 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.392857 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175181145 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153753347 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669765696 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.418284 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175138589 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153777420 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669811898 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045968313 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3046014515 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651043890 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617989866 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121337623 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12136513 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133474136 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81726090 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.023232 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139616626 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 650984890 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617988746 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121313944 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12133415 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133447359 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81752917 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.010775 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139622793 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746553256 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746581569 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7548952 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 419177402 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1577014544 # Number of cycles cpu stages are processed. -system.cpu.activity 79.001148 # Percentage of cycles cpu is active +system.cpu.timesIdled 7474420 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 398305853 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576852273 # Number of cycles cpu stages are processed. +system.cpu.activity 79.834230 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -272,144 +272,144 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.096941 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.085383 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.096941 # CPI: Total CPI of All Threads -system.cpu.ipc 0.911626 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.085383 # CPI: Total CPI of All Threads +system.cpu.ipc 0.921334 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.911626 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 805412484 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190779462 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.652553 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1063871870 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932320076 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.704931 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1022192992 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973998954 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.792851 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1586493403 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409698543 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.524005 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 973220385 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022971561 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.246152 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.921334 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 784384186 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190773940 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.287525 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1042820423 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932337703 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 47.203193 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1001198544 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973959582 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.310461 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1565492748 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409665378 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.740890 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 952315389 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022842737 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.785360 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.791202 # Cycle average of tags in use -system.cpu.icache.total_refs 232076694 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 667.497042 # Cycle average of tags in use +system.cpu.icache.total_refs 232119756 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270170.772992 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270220.903376 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.791202 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.326070 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.326070 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232076694 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232076694 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232076694 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232076694 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232076694 # number of overall hits -system.cpu.icache.overall_hits::total 232076694 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses -system.cpu.icache.overall_misses::total 1072 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56100000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56100000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56100000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56100000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56100000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56100000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232077766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232077766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232077766 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232077766 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232077766 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232077766 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 667.497042 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325926 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325926 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232119756 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232119756 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232119756 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232119756 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232119756 # number of overall hits +system.cpu.icache.overall_hits::total 232119756 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1104 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1104 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1104 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1104 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1104 # number of overall misses +system.cpu.icache.overall_misses::total 1104 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58767000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58767000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58767000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58767000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58767000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58767000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232120860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232120860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232120860 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232120860 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232120860 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232120860 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52332.089552 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52332.089552 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52332.089552 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52332.089552 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52332.089552 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52332.089552 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 99 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53230.978261 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53230.978261 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53230.978261 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53230.978261 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45656000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45656000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45656000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45656000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45656000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45656000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46993000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46993000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46993000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46993000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46993000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46993000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.174622 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.174622 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.174622 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.174622 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.174622 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.174622 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54706.635623 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54706.635623 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107316 # number of replacements -system.cpu.dcache.tagsinuse 4082.375203 # Cycle average of tags in use -system.cpu.dcache.total_refs 595069266 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111412 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310324 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12653266000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.375203 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996674 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996674 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271434 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271434 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157797832 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157797832 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595069266 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595069266 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595069266 # number of overall hits -system.cpu.dcache.overall_hits::total 595069266 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324229 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324229 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2930670 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2930670 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10254899 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10254899 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10254899 # number of overall misses -system.cpu.dcache.overall_misses::total 10254899 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 169482879500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 169482879500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 114253006500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 114253006500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 283735886000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 283735886000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 283735886000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 283735886000 # number of overall miss cycles +system.cpu.dcache.replacements 9107377 # number of replacements +system.cpu.dcache.tagsinuse 4082.124534 # Cycle average of tags in use +system.cpu.dcache.total_refs 593539067 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111473 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.141944 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12681076000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.124534 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996612 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996612 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268755 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268755 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156270312 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156270312 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593539067 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593539067 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593539067 # number of overall hits +system.cpu.dcache.overall_hits::total 593539067 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326908 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326908 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4458190 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4458190 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 11785098 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11785098 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11785098 # number of overall misses +system.cpu.dcache.overall_misses::total 11785098 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 160313092500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 160313092500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 195290221000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 195290221000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 355603313500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 355603313500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 355603313500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 355603313500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -418,56 +418,56 @@ system.cpu.dcache.demand_accesses::cpu.data 605324165 # system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018234 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.018234 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016941 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016941 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016941 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016941 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23140.030097 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23140.030097 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38985.285447 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38985.285447 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27668.325744 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27668.325744 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27668.325744 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27668.325744 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 791552 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14185855 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 26512 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 205984 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.856367 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 68.868723 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027737 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027737 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21880.047149 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21880.047149 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43804.822361 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43804.822361 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30173.980182 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30173.980182 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9234267 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4818811 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 358092 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65601 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.787415 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.456365 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389638 # number of writebacks -system.cpu.dcache.writebacks::total 3389638 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101954 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101954 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1041533 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1041533 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1143487 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1143487 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1143487 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1143487 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222275 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222275 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889137 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889137 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111412 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111412 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111412 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111412 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 153198656000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 153198656000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69357589500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 69357589500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 222556245500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 222556245500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 222556245500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 222556245500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3693297 # number of writebacks +system.cpu.dcache.writebacks::total 3693297 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568993 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2568993 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2673625 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2673625 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2673625 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2673625 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222276 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222276 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889197 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111473 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111473 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111473 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111473 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144007395000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 144007395000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67943434500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 67943434500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211950829500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211950829500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211950829500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211950829500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -476,149 +476,149 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21211.966589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21211.966589 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36713.901374 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36713.901374 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24426.098337 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24426.098337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24426.098337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24426.098337 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19939.336990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19939.336990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35964.187165 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35964.187165 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23261.971967 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23261.971967 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2133754 # number of replacements -system.cpu.l2cache.tagsinuse 30562.068421 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8448353 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2163445 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905046 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 183967255500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14375.476614 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.146879 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16152.444929 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.438705 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001042 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.492934 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.932680 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5860981 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5860981 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389638 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389638 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100755 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1100755 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6961736 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6961736 # 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average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 438308 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53701.979045 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64721.293112 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 64713.260466 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70143.270284 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70143.270284 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66878.120015 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66878.120015 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 3445 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 127.230189 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413463 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39493.521537 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51377.836812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51370.339900 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58698.152751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58698.152751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39493.521537 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54064.028080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54058.208103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39493.521537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54064.028080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54058.208103 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41052.875437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51965.326261 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51957.371514 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57495.405160 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57495.405160 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 4dd96e908..4dfb5e529 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.622687 # Number of seconds simulated -sim_ticks 622686686500 # Number of ticks simulated -final_tick 622686686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.676099 # Number of seconds simulated +sim_ticks 676099363500 # Number of ticks simulated +final_tick 676099363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130099 # Simulator instruction rate (inst/s) -host_op_rate 130099 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46664017 # Simulator tick rate (ticks/s) -host_mem_usage 466244 # Number of bytes of host memory used -host_seconds 13344.04 # Real time elapsed on the host +host_inst_rate 178127 # Simulator instruction rate (inst/s) +host_op_rate 178127 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69371375 # Simulator tick rate (ticks/s) +host_mem_usage 459324 # Number of bytes of host memory used +host_seconds 9746.09 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138173120 # Number of bytes read from this memory -system.physmem.bytes_read::total 138234624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67206720 # Number of bytes written to this memory -system.physmem.bytes_written::total 67206720 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2158955 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2159916 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050105 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050105 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 98772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 221898305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 221997077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 98772 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 98772 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 107930234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 107930234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 107930234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 98772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 221898305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 329927311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2159916 # Total number of read requests seen -system.physmem.writeReqs 1050105 # Total number of write requests seen -system.physmem.cpureqs 3210021 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 138234624 # Total number of bytes read from memory -system.physmem.bytesWritten 67206720 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 138234624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67206720 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1101 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125805120 # Number of bytes read from this memory +system.physmem.bytes_read::total 125866688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265216 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265216 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965705 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966667 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019769 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019769 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 186074898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 186165961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96531989 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96531989 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96531989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 186074898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 282697950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966667 # Total number of read requests seen +system.physmem.writeReqs 1019769 # Total number of write requests seen +system.physmem.cpureqs 2986436 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125866688 # Total number of bytes read from memory +system.physmem.bytesWritten 65265216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125866688 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65265216 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 625 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 135516 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 134944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 135958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 133984 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 135382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 135012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 135645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 134678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 134063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 135260 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 135483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 131205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 132348 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 135290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 137712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 136335 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 65727 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 65366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 66027 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 65044 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 65255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 64804 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 65281 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65090 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 64712 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65787 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64601 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 65333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 67038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 67805 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 66971 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 123034 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123551 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 123227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 121682 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123042 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122572 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 124906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 123907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121965 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 123012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120476 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 120832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 122358 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 124956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123644 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63494 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63931 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63515 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 63255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62796 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63537 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 62612 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63480 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 64069 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 63419 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64057 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64815 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 65441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64562 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 622686634000 # Total gap between requests +system.physmem.totGap 676099295000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2159916 # Categorize read packet sizes +system.physmem.readPktSize::6 1966667 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1050105 # categorize write packet sizes +system.physmem.writePktSize::6 1019769 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1715217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 265103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 37466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 21744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13852 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9060 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1634338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 235140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 26277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 22793561782 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 94682781782 # Sum of mem lat for all requests -system.physmem.totBusLat 8635260000 # Total cycles spent in databus access -system.physmem.totBankLat 63253960000 # Total cycles spent in bank access -system.physmem.avgQLat 10558.37 # Average queueing delay per request -system.physmem.avgBankLat 29300.32 # Average bank access latency per request +system.physmem.totQLat 20663639504 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85829737504 # Sum of mem lat for all requests +system.physmem.totBusLat 7864168000 # Total cycles spent in databus access +system.physmem.totBankLat 57301930000 # Total cycles spent in bank access +system.physmem.avgQLat 10510.27 # Average queueing delay per request +system.physmem.avgBankLat 29145.83 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43858.68 # Average memory access latency -system.physmem.avgRdBW 222.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 107.93 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 222.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 107.93 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43656.11 # Average memory access latency +system.physmem.avgRdBW 186.17 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 96.53 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 186.17 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 96.53 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.06 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.91 # Average write queue length over time -system.physmem.readRowHits 893342 # Number of row buffer hits during reads -system.physmem.writeRowHits 340237 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.40 # Row buffer hit rate for writes -system.physmem.avgGap 193982.11 # Average gap between requests +system.physmem.busUtil 1.77 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.avgWrQLen 11.69 # Average write queue length over time +system.physmem.readRowHits 840809 # Number of row buffer hits during reads +system.physmem.writeRowHits 193935 # Number of row buffer hits during writes +system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 19.02 # Row buffer hit rate for writes +system.physmem.avgGap 226390.02 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 610476386 # DTB read hits -system.cpu.dtb.read_misses 10761875 # DTB read misses +system.cpu.dtb.read_hits 623300287 # DTB read hits +system.cpu.dtb.read_misses 11248161 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 621238261 # DTB read accesses -system.cpu.dtb.write_hits 207269464 # DTB write hits -system.cpu.dtb.write_misses 6561537 # DTB write misses +system.cpu.dtb.read_accesses 634548448 # DTB read accesses +system.cpu.dtb.write_hits 212126260 # DTB write hits +system.cpu.dtb.write_misses 7156273 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 213831001 # DTB write accesses -system.cpu.dtb.data_hits 817745850 # DTB hits -system.cpu.dtb.data_misses 17323412 # DTB misses +system.cpu.dtb.write_accesses 219282533 # DTB write accesses +system.cpu.dtb.data_hits 835426547 # DTB hits +system.cpu.dtb.data_misses 18404434 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 835069262 # DTB accesses -system.cpu.itb.fetch_hits 398378101 # ITB hits -system.cpu.itb.fetch_misses 55 # ITB misses +system.cpu.dtb.data_accesses 853830981 # DTB accesses +system.cpu.itb.fetch_hits 409165317 # ITB hits +system.cpu.itb.fetch_misses 53 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398378156 # ITB accesses +system.cpu.itb.fetch_accesses 409165370 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,245 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1245373374 # number of cpu cycles simulated +system.cpu.numCycles 1352198728 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 378146140 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 290510585 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18737073 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 264395160 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 259999350 # Number of BTB hits +system.cpu.BPredUnit.lookups 392126599 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 302845458 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19199722 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 274650283 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 270818962 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25131917 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6182 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 409812987 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3135210650 # Number of instructions fetch has processed -system.cpu.fetch.Branches 378146140 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 285131267 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 571966611 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 132239561 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 126137605 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1394 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 398378101 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10155921 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214707352 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.581042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.162326 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25776268 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6145 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 421462775 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3238747115 # Number of instructions fetch has processed +system.cpu.fetch.Branches 392126599 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 296595230 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 591261083 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 148936596 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 163448952 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1316 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 409165317 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10196267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1298229870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494741 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.143526 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 642740741 52.91% 52.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42508733 3.50% 56.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22198972 1.83% 58.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40683898 3.35% 61.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 126205169 10.39% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63532228 5.23% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40428272 3.33% 80.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30073881 2.48% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 206335458 16.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 706968787 54.46% 54.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 44358932 3.42% 57.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22743833 1.75% 59.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 41944085 3.23% 62.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 132056857 10.17% 73.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 64435006 4.96% 77.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41239075 3.18% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30635006 2.36% 83.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 213848289 16.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214707352 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.303641 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.517486 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 437634335 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 113109865 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542282236 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14893078 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 106787838 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60009942 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1008 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3056719356 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2151 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 106787838 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 458205445 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 68879857 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5925 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535635557 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45192730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2974950452 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 455085 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1725044 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40939895 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2225174239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3842201349 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3840803931 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1397418 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1298229870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289992 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.395171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 455239490 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 145264666 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 557656082 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18015537 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 122054095 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 61382914 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1012 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3154733525 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2110 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 122054095 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 478678718 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 92924622 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7988 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 549590922 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 54973525 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3070816575 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 560752 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1743859 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 49056518 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2295520192 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3973370931 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3971968228 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1402703 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 848971276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 208 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 208 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94220163 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 674209051 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 250003668 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 60248313 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34574137 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2672716058 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2475684354 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3185220 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 926051369 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 394490469 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214707352 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.038091 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971432 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 919317229 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 211 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 118384405 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 691487195 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 258255800 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68719353 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37210437 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2756294295 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 187 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2536632821 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3950694 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1007358741 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 432150244 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 158 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1298229870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.953917 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.961710 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 391612222 32.24% 32.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 190116739 15.65% 47.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 180710183 14.88% 62.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153608021 12.65% 75.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136709031 11.25% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80377873 6.62% 93.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 61799975 5.09% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14388617 1.18% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5384691 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 442263739 34.07% 34.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 208903385 16.09% 50.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 191557841 14.76% 64.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152463661 11.74% 76.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 137672348 10.60% 87.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81203098 6.25% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 63863451 4.92% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15081593 1.16% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5220754 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214707352 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1298229870 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2236018 11.81% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12183595 64.36% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4510642 23.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2156518 11.37% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12254343 64.62% 76.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4551680 24.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1615926808 65.27% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 102 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 638812583 25.80% 91.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 220944337 8.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1658475044 65.38% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 273 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 652209568 25.71% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 225947593 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2475684354 # Type of FU issued -system.cpu.iq.rate 1.987905 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18930255 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007646 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6186206687 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3597520072 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2374361589 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1984848 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1351695 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 870010 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2493639169 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 975440 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 56324993 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2536632821 # Type of FU issued +system.cpu.iq.rate 1.875932 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18962541 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007475 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6392425036 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3762406457 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2431792022 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1983711 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1351957 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 870252 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2554620629 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 974733 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62690136 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 229613388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 251555 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 105716 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 89275166 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 246891532 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263108 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 106999 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 97527298 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 232 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 90239 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 177 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1449625 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 106787838 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30509174 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1004696 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2814392916 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16951249 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 674209051 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 250003668 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 211284 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14280 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 105716 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13148912 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8849149 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 21998061 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2424970447 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 621239857 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 50713907 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 122054095 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 42236040 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1169448 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2901607263 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 18449890 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 691487195 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 258255800 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 187 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 295034 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19978 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 106999 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13433299 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8961049 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22394348 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2485079596 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 634549945 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 51553225 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141676677 # number of nop insts executed -system.cpu.iew.exec_refs 835070896 # number of memory reference insts executed -system.cpu.iew.exec_branches 296780799 # Number of branches executed -system.cpu.iew.exec_stores 213831039 # Number of stores executed -system.cpu.iew.exec_rate 1.947183 # Inst execution rate -system.cpu.iew.wb_sent 2403689836 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2375231599 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1360982490 # num instructions producing a value -system.cpu.iew.wb_consumers 1724379175 # num instructions consuming a value +system.cpu.iew.exec_nop 145312781 # number of nop insts executed +system.cpu.iew.exec_refs 853832523 # number of memory reference insts executed +system.cpu.iew.exec_branches 304694140 # Number of branches executed +system.cpu.iew.exec_stores 219282578 # Number of stores executed +system.cpu.iew.exec_rate 1.837806 # Inst execution rate +system.cpu.iew.wb_sent 2461943508 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2432662274 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1394848463 # num instructions producing a value +system.cpu.iew.wb_consumers 1766930878 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907245 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789259 # average fanout of values written-back +system.cpu.iew.wb_rate 1.799042 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789419 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 754743358 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 860868467 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18736187 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1107919514 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.642520 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504559 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19198826 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1176175775 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.547201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.484504 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 582245438 52.55% 52.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181606604 16.39% 68.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90875132 8.20% 77.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53034266 4.79% 81.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36917610 3.33% 85.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29689254 2.68% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22142026 2.00% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22921878 2.07% 92.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88487306 7.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 658247718 55.97% 55.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175915600 14.96% 70.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90578875 7.70% 78.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53177308 4.52% 83.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35329719 3.00% 86.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23851430 2.03% 88.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 23326017 1.98% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23350140 1.99% 92.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 92398968 7.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1107919514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1176175775 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,373 +475,371 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88487306 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 92398968 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3508176492 # The number of ROB reads -system.cpu.rob.rob_writes 5255937619 # The number of ROB writes -system.cpu.timesIdled 768601 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30666022 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3678646200 # The number of ROB reads +system.cpu.rob.rob_writes 5483460601 # The number of ROB writes +system.cpu.timesIdled 829567 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53968858 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.717363 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.717363 # CPI: Total CPI of All Threads -system.cpu.ipc 1.393995 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.393995 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3260141632 # number of integer regfile reads -system.cpu.int_regfile_writes 1905484731 # number of integer regfile writes -system.cpu.fp_regfile_reads 51179 # number of floating regfile reads -system.cpu.fp_regfile_writes 563 # number of floating regfile writes +system.cpu.cpi 0.778897 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.778897 # CPI: Total CPI of All Threads +system.cpu.ipc 1.283867 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.283867 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3341460388 # number of integer regfile reads +system.cpu.int_regfile_writes 1950187380 # number of integer regfile writes +system.cpu.fp_regfile_reads 51936 # number of floating regfile reads +system.cpu.fp_regfile_writes 538 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 770.400860 # Cycle average of tags in use -system.cpu.icache.total_refs 398376643 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 414543.853278 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 771.801258 # Cycle average of tags in use +system.cpu.icache.total_refs 409163812 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 962 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 425326.207900 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 770.400860 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.376172 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.376172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 398376643 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 398376643 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 398376643 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 398376643 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 398376643 # number of overall hits -system.cpu.icache.overall_hits::total 398376643 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1458 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1458 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1458 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1458 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1458 # number of overall misses -system.cpu.icache.overall_misses::total 1458 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 53978500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 53978500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 53978500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 53978500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 53978500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 53978500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 398378101 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 398378101 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 398378101 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 398378101 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 398378101 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 398378101 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 771.801258 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.376856 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.376856 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 409163812 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 409163812 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 409163812 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 409163812 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 409163812 # number of overall hits +system.cpu.icache.overall_hits::total 409163812 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1504 # 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number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 409165316 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 409165316 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37022.290809 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37022.290809 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37022.290809 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37022.290809 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37022.290809 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37022.290809 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53556.515293 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53556.515293 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53556.515293 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53556.515293 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1029 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37991000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37991000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 542 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 542 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 542 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 542 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 542 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 542 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 962 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 962 # 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mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39532.778356 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39532.778356 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39532.778356 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39532.778356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39532.778356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39532.778356 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59324.323285 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59324.323285 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176449 # number of replacements -system.cpu.dcache.tagsinuse 4086.538678 # Cycle average of tags in use -system.cpu.dcache.total_refs 700391806 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180545 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.290874 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5478544000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.538678 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997690 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997690 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 544376569 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 544376569 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156015231 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156015231 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 700391800 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 164485394500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 164485394500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 131300824319 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 131300824319 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 62500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 62500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 295786218819 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 295786218819 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 295786218819 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 295786218819 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 554129499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 554129499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 9177397 # number of replacements +system.cpu.dcache.tagsinuse 4086.580271 # Cycle average of tags in use +system.cpu.dcache.total_refs 703801568 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9181493 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.654371 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5761373000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.580271 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997700 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997700 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 548148518 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 548148518 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155653046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155653046 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 703801564 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 703801564 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 703801564 # number of overall hits +system.cpu.dcache.overall_hits::total 703801564 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11295128 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11295128 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5075456 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5075456 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 497136442889 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 497136442889 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 497136442889 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 559443646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 559443646 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 8 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 8 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 714858001 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 714858001 # 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miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.020236 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16865.228654 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16865.228654 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27857.686163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27857.686163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20446.710150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20446.710150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20446.710150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20446.710150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 200506 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3116753 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 10498 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65116 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.099448 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 47.864626 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 720172148 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 720172148 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 720172148 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 720172148 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020190 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020190 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031578 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031578 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24817.886747 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24817.886747 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42718.375529 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42718.375529 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30367.666962 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30367.666962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30367.666962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30367.666962 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10443209 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5645556 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 732857 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.249996 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 86.680014 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3416510 # number of writebacks -system.cpu.dcache.writebacks::total 3416510 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2456183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2456183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2829474 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 28500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 28500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126220260844 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126220260844 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126220260844 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126220260844 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013168 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013168 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9181492 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9181492 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214870111300 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214870111300 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013045 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013045 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.125000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.125000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012842 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415406 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.415406 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163141 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163251 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411497 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411497 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235166 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.235246 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214094 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235166 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.235246 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38526.014568 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50677.063990 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50668.586142 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49614.172001 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49614.172001 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38526.014568 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50291.804137 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50286.569246 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38526.014568 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50291.804137 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50286.569246 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 138175 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214094 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58314.449064 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67499.766079 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67492.350197 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67011.047781 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67011.047781 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58314.449064 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67307.050651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67302.651898 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58314.449064 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67307.050651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67302.651898 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 4214 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 32.789511 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050105 # number of writebacks -system.cpu.l2cache.writebacks::total 1050105 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376412 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1377373 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782543 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782543 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2158955 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2159916 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2158955 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2159916 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33564956 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 64705839431 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 64739404387 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36015294954 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36015294954 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33564956 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 100721134385 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 100754699341 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33564956 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 100721134385 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 100754699341 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019769 # number of writebacks +system.cpu.l2cache.writebacks::total 1019769 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190572 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191534 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775133 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775133 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965705 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966667 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965705 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966667 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 43990994 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 65246294234 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65290285228 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 42161089674 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 42161089674 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43990994 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107407383908 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 107451374902 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43990994 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107407383908 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 107451374902 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188741 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415406 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163141 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163251 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411497 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411497 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235166 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235246 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214094 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235166 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235246 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34927.113424 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47010.516786 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47002.086136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46023.406962 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46023.406962 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34927.113424 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46652.725224 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 46647.508209 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34927.113424 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46652.725224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46647.508209 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214094 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45728.683992 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54802.476653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54795.150812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54392.071650 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54392.071650 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45728.683992 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54640.642369 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54636.283063 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45728.683992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54640.642369 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54636.283063 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 78e7b43f1..3a71ce0c3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.631385 # Number of seconds simulated -sim_ticks 2631384990000 # Number of ticks simulated -final_tick 2631384990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.623386 # Number of seconds simulated +sim_ticks 2623386226000 # Number of ticks simulated +final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011793 # Simulator instruction rate (inst/s) -host_op_rate 1011793 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1463043658 # Simulator tick rate (ticks/s) -host_mem_usage 219388 # Number of bytes of host memory used -host_seconds 1798.57 # Real time elapsed on the host +host_inst_rate 1789114 # Simulator instruction rate (inst/s) +host_op_rate 1789114 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2579177735 # Simulator tick rate (ticks/s) +host_mem_usage 217052 # Number of bytes of host memory used +host_seconds 1017.14 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137580288 # Number of bytes read from this memory -system.physmem.bytes_read::total 137631616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125367104 # Number of bytes read from this memory +system.physmem.bytes_read::total 125418432 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67105600 # Number of bytes written to this memory -system.physmem.bytes_written::total 67105600 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65156928 # Number of bytes written to this memory +system.physmem.bytes_written::total 65156928 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149692 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150494 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048525 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52284363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52303869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25502008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25502008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25502008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52284363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77805877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1958861 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959663 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47788276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47807841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24836956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24836956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24836956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5262769980 # number of cpu cycles simulated +system.cpu.numCycles 5246772452 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5262769980 # Number of busy cycles +system.cpu.num_busy_cycles 5246772452 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.470356 # Cycle average of tags in use +system.cpu.icache.tagsinuse 612.458646 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.470356 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299058 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299058 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44120000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44120000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44120000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44120000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44120000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44120000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44182000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44182000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44182000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44182000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44182000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44182000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55012.468828 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55012.468828 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55012.468828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55012.468828 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55089.775561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55089.775561 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55089.775561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55089.775561 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42516000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42516000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42578000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42578000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42578000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42578000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42578000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42578000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53012.468828 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53012.468828 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53089.775561 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53089.775561 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.313701 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40977019000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.313701 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995926 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995926 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151059345000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151059345000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57691387000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57691387000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 208750732000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 208750732000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 208750732000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 208750732000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20915.353925 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20915.353925 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30535.529714 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30535.529714 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22910.099439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22910.099439 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389919 # number of writebacks -system.cpu.dcache.writebacks::total 3389919 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks +system.cpu.dcache.writebacks::total 3693497 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136614517000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 136614517000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53912747000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53912747000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190527264000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 190527264000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190527264000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 190527264000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -258,65 +258,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18915.353925 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18915.353925 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.529714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.529714 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2133721 # number of replacements -system.cpu.l2cache.tagsinuse 30159.988647 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8449191 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2163414 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905490 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 496965874000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14375.657027 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 37.778500 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15746.553119 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.438710 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001153 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.480547 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.920410 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5861531 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5861531 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389919 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389919 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100511 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1100511 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6962042 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6962042 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6962042 # number of overall hits -system.cpu.l2cache.overall_hits::total 6962042 # number of overall hits +system.cpu.l2cache.replacements 1926937 # number of replacements +system.cpu.l2cache.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8959453 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1956729 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.578791 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693497 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108019 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108019 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7152873 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7152873 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111795110000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 111836824000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41714000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111795110000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 111836824000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958861 # number of overall misses +system.cpu.l2cache.overall_misses::total 1959663 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41776000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61258944000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61300720000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40629030000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40629030000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41776000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101887974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101929750000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41776000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101887974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101929750000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3389919 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3389919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693497 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3693497 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses @@ -326,27 +326,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 802 system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188425 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188515 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417509 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417509 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163042 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163135 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413536 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413536 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235926 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.235993 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214982 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.215051 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235926 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.235993 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52012.468828 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.992605 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52007.995241 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.315666 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.315666 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52005.178345 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52005.178345 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214982 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.215051 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52089.775561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52021.930093 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52021.976269 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.763725 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.763725 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52013.917699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52013.917699 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,52 +355,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1048525 # number of writebacks -system.cpu.l2cache.writebacks::total 1048525 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1018077 # number of writebacks +system.cpu.l2cache.writebacks::total 1018077 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360883 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1361685 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788809 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 788809 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177560 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178362 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781301 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781301 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2149692 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2150494 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958861 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1959663 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2149692 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2150494 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32090000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54446197000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54478287000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31552609000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31552609000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32090000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85998806000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86030896000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32090000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85998806000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86030896000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958861 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959663 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32152000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47128224000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47160376000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31253418000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31253418000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78381642000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78413794000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78381642000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78413794000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188425 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188515 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417509 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417509 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163135 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413536 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413536 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.215051 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235993 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40012.468828 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.992605 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40007.995241 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.315666 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.315666 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40012.468828 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.175625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.178345 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.215051 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40089.775561 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.930093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.976269 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.763725 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.763725 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |