diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/long/se/60.bzip2/ref/alpha | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha')
4 files changed, 1363 insertions, 1290 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index f20aedd28..df378c8bf 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.007337 # Number of seconds simulated -sim_ticks 1007336591500 # Number of ticks simulated -final_tick 1007336591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.005768 # Number of seconds simulated +sim_ticks 1005767806500 # Number of ticks simulated +final_tick 1005767806500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109896 # Simulator instruction rate (inst/s) -host_op_rate 109896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60832901 # Simulator tick rate (ticks/s) -host_mem_usage 265436 # Number of bytes of host memory used -host_seconds 16559.08 # Real time elapsed on the host +host_inst_rate 106626 # Simulator instruction rate (inst/s) +host_op_rate 106626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58930745 # Simulator tick rate (ticks/s) +host_mem_usage 266468 # Number of bytes of host memory used +host_seconds 17066.95 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory -system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365120 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420096 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory -system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155584 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155584 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 124452002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 124506578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 64680982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 64680982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 64680982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 124452002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 189187560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959688 # Number of read requests accepted -system.physmem.writeReqs 1018055 # Number of write requests accepted -system.physmem.readBursts 1959688 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018055 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125336064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83968 # Total number of bytes read from write queue -system.physmem.bytesWritten 65153920 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125420032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65155520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1312 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 1958830 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959689 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018056 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018056 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 54661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 124646185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 124700846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 64781934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 64781934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 64781934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 124646185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 189482780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959689 # Number of read requests accepted +system.physmem.writeReqs 1018056 # Number of write requests accepted +system.physmem.readBursts 1959689 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018056 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125339392 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 80704 # Total number of bytes read from write queue +system.physmem.bytesWritten 65154112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125420096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65155584 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1261 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118685 # Per bank write bursts -system.physmem.perBankRdBursts::1 114026 # Per bank write bursts -system.physmem.perBankRdBursts::2 116162 # Per bank write bursts -system.physmem.perBankRdBursts::3 117671 # Per bank write bursts -system.physmem.perBankRdBursts::4 117731 # Per bank write bursts -system.physmem.perBankRdBursts::5 117464 # Per bank write bursts -system.physmem.perBankRdBursts::6 119807 # Per bank write bursts -system.physmem.perBankRdBursts::7 124441 # Per bank write bursts -system.physmem.perBankRdBursts::8 126920 # Per bank write bursts +system.physmem.perBankRdBursts::0 118688 # Per bank write bursts +system.physmem.perBankRdBursts::1 114039 # Per bank write bursts +system.physmem.perBankRdBursts::2 116164 # Per bank write bursts +system.physmem.perBankRdBursts::3 117666 # Per bank write bursts +system.physmem.perBankRdBursts::4 117733 # Per bank write bursts +system.physmem.perBankRdBursts::5 117466 # Per bank write bursts +system.physmem.perBankRdBursts::6 119809 # Per bank write bursts +system.physmem.perBankRdBursts::7 124448 # Per bank write bursts +system.physmem.perBankRdBursts::8 126913 # Per bank write bursts system.physmem.perBankRdBursts::9 130015 # Per bank write bursts -system.physmem.perBankRdBursts::10 128574 # Per bank write bursts -system.physmem.perBankRdBursts::11 130216 # Per bank write bursts -system.physmem.perBankRdBursts::12 125899 # Per bank write bursts -system.physmem.perBankRdBursts::13 125145 # Per bank write bursts -system.physmem.perBankRdBursts::14 122505 # Per bank write bursts -system.physmem.perBankRdBursts::15 123115 # Per bank write bursts +system.physmem.perBankRdBursts::10 128579 # Per bank write bursts +system.physmem.perBankRdBursts::11 130223 # Per bank write bursts +system.physmem.perBankRdBursts::12 125906 # Per bank write bursts +system.physmem.perBankRdBursts::13 125163 # Per bank write bursts +system.physmem.perBankRdBursts::14 122509 # Per bank write bursts +system.physmem.perBankRdBursts::15 123107 # Per bank write bursts system.physmem.perBankWrBursts::0 61223 # Per bank write bursts system.physmem.perBankWrBursts::1 61467 # Per bank write bursts system.physmem.perBankWrBursts::2 60558 # Per bank write bursts -system.physmem.perBankWrBursts::3 61215 # Per bank write bursts +system.physmem.perBankWrBursts::3 61216 # Per bank write bursts system.physmem.perBankWrBursts::4 61647 # Per bank write bursts -system.physmem.perBankWrBursts::5 63083 # Per bank write bursts -system.physmem.perBankWrBursts::6 64136 # Per bank write bursts +system.physmem.perBankWrBursts::5 63085 # Per bank write bursts +system.physmem.perBankWrBursts::6 64137 # Per bank write bursts system.physmem.perBankWrBursts::7 65614 # Per bank write bursts system.physmem.perBankWrBursts::8 65332 # Per bank write bursts -system.physmem.perBankWrBursts::9 65769 # Per bank write bursts -system.physmem.perBankWrBursts::10 65294 # Per bank write bursts -system.physmem.perBankWrBursts::11 65608 # Per bank write bursts -system.physmem.perBankWrBursts::12 64146 # Per bank write bursts -system.physmem.perBankWrBursts::13 64202 # Per bank write bursts -system.physmem.perBankWrBursts::14 64550 # Per bank write bursts +system.physmem.perBankWrBursts::9 65770 # Per bank write bursts +system.physmem.perBankWrBursts::10 65297 # Per bank write bursts +system.physmem.perBankWrBursts::11 65611 # Per bank write bursts +system.physmem.perBankWrBursts::12 64139 # Per bank write bursts +system.physmem.perBankWrBursts::13 64200 # Per bank write bursts +system.physmem.perBankWrBursts::14 64551 # Per bank write bursts system.physmem.perBankWrBursts::15 64186 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1007336518500 # Total gap between requests +system.physmem.totGap 1005767733500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1959688 # Read request sizes (log2) +system.physmem.readPktSize::6 1959689 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018055 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1664981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 198590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018056 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1667897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 193105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 75870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,76 +144,76 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 34916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 48946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 53936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 56821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 58079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 58536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 58949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 59504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 64559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 64811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 64584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 72712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 14814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 29926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1266500 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 109.102187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 83.148932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 142.836675 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 979529 77.34% 77.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 199046 15.72% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 36524 2.88% 95.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 14982 1.18% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8864 0.70% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4419 0.35% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2809 0.22% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2238 0.18% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 18089 1.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1266500 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 58142 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.680816 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.230571 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 58099 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1810756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 105.200206 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.912098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 131.997170 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1417049 78.26% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 275870 15.24% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50109 2.77% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20785 1.15% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12643 0.70% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6844 0.38% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5544 0.31% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3818 0.21% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18094 1.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1810756 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59345 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.999023 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.520477 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59305 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 9 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes @@ -222,120 +222,98 @@ system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 58142 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 58142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.509374 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.424358 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.849185 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29010 49.90% 49.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1046 1.80% 51.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 6657 11.45% 63.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 16493 28.37% 91.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 3312 5.70% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1061 1.82% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 264 0.45% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 97 0.17% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 56 0.10% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 17 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 18 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 13 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 5 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 5 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 5 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 3 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 28 0.05% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 9 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::59 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 58142 # Writes before turning the bus around for reads -system.physmem.totQLat 19659284500 # Total ticks spent queuing -system.physmem.totMemAccLat 80383790750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9791880000 # Total ticks spent in databus transfers -system.physmem.totBankLat 50932626250 # Total ticks spent accessing banks -system.physmem.avgQLat 10038.56 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26007.58 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 59345 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59345 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.154486 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.116028 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.157894 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27533 46.39% 46.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1478 2.49% 48.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 25288 42.61% 91.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4106 6.92% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 708 1.19% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 151 0.25% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 51 0.09% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 15 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59345 # Writes before turning the bus around for reads +system.physmem.totQLat 39644301500 # Total ticks spent queuing +system.physmem.totMemAccLat 76364826500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9792140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20242.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41046.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 124.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 64.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 124.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 64.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38992.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 124.62 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 64.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 124.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 64.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.48 # Data bus utilization in percentage system.physmem.busUtilRead 0.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.51 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 753336 # Number of row buffer hits during reads -system.physmem.writeRowHits 422191 # Number of row buffer hits during writes -system.physmem.readRowHitRate 38.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.47 # Row buffer hit rate for writes -system.physmem.avgGap 338288.60 # Average gap between requests -system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 12.29 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 189187560 # Throughput (bytes/s) +system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing +system.physmem.readRowHits 749188 # Number of row buffer hits during reads +system.physmem.writeRowHits 416511 # Number of row buffer hits during writes +system.physmem.readRowHitRate 38.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.91 # Row buffer hit rate for writes +system.physmem.avgGap 337761.54 # Average gap between requests +system.physmem.pageHitRate 39.16 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 297166155500 # Time in different power states +system.physmem.memoryStateTime::REF 33584720000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 675014883250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 189482780 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 1178393 # Transaction distribution system.membus.trans_dist::ReadResp 1178393 # Transaction distribution -system.membus.trans_dist::Writeback 1018055 # Transaction distribution -system.membus.trans_dist::ReadExReq 781295 # Transaction distribution -system.membus.trans_dist::ReadExResp 781295 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937431 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4937431 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190575552 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 190575552 # Total data (bytes) +system.membus.trans_dist::Writeback 1018056 # Transaction distribution +system.membus.trans_dist::ReadExReq 781296 # Transaction distribution +system.membus.trans_dist::ReadExResp 781296 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4937434 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190575680 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190575680 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11782666500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11779296500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18347417750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18345408000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 326511183 # Number of BP lookups -system.cpu.branchPred.condPredicted 252559725 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138218265 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220270477 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135614039 # Number of BTB hits +system.cpu.branchPred.lookups 326515024 # Number of BP lookups +system.cpu.branchPred.condPredicted 252570896 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138240520 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 220728385 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135412850 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.567052 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.348181 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444830139 # DTB read hits +system.cpu.dtb.read_hits 444825863 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449727217 # DTB read accesses -system.cpu.dtb.write_hits 160844128 # DTB write hits +system.cpu.dtb.read_accesses 449722941 # DTB read accesses +system.cpu.dtb.write_hits 160844247 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162545432 # DTB write accesses -system.cpu.dtb.data_hits 605674267 # DTB hits +system.cpu.dtb.write_accesses 162545551 # DTB write accesses +system.cpu.dtb.data_hits 605670110 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612272649 # DTB accesses -system.cpu.itb.fetch_hits 232118114 # ITB hits +system.cpu.dtb.data_accesses 612268492 # DTB accesses +system.cpu.itb.fetch_hits 231919747 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232118136 # ITB accesses +system.cpu.itb.fetch_accesses 231919769 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -349,34 +327,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2014673184 # number of cpu cycles simulated +system.cpu.numCycles 2011535614 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172428181 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154083002 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667622783 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172226277 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154288747 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667639381 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043825400 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 231 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043841998 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 576 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651695392 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617886274 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120493688 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11126119 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131619807 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83580161 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.161629 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139354623 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651725578 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617883712 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120527925 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11114137 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131642062 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83557916 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.171968 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139358188 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742144730 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742007028 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7512368 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 442846963 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571826221 # Number of cycles cpu stages are processed. -system.cpu.activity 78.018918 # Percentage of cycles cpu is active +system.cpu.timesIdled 7502506 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 439794636 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571740978 # Number of cycles cpu stages are processed. +system.cpu.activity 78.136373 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -388,226 +366,226 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.107097 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.105373 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.107097 # CPI: Total CPI of All Threads -system.cpu.ipc 0.903263 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.105373 # CPI: Total CPI of All Threads +system.cpu.ipc 0.904672 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.903263 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 827756857 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186916327 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.913591 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1081059316 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933613868 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.340711 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1042290381 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972382803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.265039 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1605047974 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409625210 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.332092 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 993337465 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021335719 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.694858 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.904672 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 824896841 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186638773 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.991686 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1077691733 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933843881 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.424427 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1039140389 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972395225 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.340940 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1601912902 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409622712 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.363682 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 990187341 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021348273 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.774556 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 668.288600 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 232116975 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 668.237280 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 231918592 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 270217.665891 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 269986.719441 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 668.288600 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.326313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.326313 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 668.237280 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.326288 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.326288 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 858 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 785 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.418945 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 464237087 # Number of tag accesses -system.cpu.icache.tags.data_accesses 464237087 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 232116975 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232116975 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232116975 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232116975 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232116975 # number of overall hits -system.cpu.icache.overall_hits::total 232116975 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses -system.cpu.icache.overall_misses::total 1139 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 81449500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 81449500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 81449500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 81449500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 81449500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 81449500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232118114 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232118114 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232118114 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232118114 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232118114 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232118114 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 463840351 # Number of tag accesses +system.cpu.icache.tags.data_accesses 463840351 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 231918592 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231918592 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231918592 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231918592 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231918592 # number of overall hits +system.cpu.icache.overall_hits::total 231918592 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 83508500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 83508500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 83508500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 83508500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 83508500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 83508500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231919746 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231919746 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231919746 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231919746 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231919746 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231919746 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71509.657594 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71509.657594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71509.657594 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71509.657594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71509.657594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71509.657594 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72364.384749 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72364.384749 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72364.384749 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72364.384749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72364.384749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72364.384749 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 418 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 162 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 418 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 295 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 295 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 295 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 295 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 295 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 295 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 63326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 63326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 63326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 63326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 63326500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 63326500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61831500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61831500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73721.187427 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73721.187427 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73721.187427 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73721.187427 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73721.187427 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73721.187427 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71980.791618 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71980.791618 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71980.791618 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71980.791618 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71980.791618 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71980.791618 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 813589109 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7222688 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7222688 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3693283 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889624 # Transaction distribution +system.cpu.toL2Bus.throughput 814858454 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7222692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7222692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3693285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889623 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916189 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21917907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916197 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21917915 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819503104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 819558080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819558080 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819503424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 819558400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819558400 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10096080500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10096085000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1443000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1445000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13971303500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13977776250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 1926957 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30916.680897 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8958690 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1956750 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.578352 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 67897094750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14926.990701 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.739406 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15954.950790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455536 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001060 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.486906 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.943502 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1926959 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30915.615811 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8958694 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1956752 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.578349 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 67887905750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14928.983043 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.785512 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15951.847256 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455596 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001062 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.486812 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943470 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29793 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 586 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 746 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12815 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15482 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909210 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106291134 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106291134 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6044295 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044295 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693283 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693283 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108329 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108329 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7152624 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7152624 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7152624 # number of overall hits -system.cpu.l2cache.overall_hits::total 7152624 # number of overall hits +system.cpu.l2cache.tags.tag_accesses 106291175 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106291175 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.data 6044299 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044299 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693285 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693285 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108327 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108327 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7152626 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7152626 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7152626 # number of overall hits +system.cpu.l2cache.overall_hits::total 7152626 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1177534 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 1178393 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 781296 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 781296 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1958829 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1959688 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958830 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1959689 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses -system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 62463500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 95853275750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 95915739250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68840007000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 68840007000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 62463500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 164693282750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 164755746250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 62463500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 164693282750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 164755746250 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958830 # number of overall misses +system.cpu.l2cache.overall_misses::total 1959689 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60968500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94791357750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94852326250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65779017750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 65779017750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 60968500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 160570375500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 160631344000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 60968500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 160570375500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 160631344000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221829 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222688 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3693283 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3693283 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889624 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889624 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221833 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222692 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693285 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3693285 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889623 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889623 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111453 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112312 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111456 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112315 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111453 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112312 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111456 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112315 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163152 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413466 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413466 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413467 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413467 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.214985 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.215059 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72716.530850 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81401.705386 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 81395.374251 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88110.133816 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88110.133816 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72716.530850 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84077.417044 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84072.437169 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72716.530850 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84077.417044 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84072.437169 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70976.135041 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80499.890237 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80492.947811 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84192.185484 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84192.185484 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70976.135041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81972.593589 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81967.773458 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70976.135041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81972.593589 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81967.773458 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -616,94 +594,94 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks -system.cpu.l2cache.writebacks::total 1018055 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1018056 # number of writebacks +system.cpu.l2cache.writebacks::total 1018056 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1958829 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1959688 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958830 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1959689 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51686000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 81095366750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 81147052750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59075528500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59075528500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51686000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140170895250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 140222581250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51686000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140170895250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 140222581250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958830 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959689 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 50186500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80032548250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80082734750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56010972750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56010972750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50186500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 136043521000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 136093707500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50186500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 136043521000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 136093707500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60169.965076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68868.811219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68862.470118 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75612.321210 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75612.321210 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60169.965076 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71558.515445 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71553.523444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60169.965076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71558.515445 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71553.523444 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58424.330617 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67966.231336 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67959.275683 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71689.824023 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71689.824023 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58424.330617 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69451.417938 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69446.584382 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58424.330617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69451.417938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69446.584382 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9107357 # number of replacements -system.cpu.dcache.tags.tagsinuse 4082.325879 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 593298406 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111453 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.115674 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 12706876000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4082.325879 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996662 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996662 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9107360 # number of replacements +system.cpu.dcache.tags.tagsinuse 4082.305318 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 593299863 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111456 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.115813 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 12706320250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4082.305318 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996657 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996657 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 560 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2879 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 619 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 574 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2872 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1219759783 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1219759783 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 437268768 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268768 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156029638 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156029638 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593298406 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593298406 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593298406 # number of overall hits -system.cpu.dcache.overall_hits::total 593298406 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7326895 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7326895 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4698864 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4698864 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 12025759 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12025759 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12025759 # number of overall misses -system.cpu.dcache.overall_misses::total 12025759 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 180765205750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 180765205750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 250221551250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 250221551250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 430986757000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 430986757000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 430986757000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 430986757000 # number of overall miss cycles +system.cpu.dcache.tags.tag_accesses 1219759786 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219759786 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 437268763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268763 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156031100 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156031100 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593299863 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593299863 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593299863 # number of overall hits +system.cpu.dcache.overall_hits::total 593299863 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326900 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326900 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4697402 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4697402 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12024302 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12024302 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12024302 # number of overall misses +system.cpu.dcache.overall_misses::total 12024302 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 179720219500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 179720219500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 246249534250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 246249534250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 425969753750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 425969753750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 425969753750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 425969753750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -714,54 +692,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029235 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029235 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24671.461206 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24671.461206 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53251.498926 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53251.498926 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35838.632472 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35838.632472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35838.632472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35838.632472 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11447989 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7764770 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 416735 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 73422 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.470668 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 105.755359 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029226 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029226 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019864 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019864 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019864 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019864 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24528.821125 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24528.821125 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52422.495296 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52422.495296 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35425.736459 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35425.736459 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35425.736459 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35425.736459 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10235273 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7848261 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 412771 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 73432 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.796492 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 106.877941 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693283 # number of writebacks -system.cpu.dcache.writebacks::total 3693283 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104624 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104624 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2809682 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2809682 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2914306 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2914306 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2914306 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2914306 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222271 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222271 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3693285 # number of writebacks +system.cpu.dcache.writebacks::total 3693285 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104626 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104626 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2808220 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2808220 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2912846 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2912846 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2912846 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2912846 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222274 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222274 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111453 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111453 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111453 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111453 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 163647011750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 163647011750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81975016250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 81975016250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245622028000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245622028000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245622028000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245622028000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9111456 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111456 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111456 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111456 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162584714500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162584714500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78915202250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 78915202250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 241499916750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 241499916750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 241499916750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 241499916750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -770,14 +748,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22658.663978 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22658.663978 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43391.804628 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43391.804628 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26957.503704 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26957.503704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26957.503704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26957.503704 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22511.568309 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22511.568309 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41772.154430 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41772.154430 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26505.085109 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26505.085109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26505.085109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26505.085109 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 2f4d3475f..c3541208a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.682192 # Number of seconds simulated -sim_ticks 682191807000 # Number of ticks simulated -final_tick 682191807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.680209 # Number of seconds simulated +sim_ticks 680209231000 # Number of ticks simulated +final_tick 680209231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139307 # Simulator instruction rate (inst/s) -host_op_rate 139307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54741914 # Simulator tick rate (ticks/s) -host_mem_usage 268504 # Number of bytes of host memory used -host_seconds 12461.96 # Real time elapsed on the host +host_inst_rate 134123 # Simulator instruction rate (inst/s) +host_op_rate 134123 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52551522 # Simulator tick rate (ticks/s) +host_mem_usage 268516 # Number of bytes of host memory used +host_seconds 12943.66 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125800064 # Number of bytes read from this memory -system.physmem.bytes_read::total 125861760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265984 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265984 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 964 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965626 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966590 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019781 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019781 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 184405709 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 184496147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 95671017 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 95671017 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 95671017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 184405709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 280167164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966590 # Number of read requests accepted -system.physmem.writeReqs 1019781 # Number of write requests accepted -system.physmem.readBursts 1966590 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1019781 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125780416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue -system.physmem.bytesWritten 65264896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125861760 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65265984 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125794880 # Number of bytes read from this memory +system.physmem.bytes_read::total 125856448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65262848 # Number of bytes written to this memory +system.physmem.bytes_written::total 65262848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965545 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966507 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019732 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019732 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 184935567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 185026081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95945255 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95945255 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95945255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 184935567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 280971335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966507 # Number of read requests accepted +system.physmem.writeReqs 1019732 # Number of write requests accepted +system.physmem.readBursts 1966507 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1019732 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125774784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81664 # Total number of bytes read from write queue +system.physmem.bytesWritten 65260864 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125856448 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65262848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1276 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118991 # Per bank write bursts -system.physmem.perBankRdBursts::1 114394 # Per bank write bursts -system.physmem.perBankRdBursts::2 116519 # Per bank write bursts -system.physmem.perBankRdBursts::3 118029 # Per bank write bursts -system.physmem.perBankRdBursts::4 118142 # Per bank write bursts -system.physmem.perBankRdBursts::5 117777 # Per bank write bursts -system.physmem.perBankRdBursts::6 120156 # Per bank write bursts -system.physmem.perBankRdBursts::7 124892 # Per bank write bursts -system.physmem.perBankRdBursts::8 127514 # Per bank write bursts -system.physmem.perBankRdBursts::9 130376 # Per bank write bursts -system.physmem.perBankRdBursts::10 129025 # Per bank write bursts -system.physmem.perBankRdBursts::11 130742 # Per bank write bursts -system.physmem.perBankRdBursts::12 126628 # Per bank write bursts -system.physmem.perBankRdBursts::13 125605 # Per bank write bursts -system.physmem.perBankRdBursts::14 122932 # Per bank write bursts -system.physmem.perBankRdBursts::15 123597 # Per bank write bursts -system.physmem.perBankWrBursts::0 61284 # Per bank write bursts -system.physmem.perBankWrBursts::1 61572 # Per bank write bursts -system.physmem.perBankWrBursts::2 60658 # Per bank write bursts -system.physmem.perBankWrBursts::3 61323 # Per bank write bursts -system.physmem.perBankWrBursts::4 61765 # Per bank write bursts -system.physmem.perBankWrBursts::5 63192 # Per bank write bursts -system.physmem.perBankWrBursts::6 64214 # Per bank write bursts -system.physmem.perBankWrBursts::7 65706 # Per bank write bursts -system.physmem.perBankWrBursts::8 65482 # Per bank write bursts -system.physmem.perBankWrBursts::9 65855 # Per bank write bursts -system.physmem.perBankWrBursts::10 65405 # Per bank write bursts -system.physmem.perBankWrBursts::11 65740 # Per bank write bursts -system.physmem.perBankWrBursts::12 64329 # Per bank write bursts -system.physmem.perBankWrBursts::13 64310 # Per bank write bursts -system.physmem.perBankWrBursts::14 64647 # Per bank write bursts -system.physmem.perBankWrBursts::15 64282 # Per bank write bursts +system.physmem.perBankRdBursts::0 118983 # Per bank write bursts +system.physmem.perBankRdBursts::1 114362 # Per bank write bursts +system.physmem.perBankRdBursts::2 116533 # Per bank write bursts +system.physmem.perBankRdBursts::3 118021 # Per bank write bursts +system.physmem.perBankRdBursts::4 118095 # Per bank write bursts +system.physmem.perBankRdBursts::5 117780 # Per bank write bursts +system.physmem.perBankRdBursts::6 120157 # Per bank write bursts +system.physmem.perBankRdBursts::7 124901 # Per bank write bursts +system.physmem.perBankRdBursts::8 127484 # Per bank write bursts +system.physmem.perBankRdBursts::9 130413 # Per bank write bursts +system.physmem.perBankRdBursts::10 129050 # Per bank write bursts +system.physmem.perBankRdBursts::11 130729 # Per bank write bursts +system.physmem.perBankRdBursts::12 126632 # Per bank write bursts +system.physmem.perBankRdBursts::13 125586 # Per bank write bursts +system.physmem.perBankRdBursts::14 122901 # Per bank write bursts +system.physmem.perBankRdBursts::15 123604 # Per bank write bursts +system.physmem.perBankWrBursts::0 61270 # Per bank write bursts +system.physmem.perBankWrBursts::1 61551 # Per bank write bursts +system.physmem.perBankWrBursts::2 60668 # Per bank write bursts +system.physmem.perBankWrBursts::3 61328 # Per bank write bursts +system.physmem.perBankWrBursts::4 61752 # Per bank write bursts +system.physmem.perBankWrBursts::5 63187 # Per bank write bursts +system.physmem.perBankWrBursts::6 64234 # Per bank write bursts +system.physmem.perBankWrBursts::7 65693 # Per bank write bursts +system.physmem.perBankWrBursts::8 65471 # Per bank write bursts +system.physmem.perBankWrBursts::9 65863 # Per bank write bursts +system.physmem.perBankWrBursts::10 65411 # Per bank write bursts +system.physmem.perBankWrBursts::11 65720 # Per bank write bursts +system.physmem.perBankWrBursts::12 64318 # Per bank write bursts +system.physmem.perBankWrBursts::13 64300 # Per bank write bursts +system.physmem.perBankWrBursts::14 64642 # Per bank write bursts +system.physmem.perBankWrBursts::15 64293 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 682191684500 # Total gap between requests +system.physmem.totGap 680209108500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1966590 # Read request sizes (log2) +system.physmem.readPktSize::6 1966507 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1019781 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1642976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 230548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019732 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1643607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 226349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 73697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 31804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 54150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 57221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 58425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 64812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 65271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 65616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 73465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 64939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 60584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 17452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 28201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 50211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 63111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see @@ -193,139 +193,130 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1251998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 113.111439 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 84.586325 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 150.844327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 955672 76.33% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 201584 16.10% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38062 3.04% 95.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 16101 1.29% 96.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9606 0.77% 97.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4835 0.39% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3234 0.26% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2576 0.21% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20328 1.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1251998 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 58888 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.373692 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.339848 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 58850 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1771936 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.810521 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.950451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 136.949127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1375751 77.64% 77.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 273384 15.43% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53057 2.99% 96.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21092 1.19% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12942 0.73% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6638 0.37% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4973 0.28% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3952 0.22% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20147 1.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1771936 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59540 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.963117 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 163.210264 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59503 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 10 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 8 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 58888 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 58888 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.317009 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.233410 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.918536 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 34047 57.82% 57.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 20086 34.11% 91.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 4266 7.24% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 290 0.49% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 84 0.14% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 30 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 14 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 5 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 4 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 12 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 19 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 9 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::78-79 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::86-87 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-89 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-105 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::106-107 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 58888 # Writes before turning the bus around for reads -system.physmem.totQLat 20653307250 # Total ticks spent queuing -system.physmem.totMemAccLat 80037239750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9826595000 # Total ticks spent in databus transfers -system.physmem.totBankLat 49557337500 # Total ticks spent accessing banks -system.physmem.avgQLat 10508.88 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 25215.93 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 59540 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59540 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.126318 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.084701 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.213811 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29197 49.04% 49.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1546 2.60% 51.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 22630 38.01% 89.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4967 8.34% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 921 1.55% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 191 0.32% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 48 0.08% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59540 # Writes before turning the bus around for reads +system.physmem.totQLat 40008960000 # Total ticks spent queuing +system.physmem.totMemAccLat 76857041250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9826155000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20358.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40724.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 184.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 95.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 184.50 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 95.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39108.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 184.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 185.03 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.19 # Data bus utilization in percentage system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.29 # Average write queue length when enqueuing -system.physmem.readRowHits 797879 # Number of row buffer hits during reads -system.physmem.writeRowHits 422825 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.46 # Row buffer hit rate for writes -system.physmem.avgGap 228435.01 # Average gap between requests -system.physmem.pageHitRate 40.89 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 7.23 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 280167164 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191439 # Transaction distribution -system.membus.trans_dist::ReadResp 1191439 # Transaction distribution -system.membus.trans_dist::Writeback 1019781 # Transaction distribution -system.membus.trans_dist::ReadExReq 775151 # Transaction distribution -system.membus.trans_dist::ReadExResp 775151 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4952961 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191127744 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191127744 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191127744 # Total data (bytes) +system.physmem.avgWrQLen 24.89 # Average write queue length when enqueuing +system.physmem.readRowHits 795143 # Number of row buffer hits during reads +system.physmem.writeRowHits 417847 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.98 # Row buffer hit rate for writes +system.physmem.avgGap 227781.20 # Average gap between requests +system.physmem.pageHitRate 40.64 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 135240615750 # Time in different power states +system.physmem.memoryStateTime::REF 22713600000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 522252858000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 280971335 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191350 # Transaction distribution +system.membus.trans_dist::ReadResp 1191350 # Transaction distribution +system.membus.trans_dist::Writeback 1019732 # Transaction distribution +system.membus.trans_dist::ReadExReq 775157 # Transaction distribution +system.membus.trans_dist::ReadExResp 775157 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952746 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4952746 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191119296 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191119296 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191119296 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11872683000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11871718000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18474077250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18474668250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 381618384 # Number of BP lookups -system.cpu.branchPred.condPredicted 296575373 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16092188 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262164042 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259697812 # Number of BTB hits +system.cpu.branchPred.lookups 381496982 # Number of BP lookups +system.cpu.branchPred.condPredicted 296448748 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16088801 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262281784 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259596653 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.059280 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24705469 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3069 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.976242 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24710775 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3135 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613976008 # DTB read hits -system.cpu.dtb.read_misses 11261750 # DTB read misses +system.cpu.dtb.read_hits 613956448 # DTB read hits +system.cpu.dtb.read_misses 11261576 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625237758 # DTB read accesses -system.cpu.dtb.write_hits 212363538 # DTB write hits -system.cpu.dtb.write_misses 7134748 # DTB write misses +system.cpu.dtb.read_accesses 625218024 # DTB read accesses +system.cpu.dtb.write_hits 212357219 # DTB write hits +system.cpu.dtb.write_misses 7142526 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219498286 # DTB write accesses -system.cpu.dtb.data_hits 826339546 # DTB hits -system.cpu.dtb.data_misses 18396498 # DTB misses +system.cpu.dtb.write_accesses 219499745 # DTB write accesses +system.cpu.dtb.data_hits 826313667 # DTB hits +system.cpu.dtb.data_misses 18404102 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844736044 # DTB accesses -system.cpu.itb.fetch_hits 391110222 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 844717769 # DTB accesses +system.cpu.itb.fetch_hits 391069582 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391110266 # ITB accesses +system.cpu.itb.fetch_accesses 391069621 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -339,138 +330,137 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1364383615 # number of cpu cycles simulated +system.cpu.numCycles 1360418463 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402585287 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3161125101 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381618384 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284403281 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574536383 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140665925 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 188120516 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1448 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 391110222 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8062763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1282059246 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.465662 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.145744 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402539494 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3160334453 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381496982 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284307428 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574405529 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140578200 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 186557630 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1439 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 391069582 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8066485 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1280247946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.468533 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146412 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 707522863 55.19% 55.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42675531 3.33% 58.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21787283 1.70% 60.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39707555 3.10% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129310443 10.09% 73.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61549431 4.80% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38571496 3.01% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28142716 2.20% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212791928 16.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 705842417 55.13% 55.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42672657 3.33% 58.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21781408 1.70% 60.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39699602 3.10% 63.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129277672 10.10% 73.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61541075 4.81% 78.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38576961 3.01% 81.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28126887 2.20% 83.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212729267 16.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1282059246 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.279700 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.316889 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434597074 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 169317553 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542454813 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18875119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116814687 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58354170 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 898 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3088496267 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2037 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116814687 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457547940 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 113953082 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6967 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535589228 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 58147342 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3006454755 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 609106 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1833248 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51828481 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2247677853 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3898974365 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3898830865 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 143499 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1280247946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.280426 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.323061 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434538205 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167760960 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542351250 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18854501 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116743030 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58351365 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 885 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3087789939 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2070 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116743030 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457481337 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 112438612 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7413 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535473100 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 58104454 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3005831981 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 610085 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1830591 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51785017 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2247201366 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3898074686 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3897930349 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 144336 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 871474890 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 178 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 177 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123676155 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679702242 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255475560 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67614908 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37053481 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2724914461 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 131 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509610552 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3196332 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 979670705 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 416123894 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 102 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1282059246 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.957484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971278 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 870998403 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 181 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123645792 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679622906 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255441649 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67625349 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36837000 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2724438630 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 139 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509429146 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3195077 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979206212 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 415660734 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 110 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1280247946 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.960112 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971405 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 440049739 34.32% 34.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203670606 15.89% 50.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185671301 14.48% 64.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153363283 11.96% 76.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133052268 10.38% 87.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80767651 6.30% 93.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65047769 5.07% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15319478 1.19% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5117151 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 438364734 34.24% 34.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203576191 15.90% 50.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185673841 14.50% 64.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153359678 11.98% 76.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133007255 10.39% 87.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80763135 6.31% 93.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65057682 5.08% 98.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15327988 1.20% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5117442 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1282059246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1280247946 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2188252 11.81% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11925862 64.39% 76.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4407339 23.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2183926 11.79% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11926883 64.38% 76.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4416070 23.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643881644 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 99 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643735577 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 265 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 274 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 161 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 23 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 33 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued @@ -493,84 +483,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641614566 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224113754 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641577426 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224115520 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509610552 # Type of FU issued -system.cpu.iq.rate 1.839373 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18521453 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007380 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6321098058 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3703474382 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413201675 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1900077 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1218284 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 852187 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527192648 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 939357 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62588107 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509429146 # Type of FU issued +system.cpu.iq.rate 1.844601 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18526879 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007383 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6318927693 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3702533179 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413056574 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1900501 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1218976 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 851931 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527016485 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 939540 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62611923 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235106579 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263309 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 109146 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94747058 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235027243 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263015 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 108918 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94713147 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 184 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1530387 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 189 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1519116 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116814687 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 54760955 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1302145 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2867095326 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8936600 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679702242 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255475560 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 285836 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18373 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 109146 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10363389 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8561306 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18924695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462265598 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625238282 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47344954 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116743030 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 54024400 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1298779 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2866611550 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8938226 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679622906 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255441649 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 139 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 284739 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17925 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 108918 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10360501 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8559141 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18919642 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462113163 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625218563 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47315983 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142180734 # number of nop insts executed -system.cpu.iew.exec_refs 844736593 # number of memory reference insts executed -system.cpu.iew.exec_branches 300891924 # Number of branches executed -system.cpu.iew.exec_stores 219498311 # Number of stores executed -system.cpu.iew.exec_rate 1.804673 # Inst execution rate -system.cpu.iew.wb_sent 2442007403 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2414053862 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388335082 # num instructions producing a value -system.cpu.iew.wb_consumers 1764294016 # num instructions consuming a value +system.cpu.iew.exec_nop 142172781 # number of nop insts executed +system.cpu.iew.exec_refs 844718328 # number of memory reference insts executed +system.cpu.iew.exec_branches 300875979 # Number of branches executed +system.cpu.iew.exec_stores 219499765 # Number of stores executed +system.cpu.iew.exec_rate 1.809820 # Inst execution rate +system.cpu.iew.wb_sent 2441867145 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413908505 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388259644 # num instructions producing a value +system.cpu.iew.wb_consumers 1764197986 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.769337 # insts written-back per cycle +system.cpu.iew.wb_rate 1.774387 # insts written-back per cycle system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 826637792 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 826160079 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16091391 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1165244559 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.561715 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.500982 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16088003 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1163504916 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.564050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.502160 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 651170378 55.88% 55.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175014835 15.02% 70.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86149099 7.39% 78.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53527990 4.59% 82.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34710349 2.98% 85.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26102733 2.24% 88.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21568948 1.85% 89.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22887442 1.96% 91.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94112785 8.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 649463962 55.82% 55.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174969107 15.04% 70.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86152065 7.40% 78.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53532710 4.60% 82.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34727147 2.98% 85.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26083842 2.24% 88.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21573250 1.85% 89.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22881203 1.97% 91.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94121630 8.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1165244559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1163504916 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -581,224 +571,259 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94112785 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1130719227 62.13% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 75 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 166 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction +system.cpu.commit.bw_lim_events 94121630 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3631770492 # The number of ROB reads -system.cpu.rob.rob_writes 5409749589 # The number of ROB writes -system.cpu.timesIdled 953701 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 82324369 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3629544291 # The number of ROB reads +system.cpu.rob.rob_writes 5408721730 # The number of ROB writes +system.cpu.timesIdled 949757 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 80170517 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.785915 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.785915 # CPI: Total CPI of All Threads -system.cpu.ipc 1.272402 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.272402 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318200326 # number of integer regfile reads -system.cpu.int_regfile_writes 1932098427 # number of integer regfile writes -system.cpu.fp_regfile_reads 30699 # number of floating regfile reads -system.cpu.fp_regfile_writes 520 # number of floating regfile writes +system.cpu.cpi 0.783631 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.783631 # CPI: Total CPI of All Threads +system.cpu.ipc 1.276110 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.276110 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3317990648 # number of integer regfile reads +system.cpu.int_regfile_writes 1931970641 # number of integer regfile writes +system.cpu.fp_regfile_reads 30869 # number of floating regfile reads +system.cpu.fp_regfile_writes 545 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1210780745 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297678 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297678 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3724768 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883565 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1928 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085326 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22087254 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825923008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 825984704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 825984704 # Total data (bytes) +system.cpu.toL2Bus.throughput 1214348707 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3725127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883613 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1924 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085799 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22087723 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825949632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 826011200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 826011200 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10177843430 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10178394945 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1605500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1603000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14065476499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14072846750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 773.695817 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391108717 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 964 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 405714.436722 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 772.655537 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391068098 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 962 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 406515.694387 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 773.695817 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377781 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377781 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 963 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.470215 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 782221404 # Number of tag accesses -system.cpu.icache.tags.data_accesses 782221404 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 391108717 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391108717 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391108717 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391108717 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391108717 # number of overall hits -system.cpu.icache.overall_hits::total 391108717 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1503 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1503 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1503 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1503 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1503 # number of overall misses -system.cpu.icache.overall_misses::total 1503 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 108284500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 108284500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 108284500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 108284500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 108284500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 108284500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391110220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391110220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391110220 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391110220 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391110220 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391110220 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 772.655537 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377273 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377273 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 961 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 902 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.469238 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 782140126 # Number of tag accesses +system.cpu.icache.tags.data_accesses 782140126 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 391068098 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391068098 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391068098 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391068098 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391068098 # number of overall hits +system.cpu.icache.overall_hits::total 391068098 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1484 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1484 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1484 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1484 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1484 # number of overall misses +system.cpu.icache.overall_misses::total 1484 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 102456750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 102456750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 102456750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 102456750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 102456750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 102456750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391069582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391069582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391069582 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391069582 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391069582 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391069582 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72045.575516 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72045.575516 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72045.575516 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72045.575516 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72045.575516 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72045.575516 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69040.936658 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69040.936658 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69040.936658 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69040.936658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69040.936658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69040.936658 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 69.800000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 203.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 539 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 539 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 539 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 539 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 539 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 539 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 964 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 964 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 964 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 964 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 964 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75722000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75722000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75722000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75722000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75722000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75722000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 522 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 522 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 522 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 522 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 522 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 522 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 962 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 962 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 71417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 71417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 71417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 71417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 71417000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 71417000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78549.792531 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78549.792531 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78549.792531 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78549.792531 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78549.792531 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78549.792531 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74238.045738 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74238.045738 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74238.045738 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74238.045738 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74238.045738 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74238.045738 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1933885 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31421.269549 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9058254 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1963664 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.612935 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28359986250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14571.956791 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.815575 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.497182 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.444701 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000818 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513382 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958901 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29779 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 974 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 1933800 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31420.392793 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9058700 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1963581 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.613357 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28339083250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14569.495652 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.490666 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16824.406475 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.444626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000808 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.513440 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958874 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29781 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 975 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 593 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17299 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10767 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908783 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107095317 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107095317 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6106239 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106239 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3724768 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3724768 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108414 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108414 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214653 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214653 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214653 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214653 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 964 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190475 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191439 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775151 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775151 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 964 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965626 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966590 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 964 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965626 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966590 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74752000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 99906666750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 99981418750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65179640000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 65179640000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 74752000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 165086306750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 165161058750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 74752000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 165086306750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 165161058750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 964 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296714 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297678 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3724768 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3724768 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883565 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883565 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 964 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180279 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181243 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 964 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180279 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181243 # number of overall (read+write) accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17306 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10757 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908844 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 107098594 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107098594 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.data 6106335 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6106335 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3725127 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3725127 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108456 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108456 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7214791 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7214791 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7214791 # number of overall hits +system.cpu.l2cache.overall_hits::total 7214791 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1190388 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1191350 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 775157 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 775157 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1965545 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1966507 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 962 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1965545 # number of overall misses +system.cpu.l2cache.overall_misses::total 1966507 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 70450000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 97815753000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 97886203000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63988346750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 63988346750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 70450000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 161804099750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 161874549750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 70450000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 161804099750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 161874549750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 962 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296723 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297685 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3725127 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3725127 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883613 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883613 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 962 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180336 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181298 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 962 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180336 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181298 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163152 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163263 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411534 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411534 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163140 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163250 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411527 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411527 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214114 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214196 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214104 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214186 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214114 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214196 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77543.568465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83921.683992 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 83916.523423 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84086.378009 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84086.378009 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77543.568465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83986.631613 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83983.473296 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77543.568465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83986.631613 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83983.473296 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214104 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214186 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73232.848233 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82171.319771 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82164.102069 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82548.885903 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82548.885903 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73232.848233 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82320.221491 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82315.776018 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73232.848233 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82320.221491 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82315.776018 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -807,188 +832,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019781 # number of writebacks -system.cpu.l2cache.writebacks::total 1019781 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 964 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190475 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191439 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775151 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775151 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 964 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965626 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966590 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 964 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965626 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966590 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62625000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84983280750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85045905750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55444498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55444498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62625000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140427779250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 140490404250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62625000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140427779250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 140490404250 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019732 # number of writebacks +system.cpu.l2cache.writebacks::total 1019732 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775157 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775157 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965545 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966507 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965545 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966507 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58345500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 82892612500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82950958000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54245247750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54245247750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58345500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137137860250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 137196205750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58345500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137137860250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 137196205750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163263 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411534 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411534 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163250 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411527 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411527 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214114 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214196 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214186 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214196 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64963.692946 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71386.027216 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71380.830869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71527.352090 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71527.352090 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64963.692946 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71441.759139 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71438.583665 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64963.692946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71441.759139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71438.583665 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214186 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60650.207900 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69634.953057 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69627.697990 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69979.691533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69979.691533 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60650.207900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69770.908450 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69766.446674 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60650.207900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69770.908450 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69766.446674 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9176183 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.522150 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694277633 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9180279 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 75.627073 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5178034250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.522150 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9176240 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.503872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694248122 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180336 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.623389 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5175532250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.503872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997926 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997926 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 705 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2966 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 694 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2982 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 416 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1430905565 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1430905565 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 538740047 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538740047 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155537583 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155537583 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694277630 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694277630 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694277630 # number of overall hits -system.cpu.dcache.overall_hits::total 694277630 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11394090 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11394090 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5190919 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5190919 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1430846728 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1430846728 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 538710092 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538710092 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155538028 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155538028 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694248120 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694248120 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694248120 # number of overall hits +system.cpu.dcache.overall_hits::total 694248120 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11394599 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11394599 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5190474 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5190474 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16585009 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16585009 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16585009 # number of overall misses -system.cpu.dcache.overall_misses::total 16585009 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 335805939499 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 335805939499 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289123962439 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289123962439 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 201500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 201500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 624929901938 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 624929901938 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 624929901938 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 624929901938 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550134137 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550134137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16585073 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16585073 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16585073 # number of overall misses +system.cpu.dcache.overall_misses::total 16585073 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 331603001250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 331603001250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 288972510585 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 288972510585 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 129500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 620575511835 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 620575511835 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 620575511835 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 620575511835 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550104691 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550104691 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710862639 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710862639 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710862639 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710862639 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020711 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020711 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032296 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032296 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023331 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023331 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29471.940234 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 29471.940234 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55698.030048 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55698.030048 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 201500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 201500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37680.407767 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37680.407767 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37680.407767 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37680.407767 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11880802 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8587513 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 745209 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710833193 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710833193 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710833193 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710833193 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020714 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020714 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032293 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032293 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023332 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023332 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023332 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023332 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29101.770168 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 29101.770168 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55673.626452 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55673.626452 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 129500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 129500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37417.713617 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37417.713617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37417.713617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37417.713617 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11561530 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8659652 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 743678 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.942913 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 131.841759 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.546419 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132.949290 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3724768 # number of writebacks -system.cpu.dcache.writebacks::total 3724768 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4097367 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4097367 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307364 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3307364 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7404731 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7404731 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7404731 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7404731 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296723 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296723 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725127 # number of writebacks +system.cpu.dcache.writebacks::total 3725127 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4097867 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4097867 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3306871 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3306871 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7404738 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7404738 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7404738 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7404738 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296732 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296732 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883603 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883603 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180278 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180278 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180278 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180278 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 169103281751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 169103281751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78582140948 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 78582140948 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 247685422699 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 247685422699 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 247685422699 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 247685422699 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180335 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180335 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180335 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180335 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 167014367250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 167014367250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77391574454 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77391574454 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 127500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 127500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244405941704 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 244405941704 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244405941704 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 244405941704 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012914 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012914 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23175.236576 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23175.236576 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41720.120171 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41720.120171 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 199500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 199500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26980.165818 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26980.165818 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26980.165818 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26980.165818 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22888.927159 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22888.927159 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41086.988317 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41086.988317 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 127500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 127500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26622.769398 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26622.769398 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26622.769398 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26622.769398 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index b81e9af80..f3e627477 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1966439 # Simulator instruction rate (inst/s) -host_op_rate 1966439 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 986784511 # Simulator tick rate (ticks/s) -host_mem_usage 271364 # Number of bytes of host memory used -host_seconds 925.42 # Real time elapsed on the host +host_inst_rate 2693565 # Simulator instruction rate (inst/s) +host_op_rate 2693565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1351665756 # Simulator tick rate (ticks/s) +host_mem_usage 256712 # Number of bytes of host memory used +host_seconds 675.60 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 1826378527 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched +system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction +system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction +system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction +system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1826378509 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index c20c38ead..2ba96be4b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu sim_ticks 2623386226000 # Number of ticks simulated final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1078959 # Simulator instruction rate (inst/s) -host_op_rate 1078959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1555422646 # Simulator tick rate (ticks/s) -host_mem_usage 280076 # Number of bytes of host memory used -host_seconds 1686.61 # Real time elapsed on the host +host_inst_rate 1099630 # Simulator instruction rate (inst/s) +host_op_rate 1099630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1585220760 # Simulator tick rate (ticks/s) +host_mem_usage 265440 # Number of bytes of host memory used +host_seconds 1654.90 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -109,6 +109,41 @@ system.cpu.num_busy_cycles 5246772452 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched +system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction +system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction +system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction +system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1826378509 # Class of executed instruction system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. |