diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/60.bzip2/ref/arm/linux/o3-timing | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/o3-timing')
3 files changed, 296 insertions, 205 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 5b9d120fe..51e908aa2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 90c937ca7..4a2c04206 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:20 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:28:08 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 8595a64e2..1d3623ac5 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.483300 # Nu sim_ticks 483300356500 # Number of ticks simulated final_tick 483300356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96252 # Simulator instruction rate (inst/s) -host_tick_rate 26997552 # Simulator tick rate (ticks/s) -host_mem_usage 256412 # Number of bytes of host memory used -host_seconds 17901.64 # Real time elapsed on the host -sim_insts 1723073849 # Number of instructions simulated +host_inst_rate 175200 # Simulator instruction rate (inst/s) +host_op_rate 195449 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54820940 # Simulator tick rate (ticks/s) +host_mem_usage 223460 # Number of bytes of host memory used +host_seconds 8815.98 # Real time elapsed on the host +sim_insts 1544563036 # Number of instructions simulated +sim_ops 1723073849 # Number of ops (including micro ops) simulated system.physmem.bytes_read 188191232 # Number of bytes read from this memory system.physmem.bytes_inst_read 45952 # Number of instructions bytes read from this memory system.physmem.bytes_written 77928320 # Number of bytes written to this memory @@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 2.025916 # insts written-back per cycle system.cpu.iew.wb_fanout 0.632400 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 1544563054 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1723073867 # The number of committed instructions system.cpu.commit.commitSquashedInsts 464107908 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 18315306 # The number of times a branch was mispredicted @@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 888130278 # Number of insts commited each cycle -system.cpu.commit.count 1723073867 # Number of instructions committed +system.cpu.commit.committedInsts 1544563054 # Number of instructions committed +system.cpu.commit.committedOps 1723073867 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 660773817 # Number of memory references committed system.cpu.commit.loads 485926771 # Number of loads committed @@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 2976436889 # Th system.cpu.rob.rob_writes 4442782654 # The number of ROB writes system.cpu.timesIdled 920078 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 10281556 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1723073849 # Number of Instructions Simulated -system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated -system.cpu.cpi 0.560975 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.560975 # CPI: Total CPI of All Threads -system.cpu.ipc 1.782612 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.782612 # IPC: Total IPC of All Threads +system.cpu.committedInsts 1544563036 # Number of Instructions Simulated +system.cpu.committedOps 1723073849 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563036 # Number of Instructions Simulated +system.cpu.cpi 0.625809 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625809 # CPI: Total CPI of All Threads +system.cpu.ipc 1.597933 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.597933 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 9941434858 # number of integer regfile reads system.cpu.int_regfile_writes 1939754373 # number of integer regfile writes system.cpu.fp_regfile_reads 96 # number of floating regfile reads @@ -336,26 +341,39 @@ system.cpu.icache.total_refs 285077321 # To system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 382141.180965 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 609.966952 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.297835 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 285077321 # number of ReadReq hits -system.cpu.icache.demand_hits 285077321 # number of demand (read+write) hits -system.cpu.icache.overall_hits 285077321 # number of overall hits -system.cpu.icache.ReadReq_misses 1018 # number of ReadReq misses -system.cpu.icache.demand_misses 1018 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1018 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 35270500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 35270500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 35270500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 285078339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 285078339 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 285078339 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34646.856582 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34646.856582 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34646.856582 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 609.966952 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.297835 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.297835 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 285077321 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 285077321 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 285077321 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 285077321 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 285077321 # number of overall hits +system.cpu.icache.overall_hits::total 285077321 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1018 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1018 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1018 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1018 # number of overall misses +system.cpu.icache.overall_misses::total 1018 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35270500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35270500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35270500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35270500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35270500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35270500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 285078339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 285078339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 285078339 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 285078339 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 285078339 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 285078339 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34646.856582 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34646.856582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34646.856582 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,27 +382,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 272 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 272 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 272 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 746 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 746 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 746 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 25653000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 25653000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 25653000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34387.399464 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34387.399464 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34387.399464 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 272 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 272 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 272 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 272 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 272 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 272 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 746 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 746 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 746 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25653000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25653000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25653000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25653000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25653000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25653000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34387.399464 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34387.399464 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34387.399464 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9570609 # number of replacements system.cpu.dcache.tagsinuse 4087.729265 # Cycle average of tags in use @@ -392,40 +413,63 @@ system.cpu.dcache.total_refs 666885051 # To system.cpu.dcache.sampled_refs 9574705 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 69.650715 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 3484295000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.729265 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997981 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 499489564 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 167395365 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 666884929 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 666884929 # number of overall hits -system.cpu.dcache.ReadReq_misses 10445560 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 5190682 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 15636242 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 15636242 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 184478558500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 128511717246 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 312990275746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 312990275746 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 509935124 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 682521171 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 682521171 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.020484 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.030076 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.022910 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.022910 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 17660.954367 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 24758.156490 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 20016.975674 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 20016.975674 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4087.729265 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997981 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997981 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 499489564 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 499489564 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167395365 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167395365 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 62 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 62 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 666884929 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 666884929 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 666884929 # number of overall hits +system.cpu.dcache.overall_hits::total 666884929 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10445560 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10445560 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5190682 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5190682 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 15636242 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15636242 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15636242 # number of overall misses +system.cpu.dcache.overall_misses::total 15636242 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 184478558500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 184478558500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128511717246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128511717246 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 312990275746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 312990275746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 312990275746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 312990275746 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 509935124 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 509935124 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 682521171 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 682521171 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 682521171 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 682521171 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030076 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047619 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022910 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022910 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17660.954367 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24758.156490 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20016.975674 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20016.975674 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 266779202 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 225500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 90534 # number of cycles access was blocked @@ -434,33 +478,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.729428 system.cpu.dcache.avg_blocked_cycles::no_targets 16107.142857 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3128454 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2763491 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3298046 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6061537 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6061537 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7682069 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1892636 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9574705 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9574705 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 92052400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 45263240996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 137315641496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 137315641496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.015065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.014028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.014028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11982.761480 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23915.449667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 14341.501017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 14341.501017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 3128454 # number of writebacks +system.cpu.dcache.writebacks::total 3128454 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2763491 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2763491 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3298046 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3298046 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6061537 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6061537 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6061537 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6061537 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7682069 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7682069 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1892636 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1892636 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9574705 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9574705 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9574705 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9574705 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 92052400500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 92052400500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45263240996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 45263240996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137315641496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137315641496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137315641496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 137315641496 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015065 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010966 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014028 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014028 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11982.761480 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23915.449667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14341.501017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14341.501017 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2928111 # number of replacements system.cpu.l2cache.tagsinuse 26779.513847 # Cycle average of tags in use @@ -468,36 +521,75 @@ system.cpu.l2cache.total_refs 7850665 # To system.cpu.l2cache.sampled_refs 2955434 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.656349 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 102043879500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15980.141778 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10799.372069 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.487675 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.329571 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5654844 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3128454 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 980108 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6634952 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6634952 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2027970 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 912529 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2940499 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2940499 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 69622687500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 31651212500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 101273900000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 101273900000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7682814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3128454 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1892637 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9575451 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9575451 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.263962 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.482147 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.307087 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.307087 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34331.221616 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.157951 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34441.059154 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34441.059154 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 10799.372069 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 11.094827 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15969.046951 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.329571 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000339 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.487337 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.817246 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5654817 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5654844 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3128454 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3128454 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 980108 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 980108 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 6634925 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6634952 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 27 # 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number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24699000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 69597988500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 69622687500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31651212500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 31651212500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24699000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101249201000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101273900000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24699000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101249201000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101273900000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 746 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7682068 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7682814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3128454 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3128454 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1892637 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1892637 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 746 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9574705 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9575451 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 746 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9574705 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9575451 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963807 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.263894 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.482147 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963807 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.307036 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963807 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.307036 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34351.877608 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34331.214290 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34685.157951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 56425000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 6634 # number of cycles access was blocked @@ -506,31 +598,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8505.426590 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1217630 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2027959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 912529 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2940488 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2940488 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 63243262500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 28812389000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 92055651500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 92055651500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263960 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482147 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.307086 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.307086 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.671160 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31574.217367 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31306.249677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31306.249677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 1217630 # number of writebacks +system.cpu.l2cache.writebacks::total 1217630 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 718 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2027241 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2027959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 912529 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 912529 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 718 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2939770 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2940488 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 718 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2939770 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2940488 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22382500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63220880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63243262500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28812389000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28812389000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22382500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92033269000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 92055651500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22382500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92033269000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 92055651500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.263893 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.482147 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307035 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31173.398329 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31185.675507 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31574.217367 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31173.398329 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31173.398329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |