all: Update stats for memory per master and total fix.

3 files changed, 79 insertions, 22 deletions

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 11fd3546f..48015577c 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -525,9 +524,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index 35c5c026a..2f52f2c05 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:46:03
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 18:36:31
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 54d82ede5..7863d76cc 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -4,23 +4,36 @@ sim_seconds                                  0.463994                       # Nu
 sim_ticks                                463993693500                       # Number of ticks simulated
 final_tick                               463993693500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 113228                       # Simulator instruction rate (inst/s)
-host_op_rate                                   126315                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               34014323                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231672                       # Number of bytes of host memory used
-host_seconds                                 13641.13                       # Real time elapsed on the host
+host_inst_rate                                 128371                       # Simulator instruction rate (inst/s)
+host_op_rate                                   143208                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               38563333                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232076                       # Number of bytes of host memory used
+host_seconds                                 12031.99                       # Real time elapsed on the host
 sim_insts                                  1544563066                       # Number of instructions simulated
 sim_ops                                    1723073879                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                   189795648                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  49344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 78222144                       # Number of bytes written to this memory
-system.physmem.num_reads                      2965557                       # Number of read requests responded to by this memory
-system.physmem.num_writes                     1222221                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      409047904                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    106346                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                     168584498                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     577632403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             49344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         189746304                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            189795648                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        49344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           49344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     78222144                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          78222144                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                771                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2964786                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2965557                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1222221                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1222221                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               106346                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            408941558                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               409047904                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          106346                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             106346                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         168584498                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              168584498                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         168584498                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              106346                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           408941558                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              577632403                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -369,11 +382,17 @@ system.cpu.icache.demand_accesses::total    283730265                       # nu
 system.cpu.icache.overall_accesses::cpu.inst    283730265                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    283730265                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 33283.208020                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 33283.208020                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 33283.208020                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -401,11 +420,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     27579500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27579500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     27579500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000003                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34431.335830                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 34431.335830                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 34431.335830                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9619302                       # number of replacements
 system.cpu.dcache.tagsinuse               4087.756066                       # Cycle average of tags in use
@@ -461,15 +486,25 @@ system.cpu.dcache.demand_accesses::total    676628084                       # nu
 system.cpu.dcache.overall_accesses::cpu.data    676628084                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total    676628084                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021216                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.021216                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.030175                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.030175                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.030928                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.030928                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.023501                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023501                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.023501                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.023501                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17679.887499                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 24831.987697                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333                       # average LoadLockedReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20022.197405                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20022.197405                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs    271440605                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       164500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs             91957                       # number of cycles access was blocked
@@ -507,13 +542,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 138431091460
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total 138431091460                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015335                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015335                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010974                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010974                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014223                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.014223                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014223                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.014223                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.817537                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23955.185749                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14384.845297                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14384.845297                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2953110                       # number of replacements
 system.cpu.l2cache.tagsinuse             26875.343151                       # Cycle average of tags in use
@@ -578,18 +621,26 @@ system.cpu.l2cache.overall_accesses::cpu.data      9623398
 system.cpu.l2cache.overall_accesses::total      9624199                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.963795                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.265109                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.265181                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.483459                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.483459                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.963795                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.308082                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.308136                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.963795                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.308082                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.308136                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.865285                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.448450                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34328.459152                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34690.748311                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34690.748311                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.865285                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.341386                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34440.319656                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.865285                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.341386                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34440.319656                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs     57329500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs             6735                       # number of cycles access was blocked
@@ -633,18 +684,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  92824744500
 system.cpu.l2cache.overall_mshr_miss_latency::total  92848795000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.962547                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.265108                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.265180                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.483459                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.483459                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.962547                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.308081                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.308135                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.962547                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.308081                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.308135                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31187.063761                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.171225                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31309.057624                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31309.057624                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------