diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/se/60.bzip2/ref/arm/linux/o3-timing | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/o3-timing')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini | 77 | ||||
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 1521 |
2 files changed, 834 insertions, 764 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 30ce01df4..d4b45072d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 7989e6703..19d70b574 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.533691 # Number of seconds simulated -sim_ticks 533690503000 # Number of ticks simulated -final_tick 533690503000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.533797 # Number of seconds simulated +sim_ticks 533797009000 # Number of ticks simulated +final_tick 533797009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128085 # Simulator instruction rate (inst/s) -host_op_rate 142888 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44256929 # Simulator tick rate (ticks/s) -host_mem_usage 275676 # Number of bytes of host memory used -host_seconds 12058.91 # Real time elapsed on the host +host_inst_rate 102910 # Simulator instruction rate (inst/s) +host_op_rate 114803 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35565366 # Simulator tick rate (ticks/s) +host_mem_usage 295220 # Number of bytes of host memory used +host_seconds 15008.90 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143713600 # Number of bytes read from this memory -system.physmem.bytes_read::total 143761344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70434112 # Number of bytes written to this memory -system.physmem.bytes_written::total 70434112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245525 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246271 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100533 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 269282663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 269372123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 131975577 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 131975577 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 131975577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 269282663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401347700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246271 # Number of read requests accepted -system.physmem.writeReqs 1100533 # Number of write requests accepted -system.physmem.readBursts 2246271 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100533 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143722048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 39296 # Total number of bytes read from write queue -system.physmem.bytesWritten 70432960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143761344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70434112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 614 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 47680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143743296 # Number of bytes read from this memory +system.physmem.bytes_read::total 143790976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70431872 # Number of bytes written to this memory +system.physmem.bytes_written::total 70431872 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246734 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100498 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100498 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 269284566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 269373889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 131945048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 131945048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 131945048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 269284566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401318937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246734 # Number of read requests accepted +system.physmem.writeReqs 1100498 # Number of write requests accepted +system.physmem.readBursts 2246734 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100498 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143754112 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 36864 # Total number of bytes read from write queue +system.physmem.bytesWritten 70430784 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143790976 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70431872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139609 # Per bank write bursts -system.physmem.perBankRdBursts::1 136206 # Per bank write bursts -system.physmem.perBankRdBursts::2 133832 # Per bank write bursts -system.physmem.perBankRdBursts::3 136344 # Per bank write bursts -system.physmem.perBankRdBursts::4 135019 # Per bank write bursts -system.physmem.perBankRdBursts::5 135288 # Per bank write bursts -system.physmem.perBankRdBursts::6 136231 # Per bank write bursts -system.physmem.perBankRdBursts::7 136121 # Per bank write bursts -system.physmem.perBankRdBursts::8 143692 # Per bank write bursts -system.physmem.perBankRdBursts::9 146373 # Per bank write bursts -system.physmem.perBankRdBursts::10 144432 # Per bank write bursts -system.physmem.perBankRdBursts::11 146294 # Per bank write bursts -system.physmem.perBankRdBursts::12 145666 # Per bank write bursts -system.physmem.perBankRdBursts::13 146070 # Per bank write bursts -system.physmem.perBankRdBursts::14 142065 # Per bank write bursts -system.physmem.perBankRdBursts::15 142415 # Per bank write bursts -system.physmem.perBankWrBursts::0 69121 # Per bank write bursts -system.physmem.perBankWrBursts::1 67439 # Per bank write bursts -system.physmem.perBankWrBursts::2 65729 # Per bank write bursts -system.physmem.perBankWrBursts::3 66294 # Per bank write bursts -system.physmem.perBankWrBursts::4 66241 # Per bank write bursts -system.physmem.perBankWrBursts::5 66403 # Per bank write bursts -system.physmem.perBankWrBursts::6 67965 # Per bank write bursts -system.physmem.perBankWrBursts::7 68773 # Per bank write bursts -system.physmem.perBankWrBursts::8 70328 # Per bank write bursts -system.physmem.perBankWrBursts::9 70962 # Per bank write bursts -system.physmem.perBankWrBursts::10 70540 # Per bank write bursts -system.physmem.perBankWrBursts::11 70927 # Per bank write bursts -system.physmem.perBankWrBursts::12 70302 # Per bank write bursts -system.physmem.perBankWrBursts::13 70806 # Per bank write bursts -system.physmem.perBankWrBursts::14 69598 # Per bank write bursts -system.physmem.perBankWrBursts::15 69087 # Per bank write bursts +system.physmem.perBankRdBursts::0 139750 # Per bank write bursts +system.physmem.perBankRdBursts::1 136273 # Per bank write bursts +system.physmem.perBankRdBursts::2 133708 # Per bank write bursts +system.physmem.perBankRdBursts::3 136246 # Per bank write bursts +system.physmem.perBankRdBursts::4 134906 # Per bank write bursts +system.physmem.perBankRdBursts::5 135253 # Per bank write bursts +system.physmem.perBankRdBursts::6 136175 # Per bank write bursts +system.physmem.perBankRdBursts::7 136295 # Per bank write bursts +system.physmem.perBankRdBursts::8 143732 # Per bank write bursts +system.physmem.perBankRdBursts::9 146555 # Per bank write bursts +system.physmem.perBankRdBursts::10 144302 # Per bank write bursts +system.physmem.perBankRdBursts::11 146237 # Per bank write bursts +system.physmem.perBankRdBursts::12 145788 # Per bank write bursts +system.physmem.perBankRdBursts::13 146277 # Per bank write bursts +system.physmem.perBankRdBursts::14 142119 # Per bank write bursts +system.physmem.perBankRdBursts::15 142542 # Per bank write bursts +system.physmem.perBankWrBursts::0 69128 # Per bank write bursts +system.physmem.perBankWrBursts::1 67452 # Per bank write bursts +system.physmem.perBankWrBursts::2 65650 # Per bank write bursts +system.physmem.perBankWrBursts::3 66298 # Per bank write bursts +system.physmem.perBankWrBursts::4 66182 # Per bank write bursts +system.physmem.perBankWrBursts::5 66379 # Per bank write bursts +system.physmem.perBankWrBursts::6 67939 # Per bank write bursts +system.physmem.perBankWrBursts::7 68869 # Per bank write bursts +system.physmem.perBankWrBursts::8 70353 # Per bank write bursts +system.physmem.perBankWrBursts::9 70986 # Per bank write bursts +system.physmem.perBankWrBursts::10 70505 # Per bank write bursts +system.physmem.perBankWrBursts::11 70955 # Per bank write bursts +system.physmem.perBankWrBursts::12 70250 # Per bank write bursts +system.physmem.perBankWrBursts::13 70819 # Per bank write bursts +system.physmem.perBankWrBursts::14 69624 # Per bank write bursts +system.physmem.perBankWrBursts::15 69092 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 533690432500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 533796944500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2246271 # Read request sizes (log2) +system.physmem.readPktSize::6 2246734 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100533 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1620463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 446151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 135620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100498 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1621551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 445207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 135727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -127,217 +127,215 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 49049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 49091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 49066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 49073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 49089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 49084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 49051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 49094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 49119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 49182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 49203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 49260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 49964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 50324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 51901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 52174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 48879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 49064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 49063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 49078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 49086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 49106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 49070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 49088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 49113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 49112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 49119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 49167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 49186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 49268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 49533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 49888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 50325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 52053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 51988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 52147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2077885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.053834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.951836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 184.653120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1660855 79.93% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 226890 10.92% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 69105 3.33% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 37676 1.81% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 25011 1.20% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12112 0.58% 97.77% # Bytes accessed per row activation +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 2077673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.074669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.977753 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 184.400722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1659880 79.89% 79.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 227444 10.95% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 69322 3.34% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 37684 1.81% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 24960 1.20% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 12074 0.58% 97.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8103 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4494 0.22% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3425 0.16% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2747 0.13% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2032 0.10% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1669 0.08% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1441 0.07% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1240 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1051 0.05% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 987 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 902 0.04% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 711 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 8168 0.39% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4452 0.21% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3374 0.16% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2842 0.14% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2038 0.10% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1716 0.08% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1451 0.07% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1190 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1071 0.05% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 949 0.05% 99.48% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::1792-1793 473 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 132 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 131 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 122 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 122 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 103 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 129 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 90 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 83 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 94 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 68 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 57 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 64 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 70 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 60 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 55 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 48 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 43 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 58 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 55 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 43 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 33 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 30 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 32 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 24 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 19 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 34 0.00% 99.95% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 21 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 20 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 676 0.03% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3081 0.15% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 420 0.02% 99.79% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::4096-4097 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 9 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 25 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 18 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 18 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 19 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 22 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 34 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 16 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 16 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 27 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 36 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 16 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 187 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 12 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 23 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 20 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 17 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 15 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 185 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 13 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 17 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 9 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 12 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 9 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 34 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 16 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 38 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 8 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 26 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 4 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 4 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 13 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 83 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2077885 # Bytes accessed per row activation -system.physmem.totQLat 32824703500 # Total ticks spent queuing -system.physmem.totMemAccLat 104040704750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11228285000 # Total ticks spent in databus transfers -system.physmem.totBankLat 59987716250 # Total ticks spent accessing banks -system.physmem.avgQLat 14616.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26712.77 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::8192-8193 82 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2077673 # Bytes accessed per row activation +system.physmem.totQLat 32821468000 # Total ticks spent queuing +system.physmem.totMemAccLat 104059554250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11230790000 # Total ticks spent in databus transfers +system.physmem.totBankLat 60007296250 # Total ticks spent accessing banks +system.physmem.avgQLat 14612.27 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26715.53 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46329.74 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 46327.80 # Average memory access latency per DRAM burst system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 131.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 131.94 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 131.98 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 131.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.08 # Average write queue length when enqueuing -system.physmem.readRowHits 931610 # Number of row buffer hits during reads -system.physmem.writeRowHits 336677 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes -system.physmem.avgGap 159462.71 # Average gap between requests -system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.89 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 401347580 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1419678 # Transaction distribution -system.membus.trans_dist::ReadResp 1419677 # Transaction distribution -system.membus.trans_dist::Writeback 1100533 # Transaction distribution -system.membus.trans_dist::ReadExReq 826593 # Transaction distribution -system.membus.trans_dist::ReadExResp 826593 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593074 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214195392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214195392 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214195392 # Total data (bytes) +system.physmem.avgWrQLen 10.35 # Average write queue length when enqueuing +system.physmem.readRowHits 932509 # Number of row buffer hits during reads +system.physmem.writeRowHits 336457 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.57 # Row buffer hit rate for writes +system.physmem.avgGap 159474.14 # Average gap between requests +system.physmem.pageHitRate 37.92 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.98 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 401318817 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420235 # Transaction distribution +system.membus.trans_dist::ReadResp 1420234 # Transaction distribution +system.membus.trans_dist::Writeback 1100498 # Transaction distribution +system.membus.trans_dist::ReadExReq 826499 # Transaction distribution +system.membus.trans_dist::ReadExResp 826499 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593965 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5593965 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214222784 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214222784 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214222784 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12924294750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12926153000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21079818750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.9 # Layer utilization (%) -system.cpu.branchPred.lookups 303467870 # Number of BP lookups -system.cpu.branchPred.condPredicted 249715061 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15195903 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 175178105 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161776963 # Number of BTB hits +system.membus.respLayer1.occupancy 21085487000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.0 # Layer utilization (%) +system.cpu.branchPred.lookups 303451211 # Number of BP lookups +system.cpu.branchPred.condPredicted 249690817 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15200865 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 174297258 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161770128 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.349990 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17540871 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 204 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.812779 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17550277 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -381,133 +379,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1067381007 # number of cpu cycles simulated +system.cpu.numCycles 1067594019 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 299148062 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2189533318 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303467870 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179317834 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435752088 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88086251 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 164106751 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 339 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 289566494 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5997594 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 968963067 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.499628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.206367 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 299164557 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2189663567 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303451211 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179320405 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435777521 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88106670 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 164181608 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 55 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 289571528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5986152 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 969098859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.499353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.206220 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 533211067 55.03% 55.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25485631 2.63% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39032754 4.03% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48282665 4.98% 66.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43767932 4.52% 71.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46382840 4.79% 75.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38389210 3.96% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18960850 1.96% 81.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175450118 18.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 533321418 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25465587 2.63% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39057125 4.03% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48306210 4.98% 66.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43759030 4.52% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46389880 4.79% 75.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38408230 3.96% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18944401 1.95% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175446978 18.10% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 968963067 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.284311 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.051314 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 331377153 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 141962670 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405350137 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20317948 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69955159 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46017147 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2369104960 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2426 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69955159 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354884990 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 70530339 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17935 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400511119 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73063525 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2306250708 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 150920 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5011927 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60136403 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282159345 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10649371145 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9763416611 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 460 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 969098859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.284238 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.051026 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 331405346 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 142029656 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405372937 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20316462 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69974458 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46022119 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2369134638 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2461 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69974458 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354905741 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 70599540 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20110 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400539970 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73059040 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2306329085 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 151792 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5017639 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60125136 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282204226 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10649650977 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9763673843 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 575839415 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 404 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160989021 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624749088 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220784728 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85932352 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70842412 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2202316968 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 440 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018777354 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4015619 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 474672323 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1127531541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 270 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 968963067 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.083441 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906294 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 575884296 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 843 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 840 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160951749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624757210 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220789926 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85935761 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70812981 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2202388527 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 863 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018815703 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4014611 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 474721541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1127548434 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 693 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 969098859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.083189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 286087063 29.53% 29.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153648666 15.86% 45.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160841319 16.60% 61.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120316001 12.42% 74.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123517924 12.75% 87.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73816539 7.62% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38325528 3.96% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9889728 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2520299 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 286260209 29.54% 29.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153575867 15.85% 45.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160890539 16.60% 61.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120276383 12.41% 74.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123547545 12.75% 87.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73803065 7.62% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38319485 3.95% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9898934 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2526832 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 968963067 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 969098859 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 895423 3.74% 3.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5601 0.02% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18274862 76.27% 80.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4786167 19.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 899836 3.76% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5555 0.02% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18259038 76.22% 80.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4790984 20.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236899038 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 924736 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236944304 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 924745 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -529,90 +526,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 48 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 39 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587872837 29.12% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193080663 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587884247 29.12% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193062337 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018777354 # Type of FU issued -system.cpu.iq.rate 1.891337 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23962053 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011870 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5034495136 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2677178912 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957310102 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 311 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 694 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 129 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042739250 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 157 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64569425 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018815703 # Type of FU issued +system.cpu.iq.rate 1.890996 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23955413 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011866 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5034700006 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2677299944 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957368325 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 522 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042770975 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64606441 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138822319 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 268987 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192391 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45937683 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138830441 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271664 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192064 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45942881 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4778132 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4771033 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69955159 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33483642 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1603224 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2202317539 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7879544 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624749088 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220784728 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 378 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 478707 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 97428 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192391 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8138332 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9600465 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17738797 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988042975 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574015030 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30734379 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69974458 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33522833 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1603829 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2202389482 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7882723 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624757210 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220789926 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 801 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 479284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97151 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192064 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8143428 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9602990 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17746418 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988074209 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574028107 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30741494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 131 # number of nop insts executed -system.cpu.iew.exec_refs 764217607 # number of memory reference insts executed -system.cpu.iew.exec_branches 238311346 # Number of branches executed -system.cpu.iew.exec_stores 190202577 # Number of stores executed -system.cpu.iew.exec_rate 1.862543 # Inst execution rate -system.cpu.iew.wb_sent 1965731650 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957310231 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295404026 # num instructions producing a value -system.cpu.iew.wb_consumers 2059270839 # num instructions consuming a value +system.cpu.iew.exec_nop 92 # number of nop insts executed +system.cpu.iew.exec_refs 764206037 # number of memory reference insts executed +system.cpu.iew.exec_branches 238324356 # Number of branches executed +system.cpu.iew.exec_stores 190177930 # Number of stores executed +system.cpu.iew.exec_rate 1.862201 # Inst execution rate +system.cpu.iew.wb_sent 1965784253 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957368435 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295422958 # num instructions producing a value +system.cpu.iew.wb_consumers 2059236430 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.833750 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629060 # average fanout of values written-back +system.cpu.iew.wb_rate 1.833439 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629079 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 479343339 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 479415060 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15195240 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 899007908 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.916639 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.718451 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15200205 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 899124401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.916391 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718302 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 410513863 45.66% 45.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193235979 21.49% 67.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72768373 8.09% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35278706 3.92% 79.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18862057 2.10% 81.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30820454 3.43% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19957331 2.22% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11398634 1.27% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106172511 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 410581675 45.66% 45.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193287424 21.50% 67.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72783200 8.09% 75.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35268105 3.92% 79.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18874620 2.10% 81.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30803459 3.43% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19949403 2.22% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11408599 1.27% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106167916 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 899007908 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 899124401 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -623,90 +620,90 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106172511 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106167916 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2995251990 # The number of ROB reads -system.cpu.rob.rob_writes 4474939624 # The number of ROB writes -system.cpu.timesIdled 1152982 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98417940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2995444799 # The number of ROB reads +system.cpu.rob.rob_writes 4475102834 # The number of ROB writes +system.cpu.timesIdled 1153332 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98495160 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.691057 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.691057 # CPI: Total CPI of All Threads -system.cpu.ipc 1.447059 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.447059 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956212388 # number of integer regfile reads -system.cpu.int_regfile_writes 1937181821 # number of integer regfile writes -system.cpu.fp_regfile_reads 130 # number of floating regfile reads -system.cpu.fp_regfile_writes 139 # number of floating regfile writes -system.cpu.misc_regfile_reads 737624314 # number of misc regfile reads +system.cpu.cpi 0.691195 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.691195 # CPI: Total CPI of All Threads +system.cpu.ipc 1.446770 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.446770 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956366000 # number of integer regfile reads +system.cpu.int_regfile_writes 1937254103 # number of integer regfile writes +system.cpu.fp_regfile_reads 112 # number of floating regfile reads +system.cpu.fp_regfile_writes 111 # number of floating regfile writes +system.cpu.misc_regfile_reads 737634139 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1605146644 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7709082 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7709081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3782685 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893414 # Transaction distribution +system.cpu.toL2Bus.throughput 1604602532 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709031 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3780837 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893445 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22987676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22984242 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22985790 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856601984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856651520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856651520 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856482496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856532032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856532032 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10475431595 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10472653342 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1294249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1293249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14768966243 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14769367993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 22 # number of replacements -system.cpu.icache.tags.tagsinuse 628.527972 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289565308 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 20 # number of replacements +system.cpu.icache.tags.tagsinuse 628.438821 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289570320 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 374115.385013 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 374121.860465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 628.527972 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306898 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306898 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 289565308 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289565308 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289565308 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289565308 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289565308 # number of overall hits -system.cpu.icache.overall_hits::total 289565308 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1186 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1186 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1186 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1186 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1186 # number of overall misses -system.cpu.icache.overall_misses::total 1186 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82924749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82924749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82924749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82924749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82924749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82924749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289566494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289566494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289566494 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289566494 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289566494 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289566494 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 628.438821 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306855 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306855 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 289570320 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289570320 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289570320 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289570320 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289570320 # number of overall hits +system.cpu.icache.overall_hits::total 289570320 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1208 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1208 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1208 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1208 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1208 # number of overall misses +system.cpu.icache.overall_misses::total 1208 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 83080499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 83080499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 83080499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 83080499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 83080499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 83080499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289571528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289571528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289571528 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289571528 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289571528 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289571528 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69919.687184 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69919.687184 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69919.687184 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69919.687184 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69919.687184 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69919.687184 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68775.247517 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68775.247517 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68775.247517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68775.247517 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -715,120 +712,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 774 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 774 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57029751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 57029751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57029751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 57029751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57029751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 57029751 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56793251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 56793251 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56793251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56793251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56793251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 56793251 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73681.848837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73681.848837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73681.848837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73681.848837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73681.848837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73681.848837 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73376.293282 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73376.293282 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2213583 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31532.604049 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9247674 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2243357 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.122248 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2214050 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31533.035321 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9245310 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2243823 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.120338 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 21623958250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14306.578053 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.421352 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 17205.604643 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.436602 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000623 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.525073 # Average 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0.965116 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184079 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965116 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233868 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233927 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965116 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.233868 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.233927 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74940.763052 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88491.146378 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 88484.016536 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92445.316498 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92445.316498 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89941.708488 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89941.708488 # average overall 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ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79742.292792 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9597625 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.040332 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 656028832 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9601721 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 68.324088 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9597606 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.041920 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 656019476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9601702 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.323249 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 3547188250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.040332 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041920 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 489072771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489072771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166955934 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166955934 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 66 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 66 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 489062653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489062653 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166956698 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166956698 # number of WriteReq hits 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number of overall misses -system.cpu.dcache.overall_misses::total 17144152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 363445631238 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 363445631238 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307798034677 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307798034677 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 225500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 671243665915 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 671243665915 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 671243665915 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 671243665915 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500586810 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500586810 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17136845 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17136845 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17136845 # number of overall misses +system.cpu.dcache.overall_misses::total 17136845 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 363702842488 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 363702842488 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 307744962906 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 307744962906 # number of WriteReq miss cycles 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-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 69 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 69 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673172857 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673172857 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673172857 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673172857 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023001 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032622 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032622 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043478 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043478 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025468 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025468 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025468 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025468 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31565.433402 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31565.433402 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54669.956833 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54669.956833 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39152.923161 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39152.923161 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24614592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3988980 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1212230 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65133 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.305216 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.243609 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673156196 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673156196 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673156196 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673156196 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032618 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032618 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31605.732688 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31605.732688 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54667.948799 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54667.948799 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39181.529937 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39181.529937 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24597243 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3988018 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1212289 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.289917 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.230720 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3782685 # number of writebacks -system.cpu.dcache.writebacks::total 3782685 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3805731 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3805731 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736699 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3736699 # number of WriteReq MSHR hits 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overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708308 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708308 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893414 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893414 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601722 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601722 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601722 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601722 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198054864257 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 198054864257 # number of ReadReq MSHR miss cycles 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# number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 89346986214 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287560109971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 287560109971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287560109971 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 287560109971 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25693.688454 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25693.688454 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47253.040292 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47253.040292 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014264 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014264 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25714.386280 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25714.386280 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47187.526553 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47187.526553 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |