stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

    commit 2c1286865fc2542a0586ca4ff40b00765d17b348
    Author: Brandon Potter <Brandon.Potter@amd.com>
    Date:   Wed Mar 1 14:52:23 2017 -0600

        syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 32 insertions, 19 deletions

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 65c2bbf99..c5f8c8ed0 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -87,6 +87,7 @@ progress_interval=0
 simpoint_start_insts=
 socket_id=0
 switched_out=false
+syscallRetryLatency=10000
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
@@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
@@ -117,6 +118,7 @@ response_latency=2
 sequential_access=false
 size=262144
 system=system
+tag_latency=2
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -129,15 +131,16 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=262144
+tag_latency=2
 
 [system.cpu.dstage2_mmu]
 type=ArmStage2MMU
@@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3]
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
@@ -214,6 +217,7 @@ response_latency=2
 sequential_access=false
 size=131072
 system=system
+tag_latency=2
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -226,15 +230,16 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=131072
+tag_latency=2
 
 [system.cpu.interrupts]
 type=ArmInterrupts
@@ -253,8 +258,6 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
 id_isar2=555950401
@@ -265,8 +268,6 @@ id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
 id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
 midr=1091551472
 pmu=Null
 system=system
@@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=20
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
@@ -346,6 +347,7 @@ response_latency=20
 sequential_access=false
 size=2097152
 system=system
+tag_latency=20
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 write_buffers=8
@@ -358,15 +360,16 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=20
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=20
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=2097152
+tag_latency=20
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
@@ -402,7 +405,7 @@ type=ExeTracer
 eventq_index=0
 
 [system.cpu.workload]
-type=LiveProcess
+type=Process
 cmd=bzip2 input.source 1
 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
 drivers=
@@ -411,14 +414,15 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
 output=cout
+pgid=100
 pid=100
-ppid=99
+ppid=0
 simpoint=0
 system=system
 uid=100
@@ -442,6 +446,7 @@ transition_latency=100000000
 
 [system.membus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -453,7 +458,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -461,6 +466,13 @@ width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
@@ -469,6 +481,7 @@ conf_table_reported=true
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -476,7 +489,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
 port=system.membus.master[0]
 
 [system.voltage_domain]