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authorAli Saidi <Ali.Saidi@ARM.com>2012-06-29 11:19:03 -0400
committerAli Saidi <Ali.Saidi@ARM.com>2012-06-29 11:19:03 -0400
commit3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch)
tree63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
parentaf2b14a362281f36347728e13dcd6b2c4d3c4991 (diff)
downloadgem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt')
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt372
1 files changed, 186 insertions, 186 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index db0ae235a..c9d66243a 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,39 +1,39 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.431420 # Number of seconds simulated
-sim_ticks 2431419954000 # Number of ticks simulated
-final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.408512 # Number of seconds simulated
+sim_ticks 2408512388000 # Number of ticks simulated
+final_tick 2408512388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1031283 # Simulator instruction rate (inst/s)
-host_op_rate 1150922 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1629547552 # Simulator tick rate (ticks/s)
-host_mem_usage 230584 # Number of bytes of host memory used
-host_seconds 1492.08 # Real time elapsed on the host
-sim_insts 1538759609 # Number of instructions simulated
-sim_ops 1717270343 # Number of ops (including micro ops) simulated
+host_inst_rate 1431405 # Simulator instruction rate (inst/s)
+host_op_rate 1597462 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2240478292 # Simulator tick rate (ticks/s)
+host_mem_usage 233776 # Number of bytes of host memory used
+host_seconds 1075.00 # Real time elapsed on the host
+sim_insts 1538759601 # Number of instructions simulated
+sim_ops 1717270334 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 172726592 # Number of bytes read from this memory
-system.physmem.bytes_read::total 172766016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 137819840 # Number of bytes read from this memory
+system.physmem.bytes_read::total 137859264 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 75006720 # Number of bytes written to this memory
-system.physmem.bytes_written::total 75006720 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 67221184 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67221184 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2698853 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2699469 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1171980 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1171980 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 16214 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 71039391 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 71055605 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 16214 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 16214 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 30848937 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 30848937 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 30848937 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 16214 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 71039391 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 101904542 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 2153435 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 16369 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 57221977 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 57238345 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 16369 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 16369 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 27909835 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 27909835 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 27909835 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 16369 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 57221977 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 85148181 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -77,43 +77,43 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 4862839908 # number of cpu cycles simulated
+system.cpu.numCycles 4817024776 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 1538759609 # Number of instructions committed
-system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
+system.cpu.committedInsts 1538759601 # Number of instructions committed
+system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
-system.cpu.num_func_calls 27330134 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1536941850 # number of integer instructions
+system.cpu.num_func_calls 27330256 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 177498327 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1536941842 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
-system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
+system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_mem_refs 660773816 # number of memory refs
-system.cpu.num_load_insts 485926770 # Number of load instructions
+system.cpu.num_mem_refs 660773815 # number of memory refs
+system.cpu.num_load_insts 485926769 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 4862839908 # Number of busy cycles
+system.cpu.num_busy_cycles 4817024776 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 7 # number of replacements
-system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use
-system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 515.022606 # Cycle average of tags in use
+system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 514.872896 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.251403 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1544564961 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1544564961 # number of overall hits
-system.cpu.icache.overall_hits::total 1544564961 # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst 515.022606 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.251476 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.251476 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits
+system.cpu.icache.overall_hits::total 1544564952 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
@@ -126,12 +126,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 34804000
system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1544565599 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1544565599 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
@@ -178,26 +178,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138
system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9111140 # number of replacements
-system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use
-system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4083.603265 # Cycle average of tags in use
+system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4083.719979 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.997002 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.997002 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 475158040 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 475158040 # number of ReadReq hits
+system.cpu.dcache.warmup_cycle 25922973000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4083.603265 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.996973 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.996973 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 645854938 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 645854938 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 645854938 # number of overall hits
-system.cpu.dcache.overall_hits::total 645854938 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits
+system.cpu.dcache.overall_hits::total 645854937 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
@@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n
system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 177140908000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 63824222000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 63824222000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 240965130000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 240965130000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 240965130000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 240965130000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 482384127 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 482384127 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 158470312000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 158470312000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 59587262000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 59587262000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 218057574000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 218057574000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 218057574000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 218057574000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 654970174 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 654970174 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 654970174 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 654970174 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
@@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917
system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24514.084594 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33784.641656 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26435.424162 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26435.424162 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21930.307786 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21930.307786 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31541.854031 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31541.854031 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23922.317974 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23922.317974 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23922.317974 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks
-system.cpu.dcache.writebacks::total 3061985 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 3385547 # number of writebacks
+system.cpu.dcache.writebacks::total 3385547 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
@@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236
system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155462647000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58156775000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 58156775000 # number of WriteReq MSHR miss cycles
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