diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt | 1356 |
1 files changed, 678 insertions, 678 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 11790cc5e..fd3a8134b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,682 +1,682 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.379922 # Number of seconds simulated -sim_ticks 2379921906500 # Number of ticks simulated -final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1526036 # Simulator instruction rate (inst/s) -host_op_rate 1644518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2360243305 # Simulator tick rate (ticks/s) -host_mem_usage 271808 # Number of bytes of host memory used -host_seconds 1008.34 # Real time elapsed on the host -sim_insts 1538759602 # Number of instructions simulated -sim_ops 1658228915 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory -system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory -system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 4759843813 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1538759602 # Number of instructions committed -system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls -system.cpu.num_int_insts 1477900422 # number of integer instructions -system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 2601860297 # number of times the integer registers were read -system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written -system.cpu.num_fp_register_reads 24 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read -system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written -system.cpu.num_mem_refs 633153380 # number of memory refs -system.cpu.num_load_insts 458306334 # Number of load instructions -system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 213462427 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction -system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction -system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1664032481 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits -system.cpu.dcache.overall_hits::total 618379947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses -system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of 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-system.cpu.icache.demand_miss_latency::cpu.inst 39132000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39132000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39132000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39132000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1544565591 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1544565591 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1544565591 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 7 # number of writebacks -system.cpu.icache.writebacks::total 7 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38494000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38494000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38494000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38494000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38494000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38494000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq 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overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1938113 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31679.342131 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16254769 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1970881 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.247463 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 138952277000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.111234 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.251326 # Average occupied blocks per requestor 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-system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147777841 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147777841 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3667054 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3667054 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095453 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095453 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6049829 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6049829 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7145282 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7145304 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7145282 # number of overall hits -system.cpu.l2cache.overall_hits::total 7145304 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 793696 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 793696 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 616 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 616 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176258 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1176258 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1969954 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1970570 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1969954 # number of overall misses -system.cpu.l2cache.overall_misses::total 1970570 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48018674000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 48018674000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 37281000 # number of ReadCleanReq miss cycles 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-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1031709 # number of writebacks -system.cpu.l2cache.writebacks::total 1031709 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 220 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 220 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793696 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 793696 # number of ReadExReq MSHR misses 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miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31121000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 99527540500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420134 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420134 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1220 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4698763 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6350490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818066560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818107840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1938113 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66029376 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11053987 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000215 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.014666 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2378 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11053987 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3907683 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1937205 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1176874 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1031709 # Transaction distribution -system.membus.trans_dist::CleanEvict 905404 # Transaction distribution -system.membus.trans_dist::ReadExReq 793696 # Transaction distribution -system.membus.trans_dist::ReadExResp 793696 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1176874 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5878253 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192145856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192145856 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 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2379921906500 +final_tick 2379921906500 +sim_freq 1000000000000 +host_inst_rate 663470 +host_op_rate 714982 +host_tick_rate 1026156085 +host_mem_usage 282544 +host_seconds 2319.26 +sim_insts 1538759602 +sim_ops 1658228915 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 +system.physmem.bytes_read::cpu.inst 39424 +system.physmem.bytes_read::cpu.data 126077056 +system.physmem.bytes_read::total 126116480 +system.physmem.bytes_inst_read::cpu.inst 39424 +system.physmem.bytes_inst_read::total 39424 +system.physmem.bytes_written::writebacks 66029376 +system.physmem.bytes_written::total 66029376 +system.physmem.num_reads::cpu.inst 616 +system.physmem.num_reads::cpu.data 1969954 +system.physmem.num_reads::total 1970570 +system.physmem.num_writes::writebacks 1031709 +system.physmem.num_writes::total 1031709 +system.physmem.bw_read::cpu.inst 16565 +system.physmem.bw_read::cpu.data 52975291 +system.physmem.bw_read::total 52991856 +system.physmem.bw_inst_read::cpu.inst 16565 +system.physmem.bw_inst_read::total 16565 +system.physmem.bw_write::writebacks 27744346 +system.physmem.bw_write::total 27744346 +system.physmem.bw_total::writebacks 27744346 +system.physmem.bw_total::cpu.inst 16565 +system.physmem.bw_total::cpu.data 52975291 +system.physmem.bw_total::total 80736202 +system.pwrStateResidencyTicks::UNDEFINED 2379921906500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 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