diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se/60.bzip2/ref/arm/linux/simple-timing | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux/simple-timing')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt | 505 |
1 files changed, 261 insertions, 244 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 144026919..939603453 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.363663 # Number of seconds simulated -sim_ticks 2363662967500 # Number of ticks simulated -final_tick 2363662967500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363367 # Number of seconds simulated +sim_ticks 2363367211500 # Number of ticks simulated +final_tick 2363367211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 734295 # Simulator instruction rate (inst/s) -host_op_rate 791306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1127938114 # Simulator tick rate (ticks/s) -host_mem_usage 305424 # Number of bytes of host memory used -host_seconds 2095.56 # Real time elapsed on the host +host_inst_rate 1091670 # Simulator instruction rate (inst/s) +host_op_rate 1176427 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1676685643 # Simulator tick rate (ticks/s) +host_mem_usage 312924 # Number of bytes of host memory used +host_seconds 1409.55 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory -system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124870144 # Number of bytes read from this memory +system.physmem.bytes_read::total 124909568 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory -system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory +system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53020297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53036976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27542282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27542282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27542282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53020297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80579258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1951096 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1951712 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52835693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52852374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27652126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27652126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27652126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52835693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80504500 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4727325935 # number of cpu cycles simulated +system.cpu.numCycles 4726734423 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759602 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4727325934.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4726734422.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462427 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.733673 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.732137 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164659000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733673 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 25164659500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732137 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143400508500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143400508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57355969000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57355969000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200756477500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200756477500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200756477500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200756477500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143051795500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143051795500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57408921000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57408921000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200460716500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200460716500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200460716500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200460716500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19844.838340 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19844.838340 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30360.743912 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30360.743912 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22024.278858 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22024.278858 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22024.276442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22024.276442 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.580818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.580818 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.831971 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21991.831971 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.829559 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21991.829559 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,8 +302,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks -system.cpu.dcache.writebacks::total 3697418 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks +system.cpu.dcache.writebacks::total 3681379 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132561379500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 132561379500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54522245500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 54522245500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187083625000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 187083625000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187083678500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187083678500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135825709500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 135825709500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55519772000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 55519772000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191345481500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191345481500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191345535500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 191345535500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -334,26 +334,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18344.838340 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18344.838340 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28860.743912 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28860.743912 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20524.278858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20524.278858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20524.282476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.580818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.580818 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.831971 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.831971 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.835593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.835593 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.003161 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 515.003161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251466 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251466 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id @@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34207000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34207000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34207000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34212000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34212000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34212000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34212000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34212000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34212000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses @@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53615.987461 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53615.987461 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53615.987461 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53615.987461 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53623.824451 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53623.824451 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53623.824451 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53623.824451 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,117 +411,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33250000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33250000 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52623.824451 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52623.824451 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1926075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31008.535032 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150067843000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160482 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876098 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498452 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.477849 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.467728 # 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Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits +system.cpu.l2cache.tags.tag_accesses 149644895 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149644895 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 3681379 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3681379 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414013 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.414013 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214875 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951096 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1951712 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24978000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47681937000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47706915000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31625653000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31625653000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24978000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79307590000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 79332568000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24978000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79307590000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 79332568000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951096 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1951712 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33241050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33241050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26223000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26223000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697201500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697201500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26223000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938251500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82964474500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26223000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938251500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82964474500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214100 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40548.701299 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40501.712419 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40501.736993 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.224107 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.224107 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214100 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.885372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.885372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919018 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.095255 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.293567 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12813292 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18227021 90.47% 90.47% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1919018 9.53% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20146039 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12794889500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1177898 # Transaction distribution -system.membus.trans_dist::ReadResp 1177898 # Transaction distribution -system.membus.trans_dist::Writeback 1017198 # Transaction distribution -system.membus.trans_dist::ReadExReq 780876 # Transaction distribution -system.membus.trans_dist::ReadExResp 780876 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1169580 # Transaction distribution +system.membus.trans_dist::Writeback 1021127 # Transaction distribution +system.membus.trans_dist::CleanEvict 897054 # Transaction distribution +system.membus.trans_dist::ReadExReq 782132 # Transaction distribution +system.membus.trans_dist::ReadExResp 782132 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5821605 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190261696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2975972 # Request fanout histogram +system.membus.snoop_fanout::samples 3870264 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3870264 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2975972 # Request fanout histogram -system.membus.reqLayer0.occupancy 7175472500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3870264 # Request fanout histogram +system.membus.reqLayer0.occupancy 7969342268 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9807518500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9772290268 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |