diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se/60.bzip2/ref/arm/linux | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux')
4 files changed, 1675 insertions, 1652 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index a63511156..ddbab1eb8 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.128034 # Number of seconds simulated -sim_ticks 1128033563500 # Number of ticks simulated -final_tick 1128033563500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.130744 # Number of seconds simulated +sim_ticks 1130744162500 # Number of ticks simulated +final_tick 1130744162500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 296898 # Simulator instruction rate (inst/s) -host_op_rate 319862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216832014 # Simulator tick rate (ticks/s) -host_mem_usage 266856 # Number of bytes of host memory used -host_seconds 5202.34 # Real time elapsed on the host +host_inst_rate 210155 # Simulator instruction rate (inst/s) +host_op_rate 226410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153850224 # Simulator tick rate (ticks/s) +host_mem_usage 274312 # Number of bytes of host memory used +host_seconds 7349.64 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130888128 # Number of bytes read from this memory -system.physmem.bytes_read::total 130938240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67194432 # Number of bytes written to this memory -system.physmem.bytes_written::total 67194432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2045910 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1049913 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1049913 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 44424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 116032122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116076546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 44424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 59567759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 59567759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 59567759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 44424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 116032122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 175644306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2045910 # Number of read requests accepted -system.physmem.writeReqs 1049913 # Number of write requests accepted -system.physmem.readBursts 2045910 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1049913 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130851840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 86400 # Total number of bytes read from write queue -system.physmem.bytesWritten 67192960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130938240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67194432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1350 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132094976 # Number of bytes read from this memory +system.physmem.bytes_read::total 132145216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67850112 # Number of bytes written to this memory +system.physmem.bytes_written::total 67850112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2063984 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2064769 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1060158 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1060158 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 44431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 116821276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116865707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 44431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60004831 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60004831 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60004831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 44431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 116821276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 176870538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2064769 # Number of read requests accepted +system.physmem.writeReqs 1060158 # Number of write requests accepted +system.physmem.readBursts 2064769 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1060158 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 132060352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue +system.physmem.bytesWritten 67848640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132145216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67850112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127234 # Per bank write bursts -system.physmem.perBankRdBursts::1 124635 # Per bank write bursts -system.physmem.perBankRdBursts::2 121565 # Per bank write bursts -system.physmem.perBankRdBursts::3 123578 # Per bank write bursts -system.physmem.perBankRdBursts::4 122544 # Per bank write bursts -system.physmem.perBankRdBursts::5 122632 # Per bank write bursts -system.physmem.perBankRdBursts::6 123221 # Per bank write bursts -system.physmem.perBankRdBursts::7 123735 # Per bank write bursts -system.physmem.perBankRdBursts::8 131340 # Per bank write bursts -system.physmem.perBankRdBursts::9 133478 # Per bank write bursts -system.physmem.perBankRdBursts::10 132036 # Per bank write bursts -system.physmem.perBankRdBursts::11 133242 # Per bank write bursts -system.physmem.perBankRdBursts::12 133211 # Per bank write bursts -system.physmem.perBankRdBursts::13 133326 # Per bank write bursts -system.physmem.perBankRdBursts::14 129274 # Per bank write bursts -system.physmem.perBankRdBursts::15 129509 # Per bank write bursts -system.physmem.perBankWrBursts::0 66120 # Per bank write bursts -system.physmem.perBankWrBursts::1 64398 # Per bank write bursts -system.physmem.perBankWrBursts::2 62563 # Per bank write bursts -system.physmem.perBankWrBursts::3 62980 # Per bank write bursts -system.physmem.perBankWrBursts::4 62981 # Per bank write bursts -system.physmem.perBankWrBursts::5 63086 # Per bank write bursts -system.physmem.perBankWrBursts::6 64437 # Per bank write bursts -system.physmem.perBankWrBursts::7 65431 # Per bank write bursts -system.physmem.perBankWrBursts::8 67296 # Per bank write bursts -system.physmem.perBankWrBursts::9 67792 # Per bank write bursts -system.physmem.perBankWrBursts::10 67535 # Per bank write bursts -system.physmem.perBankWrBursts::11 67858 # Per bank write bursts -system.physmem.perBankWrBursts::12 67312 # Per bank write bursts -system.physmem.perBankWrBursts::13 67784 # Per bank write bursts -system.physmem.perBankWrBursts::14 66474 # Per bank write bursts -system.physmem.perBankWrBursts::15 65843 # Per bank write bursts +system.physmem.perBankRdBursts::0 128520 # Per bank write bursts +system.physmem.perBankRdBursts::1 125806 # Per bank write bursts +system.physmem.perBankRdBursts::2 122672 # Per bank write bursts +system.physmem.perBankRdBursts::3 124571 # Per bank write bursts +system.physmem.perBankRdBursts::4 123572 # Per bank write bursts +system.physmem.perBankRdBursts::5 123679 # Per bank write bursts +system.physmem.perBankRdBursts::6 124365 # Per bank write bursts +system.physmem.perBankRdBursts::7 124958 # Per bank write bursts +system.physmem.perBankRdBursts::8 132489 # Per bank write bursts +system.physmem.perBankRdBursts::9 134780 # Per bank write bursts +system.physmem.perBankRdBursts::10 133233 # Per bank write bursts +system.physmem.perBankRdBursts::11 134506 # Per bank write bursts +system.physmem.perBankRdBursts::12 134518 # Per bank write bursts +system.physmem.perBankRdBursts::13 134594 # Per bank write bursts +system.physmem.perBankRdBursts::14 130540 # Per bank write bursts +system.physmem.perBankRdBursts::15 130640 # Per bank write bursts +system.physmem.perBankWrBursts::0 66781 # Per bank write bursts +system.physmem.perBankWrBursts::1 64941 # Per bank write bursts +system.physmem.perBankWrBursts::2 63173 # Per bank write bursts +system.physmem.perBankWrBursts::3 63584 # Per bank write bursts +system.physmem.perBankWrBursts::4 63558 # Per bank write bursts +system.physmem.perBankWrBursts::5 63644 # Per bank write bursts +system.physmem.perBankWrBursts::6 65047 # Per bank write bursts +system.physmem.perBankWrBursts::7 66055 # Per bank write bursts +system.physmem.perBankWrBursts::8 67972 # Per bank write bursts +system.physmem.perBankWrBursts::9 68438 # Per bank write bursts +system.physmem.perBankWrBursts::10 68161 # Per bank write bursts +system.physmem.perBankWrBursts::11 68586 # Per bank write bursts +system.physmem.perBankWrBursts::12 68040 # Per bank write bursts +system.physmem.perBankWrBursts::13 68530 # Per bank write bursts +system.physmem.perBankWrBursts::14 67159 # Per bank write bursts +system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1128033469500 # Total gap between requests +system.physmem.totGap 1130744067500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2045910 # Read request sizes (log2) +system.physmem.readPktSize::6 2064769 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1049913 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1917702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126844 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1060158 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1931837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131592 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,113 +194,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910047 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.685692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.490486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485463 77.77% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305174 15.98% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52509 2.75% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20929 1.10% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13256 0.69% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7619 0.40% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5519 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5102 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14476 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910047 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61113 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.412400 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 159.518866 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61065 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 24 0.04% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1925169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.839212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.850367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 126.421931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1496084 77.71% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 309482 16.08% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52255 2.71% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20716 1.08% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12793 0.66% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7748 0.40% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5753 0.30% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5054 0.26% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15284 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1925169 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.244314 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.928422 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 148.698604 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61952 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61113 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.179487 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.144319 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.100540 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 26981 44.15% 44.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1028 1.68% 45.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28814 47.15% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3825 6.26% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 400 0.65% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 47 0.08% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 11 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61113 # Writes before turning the bus around for reads -system.physmem.totQLat 38097515250 # Total ticks spent queuing -system.physmem.totMemAccLat 76433015250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10222800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18633.60 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 61990 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.101710 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.070337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.034747 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 28322 45.69% 45.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1015 1.64% 47.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 30732 49.58% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1873 3.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 43 0.07% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61990 # Writes before turning the bus around for reads +system.physmem.totQLat 38536102500 # Total ticks spent queuing +system.physmem.totMemAccLat 77225658750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10317215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18675.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37383.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 59.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.08 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 59.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37425.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 116.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.87 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.37 # Data bus utilization in percentage +system.physmem.busUtil 1.38 # Data bus utilization in percentage system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 772369 # Number of row buffer hits during reads -system.physmem.writeRowHits 412032 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.24 # Row buffer hit rate for writes -system.physmem.avgGap 364372.73 # Average gap between requests -system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7040703600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3841653750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7715315400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3317734080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 423036881190 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 305734953750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 824364871770 # Total energy per rank (pJ) -system.physmem_0.averagePower 730.798394 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 505893058250 # Time in different power states -system.physmem_0.memoryStateTime::REF 37667500000 # Time in different power states +system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing +system.physmem.readRowHits 775929 # Number of row buffer hits during reads +system.physmem.writeRowHits 422476 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.85 # Row buffer hit rate for writes +system.physmem.avgGap 361846.55 # Average gap between requests +system.physmem.pageHitRate 38.37 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7091695800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3869476875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7785421800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3348753840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 423921506085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 306584736000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 826456199280 # Total energy per rank (pJ) +system.physmem_0.averagePower 730.896688 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 507283799000 # Time in different power states +system.physmem_0.memoryStateTime::REF 37757980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 584472684250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 585701078500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7399251720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4037290125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8232221400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3485553120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 432494110575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 297439138500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 826765195440 # Total energy per rank (pJ) -system.physmem_1.averagePower 732.926278 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 492041493250 # Time in different power states -system.physmem_1.memoryStateTime::REF 37667500000 # Time in different power states +system.physmem_1.actEnergy 7462581840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4071845250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8309316600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3520920960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 432965070225 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 298651785000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 828836128755 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.001436 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 494051909000 # Time in different power states +system.physmem_1.memoryStateTime::REF 37757980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 598324400250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 598934101500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019627 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610234 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240019432 # Number of BP lookups +system.cpu.branchPred.condPredicted 186610009 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131647639 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324320 # Number of BTB hits +system.cpu.branchPred.BTBLookups 131647101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122324380 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.917975 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15657430 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.918400 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 534 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 302 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,16 +419,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2256067127 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2261488325 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363716 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41363718 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.460651 # CPI: cycles per instruction -system.cpu.ipc 0.684626 # IPC: instructions per cycle +system.cpu.cpi 1.464161 # CPI: cycles per instruction +system.cpu.ipc 0.682985 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -466,61 +464,61 @@ system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1844612574 # Number of cycles that the object actually ticked -system.cpu.idleCycles 411454553 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220101 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.702912 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624495427 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.701874 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9818932500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.702912 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997486 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997486 # Average percentage of cache occupancy +system.cpu.tickCycles 1844743027 # Number of cycles that the object actually ticked +system.cpu.idleCycles 416745298 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220102 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.712457 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624495296 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224198 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.701853 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9823555500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.712457 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997488 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997488 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 241 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1240 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391791 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391791 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454164210 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454164210 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331094 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331094 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277391740 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277391740 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454164183 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454164183 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170330990 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170330990 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624495304 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624495304 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624495305 # number of overall hits -system.cpu.dcache.overall_hits::total 624495305 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333415 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333415 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254953 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254953 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624495173 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624495173 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624495174 # number of overall hits +system.cpu.dcache.overall_hits::total 624495174 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333416 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333416 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2255057 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2255057 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9588368 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9588368 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9588370 # number of overall misses -system.cpu.dcache.overall_misses::total 9588370 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190988166000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190988166000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108977258000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108977258000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 299965424000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 299965424000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 299965424000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 299965424000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9588473 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9588473 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9588475 # number of overall misses +system.cpu.dcache.overall_misses::total 9588475 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192638967000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192638967000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 111261397000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 111261397000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 303900364000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 303900364000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 303900364000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 303900364000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461497599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461497599 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -529,10 +527,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083672 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083672 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083675 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083675 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634083646 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634083646 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634083649 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634083649 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses @@ -543,50 +541,50 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015122 system.cpu.dcache.demand_miss_rate::total 0.015122 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26043.550788 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26043.550788 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48327.950960 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48327.950960 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.304482 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31284.304482 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.297957 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31284.297957 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26268.653926 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26268.653926 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49338.618492 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49338.618492 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31694.344240 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31694.344240 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31694.337629 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31694.337629 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3684499 # number of writebacks -system.cpu.dcache.writebacks::total 3684499 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3670051 # number of writebacks +system.cpu.dcache.writebacks::total 3670051 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364123 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364123 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364172 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364172 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364172 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364172 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333366 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333366 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364227 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364227 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364276 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364276 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364276 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364276 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333367 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333367 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224196 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224196 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224197 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183652478000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183652478000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84692070000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84692070000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268344548000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268344548000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268344622000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268344622000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224198 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224198 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 185303496000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 185303496000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86626211500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86626211500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 271929707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 271929707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 271929782500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 271929782500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -597,338 +595,344 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25043.408170 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.408170 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44790.948948 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44790.948948 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.375335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.375335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.380204 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.380204 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 30 # number of replacements -system.cpu.icache.tags.tagsinuse 660.287317 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466254411 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 569297.205128 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25268.542540 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25268.542540 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45813.855027 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45813.855027 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29480.041189 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29480.041189 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29480.046124 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29480.046124 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 33 # number of replacements +system.cpu.icache.tags.tagsinuse 660.343836 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466264831 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 567232.154501 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.287317 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322406 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322406 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 660.343836 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322434 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322434 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 752 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932511279 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932511279 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466254411 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466254411 # 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Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466264831 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466264831 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466264831 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466264831 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466264831 # number of overall hits +system.cpu.icache.overall_hits::total 466264831 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses +system.cpu.icache.overall_misses::total 822 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62977000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62977000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62977000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62977000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62977000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62977000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466265653 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466265653 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466265653 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466265653 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466265653 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466265653 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75323.565324 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75323.565324 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75323.565324 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75323.565324 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76614.355231 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76614.355231 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76614.355231 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76614.355231 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21737 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149613593 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149613593 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 3670051 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3670051 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1078506 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1078506 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # 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miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954988 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223758 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.223823 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89177.093746 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89177.093746 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77071.337580 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77071.337580 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88236.430485 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88236.430485 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77071.337580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88606.647077 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88602.261505 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77071.337580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88606.647077 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88602.261505 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1049913 # number of writebacks -system.cpu.l2cache.writebacks::total 1049913 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1060158 # number of writebacks +system.cpu.l2cache.writebacks::total 1060158 # number of writebacks system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 214 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 214 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801012 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 801012 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 783 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 783 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244115 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244115 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2045127 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2045910 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2045127 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2045910 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62379174000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62379174000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51402000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51402000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96270618000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96270618000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51402000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158649792000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 158701194000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51402000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158649792000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158701194000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812324 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 812324 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251660 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251660 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2063984 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2064769 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2063984 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2064769 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64317453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64317453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52651000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52651000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 97925523500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 97925523500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52651000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162242977000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 162295628000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52651000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162242977000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 162295628000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423630 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423630 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169651 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169651 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221713 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.221778 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221713 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.221778 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77875.455049 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77875.455049 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65647.509579 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65647.509579 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77380.803222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77380.803222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445147 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220143 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.223823 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.223823 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79177.093746 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79177.093746 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67071.337580 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67071.337580 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78236.520701 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78236.520701 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445155 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220147 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1285 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1445 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334186 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4734412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 30 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6498928 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4730209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333367 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1668 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670163 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826156544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 826210880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013239 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67194432 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11238255 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.016087 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333368 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670175 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825231936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 825286656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2032337 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67850112 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11257357 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000272 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016509 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11235364 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2885 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11254306 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3045 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11238255 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12907102500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11257357 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12892661500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836298494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836299994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1244898 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1049913 # Transaction distribution -system.membus.trans_dist::CleanEvict 962255 # Transaction distribution -system.membus.trans_dist::ReadExReq 801012 # Transaction distribution -system.membus.trans_dist::ReadExResp 801012 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1244898 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6103988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6103988 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198132672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198132672 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 4095876 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2031264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1252445 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1060158 # Transaction distribution +system.membus.trans_dist::CleanEvict 970949 # Transaction distribution +system.membus.trans_dist::ReadExReq 812324 # Transaction distribution +system.membus.trans_dist::ReadExResp 812324 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1252445 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6160645 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 199995328 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4058078 # Request fanout histogram +system.membus.snoop_fanout::samples 2064769 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4058078 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2064769 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4058078 # Request fanout histogram -system.membus.reqLayer0.occupancy 8755432500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2064769 # Request fanout histogram +system.membus.reqLayer0.occupancy 8803577000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11187827500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11289358000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 3edaccc65..4f03996ba 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.767804 # Number of seconds simulated -sim_ticks 767803843500 # Number of ticks simulated -final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.770752 # Number of seconds simulated +sim_ticks 770752376500 # Number of ticks simulated +final_tick 770752376500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212750 # Simulator instruction rate (inst/s) -host_op_rate 229206 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 105758139 # Simulator tick rate (ticks/s) -host_mem_usage 308972 # Number of bytes of host memory used -host_seconds 7260.00 # Real time elapsed on the host +host_inst_rate 147248 # Simulator instruction rate (inst/s) +host_op_rate 158637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73478006 # Simulator tick rate (ticks/s) +host_mem_usage 329736 # Number of bytes of host memory used +host_seconds 10489.57 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory -system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory -system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4673385 # Number of read requests accepted -system.physmem.writeReqs 1635896 # Number of write requests accepted -system.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue -system.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 236002624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63781504 # Number of bytes read from this memory +system.physmem.bytes_read::total 299849792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104607936 # Number of bytes written to this memory +system.physmem.bytes_written::total 104607936 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3687541 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 996586 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4685153 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634499 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634499 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 85195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306197725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82752264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389035183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 85195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 135721847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 135721847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 135721847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 85195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306197725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82752264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 524757030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4685154 # Number of read requests accepted +system.physmem.writeReqs 1634499 # Number of write requests accepted +system.physmem.readBursts 4685154 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634499 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 299347712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 502144 # Total number of bytes read from write queue +system.physmem.bytesWritten 104604544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299849856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104607936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7846 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301126 # Per bank write bursts -system.physmem.perBankRdBursts::1 298685 # Per bank write bursts -system.physmem.perBankRdBursts::2 284250 # Per bank write bursts -system.physmem.perBankRdBursts::3 287696 # Per bank write bursts -system.physmem.perBankRdBursts::4 287908 # Per bank write bursts -system.physmem.perBankRdBursts::5 285921 # Per bank write bursts -system.physmem.perBankRdBursts::6 280645 # Per bank write bursts -system.physmem.perBankRdBursts::7 277366 # Per bank write bursts -system.physmem.perBankRdBursts::8 293768 # Per bank write bursts -system.physmem.perBankRdBursts::9 299240 # Per bank write bursts -system.physmem.perBankRdBursts::10 292091 # Per bank write bursts -system.physmem.perBankRdBursts::11 297828 # Per bank write bursts -system.physmem.perBankRdBursts::12 299005 # Per bank write bursts -system.physmem.perBankRdBursts::13 298032 # Per bank write bursts -system.physmem.perBankRdBursts::14 293386 # Per bank write bursts -system.physmem.perBankRdBursts::15 288652 # Per bank write bursts -system.physmem.perBankWrBursts::0 103980 # Per bank write bursts -system.physmem.perBankWrBursts::1 101811 # Per bank write bursts -system.physmem.perBankWrBursts::2 99205 # Per bank write bursts -system.physmem.perBankWrBursts::3 99712 # Per bank write bursts -system.physmem.perBankWrBursts::4 99000 # Per bank write bursts -system.physmem.perBankWrBursts::5 99026 # Per bank write bursts -system.physmem.perBankWrBursts::6 102693 # Per bank write bursts -system.physmem.perBankWrBursts::7 104157 # Per bank write bursts -system.physmem.perBankWrBursts::8 105172 # Per bank write bursts -system.physmem.perBankWrBursts::9 104159 # Per bank write bursts -system.physmem.perBankWrBursts::10 102137 # Per bank write bursts -system.physmem.perBankWrBursts::11 102620 # Per bank write bursts -system.physmem.perBankWrBursts::12 102863 # Per bank write bursts -system.physmem.perBankWrBursts::13 102594 # Per bank write bursts -system.physmem.perBankWrBursts::14 104213 # Per bank write bursts -system.physmem.perBankWrBursts::15 102497 # Per bank write bursts +system.physmem.perBankRdBursts::0 301314 # Per bank write bursts +system.physmem.perBankRdBursts::1 301808 # Per bank write bursts +system.physmem.perBankRdBursts::2 285079 # Per bank write bursts +system.physmem.perBankRdBursts::3 287721 # Per bank write bursts +system.physmem.perBankRdBursts::4 288732 # Per bank write bursts +system.physmem.perBankRdBursts::5 286480 # Per bank write bursts +system.physmem.perBankRdBursts::6 281880 # Per bank write bursts +system.physmem.perBankRdBursts::7 278193 # Per bank write bursts +system.physmem.perBankRdBursts::8 293719 # Per bank write bursts +system.physmem.perBankRdBursts::9 299847 # Per bank write bursts +system.physmem.perBankRdBursts::10 291529 # Per bank write bursts +system.physmem.perBankRdBursts::11 297903 # Per bank write bursts +system.physmem.perBankRdBursts::12 299405 # Per bank write bursts +system.physmem.perBankRdBursts::13 299387 # Per bank write bursts +system.physmem.perBankRdBursts::14 294305 # Per bank write bursts +system.physmem.perBankRdBursts::15 290006 # Per bank write bursts +system.physmem.perBankWrBursts::0 103629 # Per bank write bursts +system.physmem.perBankWrBursts::1 101748 # Per bank write bursts +system.physmem.perBankWrBursts::2 99222 # Per bank write bursts +system.physmem.perBankWrBursts::3 99944 # Per bank write bursts +system.physmem.perBankWrBursts::4 98990 # Per bank write bursts +system.physmem.perBankWrBursts::5 98822 # Per bank write bursts +system.physmem.perBankWrBursts::6 102440 # Per bank write bursts +system.physmem.perBankWrBursts::7 104048 # Per bank write bursts +system.physmem.perBankWrBursts::8 105134 # Per bank write bursts +system.physmem.perBankWrBursts::9 103994 # Per bank write bursts +system.physmem.perBankWrBursts::10 101818 # Per bank write bursts +system.physmem.perBankWrBursts::11 102570 # Per bank write bursts +system.physmem.perBankWrBursts::12 102850 # Per bank write bursts +system.physmem.perBankWrBursts::13 102376 # Per bank write bursts +system.physmem.perBankWrBursts::14 104237 # Per bank write bursts +system.physmem.perBankWrBursts::15 102624 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 767803802500 # Total gap between requests +system.physmem.totGap 770752366000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4673385 # Read request sizes (log2) +system.physmem.readPktSize::6 4685154 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1635896 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634499 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2776424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1031022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 327510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 229431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 146630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 80164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 110766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 100949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,123 +198,130 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads -system.physmem.totQLat 128478496877 # Total ticks spent queuing -system.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4255173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.931559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.862227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.833954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3394354 79.77% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 663703 15.60% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94226 2.21% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35436 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22765 0.53% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12171 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7342 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19831 0.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4255173 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97794 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.827914 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.473591 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 93707 95.82% 95.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1671 1.71% 97.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 768 0.79% 98.31% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 406 0.42% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 365 0.37% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 337 0.34% 99.45% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 234 0.24% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 165 0.17% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 89 0.09% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 24 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 12 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1664-1791 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3968-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97794 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97794 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.713152 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.671812 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.223073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68724 70.27% 70.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1896 1.94% 72.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18671 19.09% 91.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5634 5.76% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1729 1.77% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 613 0.63% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 266 0.27% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 147 0.15% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 67 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 30 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97794 # Writes before turning the bus around for reads +system.physmem.totQLat 128325813562 # Total ticks spent queuing +system.physmem.totMemAccLat 216025338562 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23386540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27435.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46185.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 135.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 135.72 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.10 # Data bus utilization in percentage -system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes +system.physmem.busUtil 4.09 # Data bus utilization in percentage +system.physmem.busUtilRead 3.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing -system.physmem.readRowHits 1710736 # Number of row buffer hits during reads -system.physmem.writeRowHits 347188 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing +system.physmem.readRowHits 1715091 # Number of row buffer hits during reads +system.physmem.writeRowHits 341475 # Number of row buffer hits during writes system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes -system.physmem.avgGap 121694.34 # Average gap between requests -system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.947771 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states -system.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states +system.physmem.writeRowHitRate 20.89 # Row buffer hit rate for writes +system.physmem.avgGap 121961.18 # Average gap between requests +system.physmem.pageHitRate 32.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15989112720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8724218250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18025846800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5241069360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 417928675995 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 95843265750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 612093526155 # Total energy per rank (pJ) +system.physmem_0.averagePower 794.157652 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 156909498029 # Time in different power states +system.physmem_0.memoryStateTime::REF 25736880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states +system.physmem_0.memoryStateTime::ACT 588099785971 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.363055 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states -system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states +system.physmem_1.actEnergy 16179556680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8828131125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18455494200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5349602880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 412908393870 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100247038500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 612309554535 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.437909 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 164276600328 # Time in different power states +system.physmem_1.memoryStateTime::REF 25736880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states +system.physmem_1.memoryStateTime::ACT 580733308672 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286292198 # Number of BP lookups -system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 286275195 # Number of BP lookups +system.cpu.branchPred.condPredicted 223398341 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14628424 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157667483 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150349199 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.358406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16643020 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3069 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1906 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1163 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 137 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -344,7 +351,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -374,7 +381,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -404,7 +411,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -435,95 +442,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1535607688 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1541504754 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13925502 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067484101 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286275195 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166994125 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1512857238 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29281631 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 279 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1018 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656940019 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 946 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1541424852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.436951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229037 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 459011037 29.78% 29.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465435057 30.20% 59.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101419068 6.58% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515559690 33.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849925630 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837854747 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128568020 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1541424852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185712 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.341212 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74709451 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 544021839 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849845592 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58207832 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14640138 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42201657 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 726 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037180089 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52484609 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14640138 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139806563 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 462600801 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15884 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837785307 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86576159 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976384850 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26739549 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45323653 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126929 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1602638 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25499860 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985860548 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128169124 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432875929 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 174 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 310961603 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 175 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 111534180 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542566077 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199303375 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26892889 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29237160 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947969517 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647584065 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1857492369 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13496690 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283937332 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647289356 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1541424852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.205049 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150817 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 588435916 38.17% 38.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326131475 21.16% 59.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378210554 24.54% 83.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219654013 14.25% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28986723 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6171 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1541424852 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166021321 40.99% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1993 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available @@ -551,13 +558,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191489776 47.28% 88.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47539480 11.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138243662 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800931 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -579,88 +586,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532135699 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186312026 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued -system.cpu.iq.rate 1.209614 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857492369 # Type of FU issued +system.cpu.iq.rate 1.204986 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405052570 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218064 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5674958613 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231919871 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805704142 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262544806 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17811536 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84259743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66618 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13244 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24456330 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4512030 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4891489 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14640138 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25364964 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1346928 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947969899 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 542566077 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199303375 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 159350 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1186169 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13244 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7699482 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8703162 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16402644 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827831567 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516957415 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29660802 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 146 # number of nop insts executed -system.cpu.iew.exec_refs 698692225 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542687 # Number of branches executed -system.cpu.iew.exec_stores 181751910 # Number of stores executed -system.cpu.iew.exec_rate 1.190295 # Inst execution rate -system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169207800 # num instructions producing a value -system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value -system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle +system.cpu.iew.exec_nop 151 # number of nop insts executed +system.cpu.iew.exec_refs 698708795 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542425 # Number of branches executed +system.cpu.iew.exec_stores 181751380 # Number of stores executed +system.cpu.iew.exec_rate 1.185745 # Inst execution rate +system.cpu.iew.wb_sent 1808736265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805704212 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169174812 # num instructions producing a value +system.cpu.iew.wb_consumers 1689572222 # num instructions consuming a value +system.cpu.iew.wb_rate 1.171391 # insts written-back per cycle system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258041892 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14627747 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1501940299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.107922 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.025263 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 921653315 61.36% 61.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250636600 16.69% 78.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110060462 7.33% 85.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55269176 3.68% 89.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29319156 1.95% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34080655 2.27% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24723288 1.65% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18133421 1.21% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58064226 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1501940299 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -706,78 +713,78 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3360114616 # The number of ROB reads -system.cpu.rob.rob_writes 3883791528 # The number of ROB writes -system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58064226 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3365949800 # The number of ROB reads +system.cpu.rob.rob_writes 3883638365 # The number of ROB writes +system.cpu.timesIdled 837 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79902 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads -system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads -system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes +system.cpu.cpi 0.998020 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.998020 # CPI: Total CPI of All Threads +system.cpu.ipc 1.001984 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.001984 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175818987 # number of integer regfile reads +system.cpu.int_regfile_writes 1261576435 # number of integer regfile writes system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 54 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads -system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes -system.cpu.misc_regfile_reads 675853618 # number of misc regfile reads +system.cpu.fp_regfile_writes 52 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965775009 # number of cc regfile reads +system.cpu.cc_regfile_writes 551856674 # number of cc regfile writes +system.cpu.misc_regfile_reads 675846934 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17003710 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 17003150 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964340 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638065664 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17003662 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 79206500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964340 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 406 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335709608 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335709608 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 469347574 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469347574 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168717937 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168717937 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits -system.cpu.dcache.overall_hits::total 638076218 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638065511 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638065511 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638065511 # number of overall hits +system.cpu.dcache.overall_hits::total 638065511 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17419228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17419228 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3868110 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3868110 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses -system.cpu.dcache.overall_misses::total 21285744 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21287338 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21287338 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21287340 # number of overall misses +system.cpu.dcache.overall_misses::total 21287340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 416423435500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 416423435500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 150253086257 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 150253086257 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 199500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 566676521757 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 566676521757 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 566676521757 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 566676521757 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486766802 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486766802 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -786,470 +793,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659352849 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659352849 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659352851 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659352851 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022413 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022413 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks -system.cpu.dcache.writebacks::total 17003710 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.032285 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032285 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032285 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032285 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23905.963887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23905.963887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38844.057242 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38844.057242 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49875 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49875 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26620.356277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26620.356277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26620.353776 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26620.353776 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20685246 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3452781 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 946049 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67233 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.864878 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51.355450 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 17003150 # number of writebacks +system.cpu.dcache.writebacks::total 17003150 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3153076 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3153076 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130592 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1130592 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281515 # 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number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17003670 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17003670 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17003671 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17003671 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335207977500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 335207977500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116679674033 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116679674033 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451887651533 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 451887651533 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451887720533 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 451887720533 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 589 # number of replacements -system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025788 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025788 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23496.733913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23496.733913 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42622.431718 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42622.431718 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26575.889295 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26575.889295 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26575.891790 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26575.891790 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 588 # number of replacements +system.cpu.icache.tags.tagsinuse 444.874436 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656938405 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 611674.492551 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 444.874436 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868895 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868895 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits -system.cpu.icache.overall_hits::total 656966815 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses -system.cpu.icache.overall_misses::total 1620 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 98788987 # 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Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 656938405 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656938405 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656938405 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656938405 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656938405 # number of overall hits +system.cpu.icache.overall_hits::total 656938405 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1611 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1611 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1611 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1611 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1611 # number of overall misses +system.cpu.icache.overall_misses::total 1611 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 103785485 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 103785485 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 103785485 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 103785485 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 103785485 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 103785485 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656940016 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656940016 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656940016 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656940016 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656940016 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656940016 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60980.856173 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 589 # number of writebacks -system.cpu.icache.writebacks::total 589 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64423.019863 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64423.019863 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64423.019863 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64423.019863 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64423.019863 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64423.019863 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 16825 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 586 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 90.945946 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 58.600000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 588 # number of writebacks +system.cpu.icache.writebacks::total 588 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 535 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 535 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 535 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 535 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 535 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73759491 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 73759491 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73759491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 73759491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73759491 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 73759491 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75943989 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75943989 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75943989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75943989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75943989 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75943989 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70579.915428 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70579.915428 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70579.915428 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70579.915428 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70579.915428 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70579.915428 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 11612917 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11641367 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 19112 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 4706089 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.119162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.799460 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000140 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982651 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15097 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 636 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 191 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11522367 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 11522367 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 56 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13279454 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13279510 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 56 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13279454 # number of overall hits -system.cpu.l2cache.overall_hits::total 13279510 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 980546 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 980546 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1020 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1020 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2744222 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2744222 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1020 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3724768 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3725788 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1020 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3724768 # number of overall misses -system.cpu.l2cache.overall_misses::total 3725788 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 121000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 121000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99083213500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 99083213500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72272000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 72272000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 72272000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 333235195500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 72272000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 333235195500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 4833112 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 4833112 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 12149903 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 12149903 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737633 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737633 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.prefetcher.pfSpanPage 4655505 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 4647068 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15866.736257 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13267029 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4662976 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.845185 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15646.626307 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 220.109950 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.954994 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013434 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.968429 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 143 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 463 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4068 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7095 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2886 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1253 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008728 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 561777243 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 561777243 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 4835234 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 4835234 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 12147319 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 12147319 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1756866 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1756866 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 49 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 49 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11510992 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 11510992 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 49 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 13267858 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13267907 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 49 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 13267858 # number of overall hits +system.cpu.l2cache.overall_hits::total 13267907 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 980689 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 980689 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1027 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1027 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2755115 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2755115 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1027 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3735804 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3736831 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3735804 # number of overall misses +system.cpu.l2cache.overall_misses::total 3736831 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 191500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 191500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100034737999 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 100034737999 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 74500500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 74500500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 237611587999 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 237611587999 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 74500500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 337646325998 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 337720826498 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 74500500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 337646325998 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 337720826498 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 4835234 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 4835234 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 12147319 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 12147319 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 9 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 9 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737555 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2737555 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266589 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 14266589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266107 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 14266107 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17004222 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17005298 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 17003662 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17004738 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17004222 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17005298 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17003662 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17004738 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358173 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.358173 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947955 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947955 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192353 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192353 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947955 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.219050 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.219096 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947955 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.219050 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.219096 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312336320998 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 312404671498 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68350500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312336320998 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 73218164638 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 385622836136 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356810 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356810 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216837 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.287303 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # 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average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84725.402270 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78931.951042 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34008488 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003756 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 201663 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 201662 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 14267181 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6469733 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12168504 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3012569 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1490485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737555 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737555 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 8842499 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104697920 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266107 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2738 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51010503 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51013241 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176436672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176543040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6137564 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104608640 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 23142303 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009630 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097659 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22919446 99.04% 99.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 222856 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23142303 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34007983525 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 16538 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1611000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25505500994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3696594 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution -system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 976790 # Transaction distribution -system.membus.trans_dist::ReadExResp 976790 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 9332231 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 4668264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3708204 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634499 # Transaction distribution +system.membus.trans_dist::CleanEvict 3012569 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 976948 # Transaction distribution +system.membus.trans_dist::ReadExResp 976948 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3708206 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14017383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14017383 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404457664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 404457664 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 9311100 # Request fanout histogram +system.membus.snoop_fanout::samples 4685163 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4685163 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9311100 # Request fanout histogram -system.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4685163 # Request fanout histogram +system.membus.reqLayer0.occupancy 17662405597 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25476549560 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index a861bb889..ddb5178a1 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1008264 # Simulator instruction rate (inst/s) -host_op_rate 1086251 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 543126570 # Simulator tick rate (ticks/s) -host_mem_usage 256604 # Number of bytes of host memory used -host_seconds 1531.90 # Real time elapsed on the host +host_inst_rate 1176831 # Simulator instruction rate (inst/s) +host_op_rate 1267857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 633929666 # Simulator tick rate (ticks/s) +host_mem_usage 260476 # Number of bytes of host memory used +host_seconds 1312.48 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 8383808423 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram -system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2172060895 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2172060895 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index e3d403cda..02e32a48c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.377030 # Number of seconds simulated -sim_ticks 2377029670500 # Number of ticks simulated -final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.379922 # Number of seconds simulated +sim_ticks 2379921906500 # Number of ticks simulated +final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 744525 # Simulator instruction rate (inst/s) -host_op_rate 802329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1150119113 # Simulator tick rate (ticks/s) -host_mem_usage 266344 # Number of bytes of host memory used -host_seconds 2066.77 # Real time elapsed on the host +host_inst_rate 802178 # Simulator instruction rate (inst/s) +host_op_rate 864460 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1240688848 # Simulator tick rate (ticks/s) +host_mem_usage 272000 # Number of bytes of host memory used +host_seconds 1918.23 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory -system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory +system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory -system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory +system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 4754059341 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 4759843813 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759602 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462427 # Number of branches fetched @@ -221,26 +221,26 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -263,14 +263,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 217010491500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 217010491500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 217010491500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 217010491500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -295,22 +295,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21141.000605 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21141.000605 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.742189 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.742189 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23807.448903 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23807.448903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23807.446291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23807.446291 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks -system.cpu.dcache.writebacks::total 3681379 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3667054 # number of writebacks +system.cpu.dcache.writebacks::total 3667054 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses @@ -321,16 +321,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145540602500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 145540602500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62354654000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62354654000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207895256500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 207895256500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207895318500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 207895318500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -341,26 +341,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20141.000605 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20141.000605 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.742189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.742189 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.169434 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 515.169434 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251548 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id @@ -368,7 +368,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 606 system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39132000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39132000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39132000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39132000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39132000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39132000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,90 +419,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38494000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38494000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38494000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38494000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38494000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38494000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1919027 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 99527540500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420134 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420134 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162779 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216169 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216169 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.083155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.083155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1220 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4698763 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6350490 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution @@ -620,53 +620,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919027 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65352128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818066560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818107840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1938113 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66029376 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11053987 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000215 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.014666 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2378 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11053987 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1169580 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution -system.membus.trans_dist::CleanEvict 897056 # Transaction distribution -system.membus.trans_dist::ReadExReq 782134 # Transaction distribution -system.membus.trans_dist::ReadExResp 782134 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3907683 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1937205 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1176874 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1031709 # Transaction distribution +system.membus.trans_dist::CleanEvict 905404 # Transaction distribution +system.membus.trans_dist::ReadExReq 793696 # Transaction distribution +system.membus.trans_dist::ReadExResp 793696 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1176874 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5878253 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192145856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192145856 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3869897 # Request fanout histogram +system.membus.snoop_fanout::samples 1970570 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1970570 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3869897 # Request fanout histogram -system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1970570 # Request fanout histogram +system.membus.reqLayer0.occupancy 8048170000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9852850000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |