diff options
| author | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-07-23 16:09:05 -0500 |
|---|---|---|
| committer | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-07-23 16:09:05 -0500 |
| commit | 5d0b25ba3f82b6d563b3fabd3de71f3ceabb140d (patch) | |
| tree | 0b8cdef424988f3486a9f2cebbb49f76b74ae8f9 /tests/long/se/60.bzip2/ref/arm/linux | |
| parent | 0e8a90f06bd3db00f700891a33458353478cce76 (diff) | |
| download | gem5-5d0b25ba3f82b6d563b3fabd3de71f3ceabb140d.tar.xz | |
cpu: Minor CPU add regression tests for ARM and ALPHA
This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux')
4 files changed, 1581 insertions, 0 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini new file mode 100644 index 000000000..f226b0fa2 --- /dev/null +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini @@ -0,0 +1,816 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=262144 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=bzip2 input.source 1 +cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/bzip2 +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.membus] +type=CoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr new file mode 100644 index 000000000..5d8946ede --- /dev/null +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout new file mode 100644 index 000000000..903745948 --- /dev/null +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout @@ -0,0 +1,30 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 11:11:49 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing +Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x1f2b7940 +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 1135900642500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt new file mode 100644 index 000000000..7b16ef532 --- /dev/null +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,733 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 1134079016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 227824 # Simulator instruction rate (inst/s) +host_mem_usage 293824 # Number of bytes of host memory used +host_op_rate 254155 # Simulator op (including micro ops) rate (op/s) +host_seconds 6779.62 # Real time elapsed on the host +host_tick_rate 167277674 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1544563087 # Number of instructions simulated +sim_ops 1723073900 # Number of ops (including micro ops) simulated +sim_seconds 1.134079 # Number of seconds simulated +sim_ticks 1134079016500 # Number of ticks simulated +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 87.938151 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 122192107 # Number of BTB hits +system.cpu.branchPred.BTBLookups 138952327 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 14597136 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 197361074 # Number of conditional branches predicted +system.cpu.branchPred.lookups 250285818 # Number of BP lookups +system.cpu.branchPred.usedRAS 13226889 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 1544563087 # Number of instructions committed +system.cpu.committedOps 1723073900 # Number of ops (including micro ops) committed +system.cpu.cpi 1.468479 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses::cpu.inst 485955700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 485955700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24973.063686 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24973.063686 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22917.493937 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22917.493937 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::cpu.inst 478618690 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 478618690 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183227617996 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183227617996 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015098 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015098 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 7337010 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7337010 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 222 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168140794504 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168140794504 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015098 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015098 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336788 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7336788 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45215.138055 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45215.138055 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40855.687627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40855.687627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::cpu.inst 170348428 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170348428 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101174252000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 101174252000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012965 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012965 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 2237619 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2237619 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 346681 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 346681 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77255572250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77255572250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890938 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890938 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 658541747 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 658541747 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29703.696091 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 648967118 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 648967118 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 284401869996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 284401869996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.014539 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014539 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 9574629 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9574629 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 346903 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 346903 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245396366754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245396366754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9227726 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9227726 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 658541747 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 658541747 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29703.696091 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency +system.cpu.dcache.overall_hits::cpu.inst 648967118 # number of overall hits +system.cpu.dcache.overall_hits::total 648967118 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 284401869996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 284401869996 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.014539 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014539 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 9574629 # number of overall misses +system.cpu.dcache.overall_misses::total 9574629 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 346903 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 346903 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245396366754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245396366754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9227726 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9227726 # number of overall MSHR misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1280 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2489 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 70.327970 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 1326311464 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.294010 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997386 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997386 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 9223630 # number of replacements +system.cpu.dcache.tags.sampled_refs 9227726 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 1326311464 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 4085.294010 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 648967240 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 10338720250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 3700800 # number of writebacks +system.cpu.dcache.writebacks::total 3700800 # number of writebacks +system.cpu.discardedOps 51251418 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 468616075 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 468616075 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71218.824455 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71218.824455 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68823.548426 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68823.548426 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 468615249 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 468615249 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58826749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58826749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 826 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 826 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56848251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 56848251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 826 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 468616075 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 468616075 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71218.824455 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71218.824455 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68823.548426 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68823.548426 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 468615249 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 468615249 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 58826749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58826749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 826 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 826 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56848251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56848251 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68823.548426 # average overall mshr miss latency +system.cpu.icache.overall_hits::cpu.inst 468615249 # number of overall hits +system.cpu.icache.overall_hits::total 468615249 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 58826749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58826749 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 826 # number of overall misses +system.cpu.icache.overall_misses::total 826 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56848251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 56848251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # 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Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 29 # number of replacements +system.cpu.icache.tags.sampled_refs 826 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 937232976 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 667.306532 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 468615249 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 378561103 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.680977 # IPC: instructions per cycle +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890938 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1890938 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80530.523230 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80530.523230 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67904.363586 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67904.363586 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090908 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1090908 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64426834500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 64426834500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423086 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.423086 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 800030 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 800030 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54325528000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54325528000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423086 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423086 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800030 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 800030 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7337614 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7337614 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79650.729800 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79650.729800 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67079.515524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67079.515524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::cpu.inst 6081653 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6081653 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100038210250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 100038210250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171167 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.171167 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 1255961 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1255961 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84248920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84248920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171167 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171167 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255956 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255956 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses::writebacks 3700800 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3700800 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 3700800 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700800 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.inst 9228552 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9228552 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79993.076210 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.inst 7172561 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7172561 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.inst 164465044750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 164465044750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222786 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222786 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.inst 2055991 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2055991 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138574448000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138574448000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222785 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055986 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2055986 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.inst 9228552 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9228552 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79993.076210 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency +system.cpu.l2cache.overall_hits::cpu.inst 7172561 # number of overall hits +system.cpu.l2cache.overall_hits::total 7172561 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.inst 164465044750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 164465044750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222786 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.222786 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.inst 2055991 # number of overall misses +system.cpu.l2cache.overall_misses::total 2055991 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138574448000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138574448000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222785 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055986 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055986 # number of overall MSHR misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12891 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15554 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 4.376215 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 107378812 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 14921.737919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 16303.939645 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455375 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.497557 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.952932 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 2023282 # number of replacements +system.cpu.l2cache.tags.sampled_refs 2053058 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 107378812 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 31225.677564 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8984623 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 62285743250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 1046478 # number of writebacks +system.cpu.l2cache.writebacks::total 1046478 # number of writebacks +system.cpu.numCycles 2268158033 # number of cpu cycles simulated +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.tickCycles 1889596930 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 827478528 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1652 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156252 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22157904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10165476000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1402249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14183973746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 729648037 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827425664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 827478528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7337614 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7337614 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890938 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890938 # Transaction distribution +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.membus.data_through_bus 198557696 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158450 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5158450 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 12256366000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 19378736500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.7 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 175082770 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198557696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 198557696 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1255956 # Transaction distribution +system.membus.trans_dist::ReadResp 1255956 # Transaction distribution +system.membus.trans_dist::Writeback 1046478 # Transaction distribution +system.membus.trans_dist::ReadExReq 800030 # Transaction distribution +system.membus.trans_dist::ReadExResp 800030 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 365541.37 # Average gap between requests +system.physmem.avgMemAccLat 37274.24 # Average memory access latency per DRAM burst +system.physmem.avgQLat 18524.24 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 115.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.03 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrBW 59.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 59.06 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing +system.physmem.busUtil 1.37 # Data bus utilization in percentage +system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 44808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 116026399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116026399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 59056372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 116026399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 175082770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 59056372 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 59056372 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 1917061 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.528140 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.739842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.452866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1492586 77.86% 77.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305285 15.92% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52052 2.72% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21496 1.12% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13307 0.69% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7031 0.37% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5522 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4121 0.21% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15661 0.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1917061 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 131498944 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 131583104 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 84160 # Total number of bytes read from write queue +system.physmem.bytesWritten 66972672 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 66974592 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 50816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50816 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 131583104 # Number of bytes read from this memory +system.physmem.bytes_read::total 131583104 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 66974592 # Number of bytes written to this memory +system.physmem.bytes_written::total 66974592 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 321867794250 # Time in different power states +system.physmem.memoryStateTime::REF 37869260000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 774338779750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::cpu.inst 2055986 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055986 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046478 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046478 # Number of write requests responded to by this memory +system.physmem.pageHitRate 38.18 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 127958 # Per bank write bursts +system.physmem.perBankRdBursts::1 125105 # Per bank write bursts +system.physmem.perBankRdBursts::2 122165 # Per bank write bursts +system.physmem.perBankRdBursts::3 124186 # Per bank write bursts +system.physmem.perBankRdBursts::4 123280 # Per bank write bursts +system.physmem.perBankRdBursts::5 123449 # Per bank write bursts +system.physmem.perBankRdBursts::6 123880 # Per bank write bursts +system.physmem.perBankRdBursts::7 124388 # Per bank write bursts +system.physmem.perBankRdBursts::8 131994 # Per bank write bursts +system.physmem.perBankRdBursts::9 133987 # Per bank write bursts +system.physmem.perBankRdBursts::10 132463 # Per bank write bursts +system.physmem.perBankRdBursts::11 133769 # Per bank write bursts +system.physmem.perBankRdBursts::12 133910 # Per bank write bursts +system.physmem.perBankRdBursts::13 133839 # Per bank write bursts +system.physmem.perBankRdBursts::14 129945 # Per bank write bursts +system.physmem.perBankRdBursts::15 130353 # Per bank write bursts +system.physmem.perBankWrBursts::0 65810 # Per bank write bursts +system.physmem.perBankWrBursts::1 64091 # Per bank write bursts +system.physmem.perBankWrBursts::2 62337 # Per bank write bursts +system.physmem.perBankWrBursts::3 62824 # Per bank write bursts +system.physmem.perBankWrBursts::4 62831 # Per bank write bursts +system.physmem.perBankWrBursts::5 62991 # Per bank write bursts +system.physmem.perBankWrBursts::6 64303 # Per bank write bursts +system.physmem.perBankWrBursts::7 65302 # Per bank write bursts +system.physmem.perBankWrBursts::8 67082 # Per bank write bursts +system.physmem.perBankWrBursts::9 67591 # Per bank write bursts +system.physmem.perBankWrBursts::10 67285 # Per bank write bursts +system.physmem.perBankWrBursts::11 67661 # Per bank write bursts +system.physmem.perBankWrBursts::12 67090 # Per bank write bursts +system.physmem.perBankWrBursts::13 67416 # Per bank write bursts +system.physmem.perBankWrBursts::14 66182 # Per bank write bursts +system.physmem.perBankWrBursts::15 65652 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 60782 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.755668 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.633297 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60741 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60782 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 1924013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 130641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 2055986 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 2055986 # Read request sizes (log2) +system.physmem.readReqs 2055986 # Number of read requests accepted +system.physmem.readRowHitRate 37.77 # Row buffer hit rate for reads +system.physmem.readRowHits 776076 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 1315 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 10273355000 # Total ticks spent in databus transfers +system.physmem.totGap 1134078928500 # Total gap between requests +system.physmem.totMemAccLat 76586290250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 38061209000 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 60782 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.216413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.182090 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.086488 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 25426 41.83% 41.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1488 2.45% 44.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29643 48.77% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3806 6.26% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 363 0.60% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 0.08% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60782 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 33627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 1046478 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1046478 # Write request sizes (log2) +system.physmem.writeReqs 1046478 # Number of write requests accepted +system.physmem.writeRowHitRate 38.99 # Row buffer hit rate for writes +system.physmem.writeRowHits 407972 # Number of row buffer hits during writes +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- |