diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/long/se/60.bzip2/ref/arm/linux | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux')
6 files changed, 1439 insertions, 1402 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini index 9ef5c346e..7df53f247 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout index b6bf1e68a..b95f9cdb7 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:58:37 -gem5 executing on e108600-lin, pid 24092 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:43:01 +gem5 executing on e108600-lin, pid 17341 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second @@ -27,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1128033563500 because target called exit() +Exiting @ tick 1150225722500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index ddbab1eb8..16fb45e1d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.130744 # Number of seconds simulated -sim_ticks 1130744162500 # Number of ticks simulated -final_tick 1130744162500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.150226 # Number of seconds simulated +sim_ticks 1150225722500 # Number of ticks simulated +final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210155 # Simulator instruction rate (inst/s) -host_op_rate 226410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153850224 # Simulator tick rate (ticks/s) -host_mem_usage 274312 # Number of bytes of host memory used -host_seconds 7349.64 # Real time elapsed on the host +host_inst_rate 267770 # Simulator instruction rate (inst/s) +host_op_rate 288482 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 199406485 # Simulator tick rate (ticks/s) +host_mem_usage 271372 # Number of bytes of host memory used +host_seconds 5768.25 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132094976 # Number of bytes read from this memory -system.physmem.bytes_read::total 132145216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory +system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67850112 # Number of bytes written to this memory -system.physmem.bytes_written::total 67850112 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67849984 # Number of bytes written to this memory +system.physmem.bytes_written::total 67849984 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2063984 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2064769 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1060158 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1060158 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 44431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 116821276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116865707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 44431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60004831 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60004831 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60004831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 44431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 116821276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 176870538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2064769 # Number of read requests accepted -system.physmem.writeReqs 1060158 # Number of write requests accepted -system.physmem.readBursts 2064769 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1060158 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 132060352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue -system.physmem.bytesWritten 67848640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132145216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67850112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2063982 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2064767 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 114842544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 114886222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 58988408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58988408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 58988408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 114842544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 173874630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2064767 # Number of read requests accepted +system.physmem.writeReqs 1060156 # Number of write requests accepted +system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1060156 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 132061888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83200 # Total number of bytes read from write queue +system.physmem.bytesWritten 67848256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132145088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67849984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1300 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128520 # Per bank write bursts -system.physmem.perBankRdBursts::1 125806 # Per bank write bursts -system.physmem.perBankRdBursts::2 122672 # Per bank write bursts -system.physmem.perBankRdBursts::3 124571 # Per bank write bursts +system.physmem.perBankRdBursts::0 128524 # Per bank write bursts +system.physmem.perBankRdBursts::1 125801 # Per bank write bursts +system.physmem.perBankRdBursts::2 122666 # Per bank write bursts +system.physmem.perBankRdBursts::3 124575 # Per bank write bursts system.physmem.perBankRdBursts::4 123572 # Per bank write bursts -system.physmem.perBankRdBursts::5 123679 # Per bank write bursts -system.physmem.perBankRdBursts::6 124365 # Per bank write bursts -system.physmem.perBankRdBursts::7 124958 # Per bank write bursts -system.physmem.perBankRdBursts::8 132489 # Per bank write bursts -system.physmem.perBankRdBursts::9 134780 # Per bank write bursts -system.physmem.perBankRdBursts::10 133233 # Per bank write bursts -system.physmem.perBankRdBursts::11 134506 # Per bank write bursts -system.physmem.perBankRdBursts::12 134518 # Per bank write bursts -system.physmem.perBankRdBursts::13 134594 # Per bank write bursts -system.physmem.perBankRdBursts::14 130540 # Per bank write bursts -system.physmem.perBankRdBursts::15 130640 # Per bank write bursts +system.physmem.perBankRdBursts::5 123680 # Per bank write bursts +system.physmem.perBankRdBursts::6 124357 # Per bank write bursts +system.physmem.perBankRdBursts::7 124965 # Per bank write bursts +system.physmem.perBankRdBursts::8 132488 # Per bank write bursts +system.physmem.perBankRdBursts::9 134781 # Per bank write bursts +system.physmem.perBankRdBursts::10 133246 # Per bank write bursts +system.physmem.perBankRdBursts::11 134508 # Per bank write bursts +system.physmem.perBankRdBursts::12 134524 # Per bank write bursts +system.physmem.perBankRdBursts::13 134597 # Per bank write bursts +system.physmem.perBankRdBursts::14 130537 # Per bank write bursts +system.physmem.perBankRdBursts::15 130646 # Per bank write bursts system.physmem.perBankWrBursts::0 66781 # Per bank write bursts -system.physmem.perBankWrBursts::1 64941 # Per bank write bursts +system.physmem.perBankWrBursts::1 64940 # Per bank write bursts system.physmem.perBankWrBursts::2 63173 # Per bank write bursts system.physmem.perBankWrBursts::3 63584 # Per bank write bursts system.physmem.perBankWrBursts::4 63558 # Per bank write bursts system.physmem.perBankWrBursts::5 63644 # Per bank write bursts system.physmem.perBankWrBursts::6 65047 # Per bank write bursts -system.physmem.perBankWrBursts::7 66055 # Per bank write bursts -system.physmem.perBankWrBursts::8 67972 # Per bank write bursts -system.physmem.perBankWrBursts::9 68438 # Per bank write bursts -system.physmem.perBankWrBursts::10 68161 # Per bank write bursts -system.physmem.perBankWrBursts::11 68586 # Per bank write bursts -system.physmem.perBankWrBursts::12 68040 # Per bank write bursts -system.physmem.perBankWrBursts::13 68530 # Per bank write bursts +system.physmem.perBankWrBursts::7 66059 # Per bank write bursts +system.physmem.perBankWrBursts::8 67975 # Per bank write bursts +system.physmem.perBankWrBursts::9 68435 # Per bank write bursts +system.physmem.perBankWrBursts::10 68155 # Per bank write bursts +system.physmem.perBankWrBursts::11 68585 # Per bank write bursts +system.physmem.perBankWrBursts::12 68036 # Per bank write bursts +system.physmem.perBankWrBursts::13 68532 # Per bank write bursts system.physmem.perBankWrBursts::14 67159 # Per bank write bursts system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1130744067500 # Total gap between requests +system.physmem.totGap 1150225621500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2064769 # Read request sizes (log2) +system.physmem.readPktSize::6 2064767 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1060158 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1931837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131592 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1060156 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1919491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143962 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 62386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 62444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,103 +194,114 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1925169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.839212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.850367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 126.421931 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1496084 77.71% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 309482 16.08% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52255 2.71% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20716 1.08% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12793 0.66% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7748 0.40% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5753 0.30% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5054 0.26% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15284 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1925169 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.244314 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.928422 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 148.698604 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61952 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1927680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.704050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.827428 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.877785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1497957 77.71% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 310202 16.09% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52219 2.71% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20801 1.08% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13076 0.68% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7806 0.40% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5210 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5119 0.27% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15290 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1927680 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.137773 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.854622 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 150.738788 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62143 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61990 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.101710 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.070337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.034747 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 28322 45.69% 45.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1015 1.64% 47.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 30732 49.58% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1873 3.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 43 0.07% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61990 # Writes before turning the bus around for reads -system.physmem.totQLat 38536102500 # Total ticks spent queuing -system.physmem.totMemAccLat 77225658750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10317215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18675.63 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 62182 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62182 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.048808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.017651 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.031288 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29885 48.06% 48.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1078 1.73% 49.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29552 47.53% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1636 2.63% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62182 # Writes before turning the bus around for reads +system.physmem.totQLat 59945214750 # Total ticks spent queuing +system.physmem.totMemAccLat 98635221000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29050.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37425.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.87 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.00 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47800.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 58.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.38 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.36 # Data bus utilization in percentage +system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing -system.physmem.readRowHits 775929 # Number of row buffer hits during reads -system.physmem.writeRowHits 422476 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.85 # Row buffer hit rate for writes -system.physmem.avgGap 361846.55 # Average gap between requests -system.physmem.pageHitRate 38.37 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7091695800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3869476875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7785421800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3348753840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 423921506085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 306584736000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 826456199280 # Total energy per rank (pJ) -system.physmem_0.averagePower 730.896688 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 507283799000 # Time in different power states -system.physmem_0.memoryStateTime::REF 37757980000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 585701078500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7462581840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4071845250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8309316600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3520920960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 432965070225 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 298651785000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 828836128755 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.001436 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 494051909000 # Time in different power states -system.physmem_1.memoryStateTime::REF 37757980000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 598934101500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019432 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610009 # Number of conditional branches predicted +system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing +system.physmem.readRowHits 775403 # Number of row buffer hits during reads +system.physmem.writeRowHits 420503 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes +system.physmem.avgGap 368081.27 # Average gap between requests +system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6704024460 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3563246940 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 71584047600.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47598370410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2598119520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 242886973860 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71929585440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 82360762695 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 539073775965 # Total energy per rank (pJ) +system.physmem_0.averagePower 468.667814 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1039023905500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3501879500 # Time in different power states +system.physmem_0.memoryStateTime::REF 30346756000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 319059811750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 187317352250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77352878250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 532647044750 # Time in different power states +system.physmem_1.actEnergy 7059682140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3752298660 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 71064062160.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47576528010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2430223200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 248601681570 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68458810560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 80907988260 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 540316908180 # Total energy per rank (pJ) +system.physmem_1.averagePower 469.748583 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1039511813000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3059644000 # Time in different power states +system.physmem_1.memoryStateTime::REF 30118792000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 316054273750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178278810500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77535412750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 545178789500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240019882 # Number of BP lookups +system.cpu.branchPred.condPredicted 186610383 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131647101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324380 # Number of BTB hits +system.cpu.branchPred.BTBLookups 131646647 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122324605 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.918400 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.918891 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. @@ -298,7 +309,7 @@ system.cpu.branchPred.indirectHits 232 # Nu system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -328,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,7 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,16 +430,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2261488325 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2300451445 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363718 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41363683 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.464161 # CPI: cycles per instruction -system.cpu.ipc 0.682985 # IPC: instructions per cycle +system.cpu.cpi 1.489387 # CPI: cycles per instruction +system.cpu.ipc 0.671417 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -464,61 +475,61 @@ system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1844743027 # Number of cycles that the object actually ticked -system.cpu.idleCycles 416745298 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220102 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.712457 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624495296 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224198 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.701853 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9823555500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.712457 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997488 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997488 # Average percentage of cache occupancy +system.cpu.tickCycles 1845014986 # Number of cycles that the object actually ticked +system.cpu.idleCycles 455436459 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220107 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.805290 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624493165 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805290 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391740 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391740 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454164183 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454164183 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170330990 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170330990 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277391151 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277391151 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454163885 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454163885 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170329157 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170329157 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624495173 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624495173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624495174 # number of overall hits -system.cpu.dcache.overall_hits::total 624495174 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333416 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333416 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2255057 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2255057 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624493042 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624493042 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624493043 # number of overall hits +system.cpu.dcache.overall_hits::total 624493043 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2256890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2256890 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9588473 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9588473 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9588475 # number of overall misses -system.cpu.dcache.overall_misses::total 9588475 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192638967000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192638967000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 111261397000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 111261397000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 303900364000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 303900364000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 303900364000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 303900364000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497599 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9590307 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9590307 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590309 # number of overall misses +system.cpu.dcache.overall_misses::total 9590309 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 208195707500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119902321500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 328098029000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328098029000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 328098029000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328098029000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461497302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461497302 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -527,64 +538,64 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083646 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083646 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083649 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083649 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634083349 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634083349 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634083352 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634083352 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015122 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015122 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26268.653926 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26268.653926 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49338.618492 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49338.618492 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31694.344240 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31694.344240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31694.337629 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31694.337629 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34211.420865 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34211.413730 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3670051 # number of writebacks -system.cpu.dcache.writebacks::total 3670051 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3670055 # number of writebacks +system.cpu.dcache.writebacks::total 3670055 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364227 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364227 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364276 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364276 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364276 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364276 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333367 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333367 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366056 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 366056 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366105 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366105 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366105 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366105 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890834 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224197 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224197 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224198 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224198 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 185303496000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 185303496000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86626211500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86626211500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 271929707500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 271929707500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 271929782500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 271929782500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92466638500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92466638500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 293324557500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 293324638500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -595,70 +606,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25268.542540 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25268.542540 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45813.855027 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45813.855027 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29480.041189 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29480.041189 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29480.046124 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29480.046124 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 33 # number of replacements -system.cpu.icache.tags.tagsinuse 660.343836 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466264831 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.478132 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466274661 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567232.154501 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567244.113139 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.343836 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322434 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322434 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 660.478132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932532128 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932532128 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466264831 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466264831 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466264831 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466264831 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466264831 # number of overall hits -system.cpu.icache.overall_hits::total 466264831 # number of overall hits +system.cpu.icache.tags.tag_accesses 932551788 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932551788 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466274661 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466274661 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466274661 # number of demand (read+write) hits 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system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954988 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170681 # miss rate for ReadSharedReq accesses @@ -783,26 +794,26 @@ system.cpu.l2cache.demand_miss_rate::total 0.223823 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89177.093746 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89177.093746 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77071.337580 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77071.337580 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88236.430485 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88236.430485 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77071.337580 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88606.647077 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 88602.261505 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77071.337580 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88606.647077 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 88602.261505 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1060158 # number of writebacks -system.cpu.l2cache.writebacks::total 1060158 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1060156 # number of writebacks +system.cpu.l2cache.writebacks::total 1060156 # number of writebacks system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits @@ -811,128 +822,128 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 6 system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812324 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 812324 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812323 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 812323 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251660 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251660 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251659 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251659 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2063984 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2064769 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2063982 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2064767 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2063984 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2064769 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64317453500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64317453500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52651000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52651000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 97925523500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 97925523500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52651000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162242977000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 162295628000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52651000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162242977000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 162295628000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159329500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159329500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429612 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429611 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.223823 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.223823 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79177.093746 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79177.093746 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67071.337580 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67071.337580 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78236.520701 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78236.520701 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445155 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220147 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1445 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4730209 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890834 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333369 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670175 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668513 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670190 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825231936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 825286656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2032337 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67850112 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11257357 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.016509 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825232512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 825287232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2032334 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67849984 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11257359 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11254306 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3045 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11254309 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11257357 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12892661500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11257359 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12892670500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836299994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836307494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4095876 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2031264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 4095872 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2031262 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1252445 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1060158 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1252444 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution system.membus.trans_dist::CleanEvict 970949 # Transaction distribution -system.membus.trans_dist::ReadExReq 812324 # Transaction distribution -system.membus.trans_dist::ReadExResp 812324 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1252445 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6160645 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 199995328 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 812323 # Transaction distribution +system.membus.trans_dist::ReadExResp 812323 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1252444 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160639 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6160639 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 199995072 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2064769 # Request fanout histogram +system.membus.snoop_fanout::samples 2064767 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2064769 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2064767 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2064769 # Request fanout histogram -system.membus.reqLayer0.occupancy 8803577000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2064767 # Request fanout histogram +system.membus.reqLayer0.occupancy 8804910500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11289358000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11285155750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 8b8fd1b4f..5a7d7b1a5 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 00cbc440d..fbc8b4e01 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12200 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:48:52 +gem5 executing on e108600-lin, pid 17438 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -27,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 767803843500 because target called exit() +Exiting @ tick 787742202500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 4f03996ba..ea5c16164 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.770752 # Number of seconds simulated -sim_ticks 770752376500 # Number of ticks simulated -final_tick 770752376500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.787742 # Number of seconds simulated +sim_ticks 787742202500 # Number of ticks simulated +final_tick 787742202500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147248 # Simulator instruction rate (inst/s) -host_op_rate 158637 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73478006 # Simulator tick rate (ticks/s) -host_mem_usage 329736 # Number of bytes of host memory used -host_seconds 10489.57 # Real time elapsed on the host +host_inst_rate 201500 # Simulator instruction rate (inst/s) +host_op_rate 217086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 102767126 # Simulator tick rate (ticks/s) +host_mem_usage 327820 # Number of bytes of host memory used +host_seconds 7665.31 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 65664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 236002624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63781504 # Number of bytes read from this memory -system.physmem.bytes_read::total 299849792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 236035776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63780672 # Number of bytes read from this memory +system.physmem.bytes_read::total 299882112 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 65664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 65664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104607936 # Number of bytes written to this memory -system.physmem.bytes_written::total 104607936 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 104579136 # Number of bytes written to this memory +system.physmem.bytes_written::total 104579136 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3687541 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 996586 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4685153 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634499 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634499 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 85195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306197725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82752264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389035183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 85195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 135721847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 135721847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 135721847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 85195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306197725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82752264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 524757030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4685154 # Number of read requests accepted -system.physmem.writeReqs 1634499 # Number of write requests accepted -system.physmem.readBursts 4685154 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634499 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 299347712 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 502144 # Total number of bytes read from write queue -system.physmem.bytesWritten 104604544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299849856 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104607936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7846 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one +system.physmem.num_reads::cpu.data 3688059 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 996573 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4685658 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634049 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634049 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 83357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 299635814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 80966428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380685599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 83357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 83357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 132758072 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 132758072 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 132758072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 83357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 299635814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 80966428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 513443671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4685658 # Number of read requests accepted +system.physmem.writeReqs 1634049 # Number of write requests accepted +system.physmem.readBursts 4685658 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634049 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 299378880 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 503232 # Total number of bytes read from write queue +system.physmem.bytesWritten 104576512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299882112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104579136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7863 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 17 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301314 # Per bank write bursts -system.physmem.perBankRdBursts::1 301808 # Per bank write bursts -system.physmem.perBankRdBursts::2 285079 # Per bank write bursts -system.physmem.perBankRdBursts::3 287721 # Per bank write bursts -system.physmem.perBankRdBursts::4 288732 # Per bank write bursts -system.physmem.perBankRdBursts::5 286480 # Per bank write bursts -system.physmem.perBankRdBursts::6 281880 # Per bank write bursts -system.physmem.perBankRdBursts::7 278193 # Per bank write bursts -system.physmem.perBankRdBursts::8 293719 # Per bank write bursts -system.physmem.perBankRdBursts::9 299847 # Per bank write bursts -system.physmem.perBankRdBursts::10 291529 # Per bank write bursts -system.physmem.perBankRdBursts::11 297903 # Per bank write bursts -system.physmem.perBankRdBursts::12 299405 # Per bank write bursts -system.physmem.perBankRdBursts::13 299387 # Per bank write bursts -system.physmem.perBankRdBursts::14 294305 # Per bank write bursts -system.physmem.perBankRdBursts::15 290006 # Per bank write bursts -system.physmem.perBankWrBursts::0 103629 # Per bank write bursts -system.physmem.perBankWrBursts::1 101748 # Per bank write bursts -system.physmem.perBankWrBursts::2 99222 # Per bank write bursts -system.physmem.perBankWrBursts::3 99944 # Per bank write bursts -system.physmem.perBankWrBursts::4 98990 # Per bank write bursts -system.physmem.perBankWrBursts::5 98822 # Per bank write bursts -system.physmem.perBankWrBursts::6 102440 # Per bank write bursts -system.physmem.perBankWrBursts::7 104048 # Per bank write bursts -system.physmem.perBankWrBursts::8 105134 # Per bank write bursts -system.physmem.perBankWrBursts::9 103994 # Per bank write bursts -system.physmem.perBankWrBursts::10 101818 # Per bank write bursts -system.physmem.perBankWrBursts::11 102570 # Per bank write bursts -system.physmem.perBankWrBursts::12 102850 # Per bank write bursts -system.physmem.perBankWrBursts::13 102376 # Per bank write bursts -system.physmem.perBankWrBursts::14 104237 # Per bank write bursts -system.physmem.perBankWrBursts::15 102624 # Per bank write bursts +system.physmem.perBankRdBursts::0 301431 # Per bank write bursts +system.physmem.perBankRdBursts::1 301123 # Per bank write bursts +system.physmem.perBankRdBursts::2 285299 # Per bank write bursts +system.physmem.perBankRdBursts::3 287676 # Per bank write bursts +system.physmem.perBankRdBursts::4 288751 # Per bank write bursts +system.physmem.perBankRdBursts::5 286469 # Per bank write bursts +system.physmem.perBankRdBursts::6 281133 # Per bank write bursts +system.physmem.perBankRdBursts::7 278330 # Per bank write bursts +system.physmem.perBankRdBursts::8 294107 # Per bank write bursts +system.physmem.perBankRdBursts::9 299584 # Per bank write bursts +system.physmem.perBankRdBursts::10 292343 # Per bank write bursts +system.physmem.perBankRdBursts::11 297976 # Per bank write bursts +system.physmem.perBankRdBursts::12 299704 # Per bank write bursts +system.physmem.perBankRdBursts::13 299189 # Per bank write bursts +system.physmem.perBankRdBursts::14 294388 # Per bank write bursts +system.physmem.perBankRdBursts::15 290292 # Per bank write bursts +system.physmem.perBankWrBursts::0 103694 # Per bank write bursts +system.physmem.perBankWrBursts::1 101682 # Per bank write bursts +system.physmem.perBankWrBursts::2 99052 # Per bank write bursts +system.physmem.perBankWrBursts::3 99844 # Per bank write bursts +system.physmem.perBankWrBursts::4 99095 # Per bank write bursts +system.physmem.perBankWrBursts::5 98699 # Per bank write bursts +system.physmem.perBankWrBursts::6 102473 # Per bank write bursts +system.physmem.perBankWrBursts::7 104090 # Per bank write bursts +system.physmem.perBankWrBursts::8 105068 # Per bank write bursts +system.physmem.perBankWrBursts::9 104102 # Per bank write bursts +system.physmem.perBankWrBursts::10 101990 # Per bank write bursts +system.physmem.perBankWrBursts::11 102510 # Per bank write bursts +system.physmem.perBankWrBursts::12 102612 # Per bank write bursts +system.physmem.perBankWrBursts::13 102296 # Per bank write bursts +system.physmem.perBankWrBursts::14 104281 # Per bank write bursts +system.physmem.perBankWrBursts::15 102520 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 770752366000 # Total gap between requests +system.physmem.totGap 787742161500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4685154 # Read request sizes (log2) +system.physmem.readPktSize::6 4685658 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634499 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2776424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1031022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 327510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 229431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 146630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 80164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634049 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2727854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1051064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 327817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 158136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 89940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,40 +149,40 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 100116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 110766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 100949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req 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activation -system.physmem.bytesPerActivate::0-127 3394354 79.77% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 663703 15.60% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94226 2.21% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35436 0.83% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22765 0.53% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12171 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7342 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19831 0.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4255173 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97794 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.827914 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.473591 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 93707 95.82% 95.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1671 1.71% 97.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 768 0.79% 98.31% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 406 0.42% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 365 0.37% 99.10% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 337 0.34% 99.45% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 234 0.24% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 165 0.17% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 89 0.09% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 24 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 12 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1664-1791 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3968-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97794 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97794 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.713152 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.671812 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.223073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68724 70.27% 70.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1896 1.94% 72.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18671 19.09% 91.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5634 5.76% 97.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1729 1.77% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 613 0.63% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 266 0.27% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 147 0.15% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 67 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 30 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97794 # Writes before turning the bus around for reads -system.physmem.totQLat 128325813562 # Total ticks spent queuing -system.physmem.totMemAccLat 216025338562 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23386540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27435.83 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4258602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.856263 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.818587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.740363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3399214 79.82% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 662534 15.56% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94110 2.21% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35203 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22640 0.53% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12473 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7407 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5223 0.12% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19798 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4258602 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97968 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.747867 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.462080 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95523 97.50% 97.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1197 1.22% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 705 0.72% 99.45% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 407 0.42% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 106 0.11% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 17 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97968 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97968 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.678997 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.638691 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.208217 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 70313 71.77% 71.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1920 1.96% 73.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 17565 17.93% 91.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5314 5.42% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1711 1.75% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 637 0.65% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 262 0.27% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 130 0.13% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 63 0.06% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 33 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 13 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97968 # Writes before turning the bus around for reads +system.physmem.totQLat 162666982970 # Total ticks spent queuing +system.physmem.totMemAccLat 250375639220 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23388975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34774.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46185.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 135.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.04 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 135.72 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53524.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 132.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.69 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.09 # Data bus utilization in percentage -system.physmem.busUtilRead 3.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing -system.physmem.readRowHits 1715091 # Number of row buffer hits during reads -system.physmem.writeRowHits 341475 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 20.89 # Row buffer hit rate for writes -system.physmem.avgGap 121961.18 # Average gap between requests -system.physmem.pageHitRate 32.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15989112720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8724218250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18025846800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5241069360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 417928675995 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 95843265750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 612093526155 # Total energy per rank (pJ) -system.physmem_0.averagePower 794.157652 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 156909498029 # Time in different power states -system.physmem_0.memoryStateTime::REF 25736880000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 588099785971 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16179556680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8828131125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18455494200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5349602880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 412908393870 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100247038500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 612309554535 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.437909 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 164276600328 # Time in different power states -system.physmem_1.memoryStateTime::REF 25736880000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 580733308672 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286275195 # Number of BP lookups -system.cpu.branchPred.condPredicted 223398341 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14628424 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157667483 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150349199 # Number of BTB hits +system.physmem.busUtil 4.01 # Data bus utilization in percentage +system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing +system.physmem.readRowHits 1712898 # Number of row buffer hits during reads +system.physmem.writeRowHits 340301 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 20.83 # Row buffer hit rate for writes +system.physmem.avgGap 124648.53 # Average gap between requests +system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15106540680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8029309200 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16494913680 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4221043380 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 59407414560.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64582002630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1606944480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 223006056720 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 35875852320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 16122239730 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 444464207160 # Total energy per rank (pJ) +system.physmem_0.averagePower 564.225454 # Core power per rank (mW) +system.physmem_0.totalIdleTime 641904162368 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1401750889 # Time in different power states +system.physmem_0.memoryStateTime::REF 25151370000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 59428702250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 93425472309 # Time in different power states +system.physmem_0.memoryStateTime::ACT 119284909993 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 489049997059 # Time in different power states +system.physmem_1.actEnergy 15299891880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8132085390 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 16904542620 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4308478380 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 58934141760.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64765265610 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1612336320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 219700492200 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 35552759520 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18091245240 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 443312102310 # Total energy per rank (pJ) +system.physmem_1.averagePower 562.762917 # Core power per rank (mW) +system.physmem_1.totalIdleTime 641480248383 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1450220904 # Time in different power states +system.physmem_1.memoryStateTime::REF 24952394000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67105561000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 92583809905 # Time in different power states +system.physmem_1.memoryStateTime::ACT 119858377963 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 481791838728 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 286283098 # Number of BP lookups +system.cpu.branchPred.condPredicted 223408244 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630421 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158004936 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150354998 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.358406 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16643020 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3069 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1906 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1163 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 137 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.158418 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16643073 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3065 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1898 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1167 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 134 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,7 +354,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,7 +384,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -411,7 +414,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -442,129 +445,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1541504754 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1575484406 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13925502 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067484101 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286275195 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166994125 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1512857238 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29281631 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 279 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1018 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656940019 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 946 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1541424852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.436951 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229037 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13928690 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067537239 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286283098 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166999969 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1546809233 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29285745 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 303 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 986 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656964714 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1575382084 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.406011 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.233492 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 459011037 29.78% 29.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465435057 30.20% 59.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101419068 6.58% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515559690 33.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 492942163 31.29% 31.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465443083 29.54% 60.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101428647 6.44% 67.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515568191 32.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1541424852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185712 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.341212 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74709451 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 544021839 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849845592 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58207832 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14640138 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42201657 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 726 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037180089 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52484609 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14640138 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139806563 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 462600801 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15884 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837785307 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86576159 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976384850 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26739549 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45323653 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126929 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1602638 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25499860 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985860548 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128169124 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432875929 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1575382084 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.181711 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.312318 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74686824 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 577980395 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849907031 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58165638 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642196 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42200734 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 724 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037196735 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52499519 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642196 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139768268 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 492678513 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15538 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837819054 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 90458515 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976393108 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26740093 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45400307 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126273 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1723349 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 29315109 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985867653 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128208959 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432891999 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 131 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310961603 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 175 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111534180 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542566077 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199303375 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26892889 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29237160 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947969517 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857492369 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13496690 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283937332 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647289356 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1541424852 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.205049 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150817 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310968708 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 177 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 176 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111448171 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542564068 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199306440 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26831952 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28868587 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947979256 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 230 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857513748 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13517148 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283947070 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647252748 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1575382084 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.179088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151868 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 588435916 38.17% 38.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326131475 21.16% 59.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378210554 24.54% 83.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219654013 14.25% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28986723 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6171 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 622503864 39.51% 39.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326012726 20.69% 60.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378121823 24.00% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219723484 13.95% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29014011 1.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1541424852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1575382084 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166021321 40.99% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1993 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191489776 47.28% 88.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47539480 11.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166098751 40.96% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2024 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191460462 47.22% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47920671 11.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138243662 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800931 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138250302 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801028 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -592,82 +595,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532135699 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186312026 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532139540 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186322827 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857492369 # Type of FU issued -system.cpu.iq.rate 1.204986 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405052570 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218064 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5674958613 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231919871 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805704142 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 1857513748 # Type of FU issued +system.cpu.iq.rate 1.179011 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405481908 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218293 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5709408399 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231939413 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805717250 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262544806 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262995523 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17811536 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 17822173 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84259743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66618 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13244 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24456330 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84257734 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66715 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13309 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24459395 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4512030 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4891489 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4550351 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4849996 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14640138 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25364964 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1346928 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947969899 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14642196 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25436916 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1454941 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947979633 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542566077 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199303375 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159350 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1186169 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13244 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7699482 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8703162 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16402644 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827831567 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516957415 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29660802 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542564068 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199306440 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 168 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1294449 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13309 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700831 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8703764 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16404595 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827842620 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516961097 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29671128 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151 # number of nop insts executed -system.cpu.iew.exec_refs 698708795 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542425 # Number of branches executed -system.cpu.iew.exec_stores 181751380 # Number of stores executed -system.cpu.iew.exec_rate 1.185745 # Inst execution rate -system.cpu.iew.wb_sent 1808736265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805704212 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169174812 # num instructions producing a value -system.cpu.iew.wb_consumers 1689572222 # num instructions consuming a value -system.cpu.iew.wb_rate 1.171391 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258041892 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 147 # number of nop insts executed +system.cpu.iew.exec_refs 698716504 # number of memory reference insts executed +system.cpu.iew.exec_branches 229543654 # Number of branches executed +system.cpu.iew.exec_stores 181755407 # Number of stores executed +system.cpu.iew.exec_rate 1.160178 # Inst execution rate +system.cpu.iew.wb_sent 1808745333 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805717319 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169202335 # num instructions producing a value +system.cpu.iew.wb_consumers 1689603795 # num instructions consuming a value +system.cpu.iew.wb_rate 1.146135 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691998 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258049766 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14627747 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1501940299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.107922 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.025263 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14629745 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1535892995 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.083430 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.009496 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 921653315 61.36% 61.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250636600 16.69% 78.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110060462 7.33% 85.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55269176 3.68% 89.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29319156 1.95% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34080655 2.27% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24723288 1.65% 94.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18133421 1.21% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58064226 3.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 955612705 62.22% 62.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250634240 16.32% 78.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110090472 7.17% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55300497 3.60% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29246766 1.90% 91.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34056030 2.22% 93.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24731317 1.61% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18107101 1.18% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58113867 3.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1501940299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1535892995 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -713,78 +716,78 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58064226 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3365949800 # The number of ROB reads -system.cpu.rob.rob_writes 3883638365 # The number of ROB writes -system.cpu.timesIdled 837 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 79902 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58113867 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3399860729 # The number of ROB reads +system.cpu.rob.rob_writes 3883658641 # The number of ROB writes +system.cpu.timesIdled 841 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 102322 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.998020 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.998020 # CPI: Total CPI of All Threads -system.cpu.ipc 1.001984 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.001984 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175818987 # number of integer regfile reads -system.cpu.int_regfile_writes 1261576435 # number of integer regfile writes -system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 52 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965775009 # number of cc regfile reads -system.cpu.cc_regfile_writes 551856674 # number of cc regfile writes -system.cpu.misc_regfile_reads 675846934 # number of misc regfile reads +system.cpu.cpi 1.020020 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.020020 # CPI: Total CPI of All Threads +system.cpu.ipc 0.980373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.980373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175838440 # number of integer regfile reads +system.cpu.int_regfile_writes 1261579513 # number of integer regfile writes +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965813253 # number of cc regfile reads +system.cpu.cc_regfile_writes 551861987 # number of cc regfile writes +system.cpu.misc_regfile_reads 675852638 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17003150 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964340 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638065664 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17003662 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 79206500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964340 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 17003360 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.963277 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638058665 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17003872 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.524316 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 83293500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.963277 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999928 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999928 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 406 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335709608 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335709608 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469347574 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469347574 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168717937 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168717937 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335696042 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335696042 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 469342719 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469342719 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168715791 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168715791 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638065511 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638065511 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638065511 # number of overall hits -system.cpu.dcache.overall_hits::total 638065511 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17419228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17419228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3868110 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3868110 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638058510 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638058510 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638058510 # number of overall hits +system.cpu.dcache.overall_hits::total 638058510 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17417195 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17417195 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3870256 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3870256 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses 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(read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 566676521757 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 566676521757 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 566676521757 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486766802 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486766802 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21287451 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21287451 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21287453 # number of overall misses +system.cpu.dcache.overall_misses::total 21287453 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 440618340000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 440618340000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157333375444 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157333375444 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 245500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 597951715444 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 597951715444 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 597951715444 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 597951715444 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486759914 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486759914 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -793,470 +796,475 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659352849 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659352849 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659352851 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659352851 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022413 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022413 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659345961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659345961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659345963 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659345963 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035782 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035782 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022425 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022425 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032285 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032285 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032285 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032285 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23905.963887 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23905.963887 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38844.057242 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38844.057242 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49875 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49875 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26620.356277 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26620.356277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26620.353776 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26620.353776 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20685246 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3452781 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 946049 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67233 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.864878 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51.355450 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17003150 # number of writebacks -system.cpu.dcache.writebacks::total 17003150 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3153076 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3153076 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130592 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1130592 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25297.893260 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25297.893260 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40651.929858 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40651.929858 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 61375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 61375 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28089.399499 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28089.399499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28089.396859 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28089.396859 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21254267 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3791320 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 940376 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67438 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.601882 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.219342 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 17003360 # number of writebacks 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number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266152 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737518 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737518 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4283573 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4283573 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4283573 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4283573 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266317 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266317 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737561 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737561 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17003670 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17003670 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17003671 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17003671 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335207977500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 335207977500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116679674033 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116679674033 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451887651533 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 451887651533 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451887720533 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 451887720533 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 17003878 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17003878 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17003879 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17003879 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354302060000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 354302060000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121168074300 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 121168074300 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475470134300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 475470134300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475470209300 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 475470209300 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025788 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025788 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23496.733913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23496.733913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42622.431718 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42622.431718 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26575.889295 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26575.889295 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26575.891790 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26575.891790 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 588 # number of replacements -system.cpu.icache.tags.tagsinuse 444.874436 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656938405 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 611674.492551 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses 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average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27962.452700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27962.455467 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27962.455467 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 589 # number of replacements +system.cpu.icache.tags.tagsinuse 445.623702 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656963104 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 610560.505576 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 444.874436 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.868895 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.868895 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 445.623702 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.870359 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.870359 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 487 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 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79208.635572 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 79208.635572 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 79208.635572 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 21110 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 318 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 109.378238 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 35.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 589 # number of writebacks +system.cpu.icache.writebacks::total 589 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 531 # number of ReadReq MSHR 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Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 11610963 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11639700 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 19388 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4655505 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 4647068 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15866.736257 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13267029 # Total number of references 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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356810 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356810 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954461 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189922 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189922 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216837 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356978 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356978 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.952646 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189920 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189920 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216816 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216863 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216816 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.287303 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61104.298554 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96035.613700 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96035.613700 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66553.554041 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66553.554041 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80654.828088 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80654.828088 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84725.402270 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78931.951042 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34008488 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003756 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 201663 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 201662 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.287278 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70298.609693 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15214.285714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15214.285714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100575.793669 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100575.793669 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82436.647173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82436.647173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.448609 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.448609 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82436.647173 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91064.167743 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91061.767405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82436.647173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91064.167743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85972.521147 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34008905 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003965 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 200821 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200820 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14267181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6469733 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12168504 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3012569 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1490485 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 14267344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6459789 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12178209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3013479 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1493524 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737555 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737555 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266107 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2738 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51010503 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51013241 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176436672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176543040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6137564 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104608640 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 23142303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009630 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097659 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266268 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011129 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51013871 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176463552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176570112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6141063 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104579840 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 23146008 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009594 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097477 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22919446 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 222856 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22923954 99.04% 99.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 222053 0.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23142303 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34007983525 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 16538 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23146008 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34008401540 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 16551 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1611000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1614499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25505500994 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 9332231 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 4668264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 25505814993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 9333193 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 4668760 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3708204 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634499 # Transaction distribution -system.membus.trans_dist::CleanEvict 3012569 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 976948 # Transaction distribution -system.membus.trans_dist::ReadExResp 976948 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3708206 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14017383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14017383 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404457664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 404457664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3708223 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634049 # Transaction distribution +system.membus.trans_dist::CleanEvict 3013479 # Transaction distribution +system.membus.trans_dist::UpgradeReq 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 977434 # Transaction distribution +system.membus.trans_dist::ReadExResp 977434 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3708224 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14018850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14018850 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404461184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 404461184 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4685163 # Request fanout histogram +system.membus.snoop_fanout::samples 4685665 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4685163 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4685665 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4685163 # Request fanout histogram -system.membus.reqLayer0.occupancy 17662405597 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25476549560 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.3 # Layer utilization (%) +system.membus.snoop_fanout::total 4685665 # Request fanout histogram +system.membus.reqLayer0.occupancy 17659262741 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 25448696800 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |