diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
| commit | cfb805cc71bd1c4b72691b69faa879663e548c11 (patch) | |
| tree | 4ef4be8b34eb3722e303546a96956b1adaa3315b /tests/long/se/60.bzip2/ref/arm/linux | |
| parent | 612f8f074fa1099cf70faf495d46cc647762a031 (diff) | |
| download | gem5-cfb805cc71bd1c4b72691b69faa879663e548c11.tar.xz | |
stats: update stats for ARMv8 changes
Diffstat (limited to 'tests/long/se/60.bzip2/ref/arm/linux')
9 files changed, 1164 insertions, 836 deletions
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index c32ff375e..56ff7911f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index aa09d1777..c3788cdfe 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:27:54 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:05:55 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5017340 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data @@ -24,4 +25,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 533797009000 because target called exit() +Exiting @ tick 533761922000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 5e5db11e7..8c6f8359f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.533797 # Number of seconds simulated -sim_ticks 533797009000 # Number of ticks simulated -final_tick 533797009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.533762 # Number of seconds simulated +sim_ticks 533761922000 # Number of ticks simulated +final_tick 533761922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163502 # Simulator instruction rate (inst/s) -host_op_rate 182399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56505895 # Simulator tick rate (ticks/s) -host_mem_usage 249880 # Number of bytes of host memory used -host_seconds 9446.75 # Real time elapsed on the host +host_inst_rate 155948 # Simulator instruction rate (inst/s) +host_op_rate 173972 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53891847 # Simulator tick rate (ticks/s) +host_mem_usage 269768 # Number of bytes of host memory used +host_seconds 9904.32 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 47680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143743296 # Number of bytes read from this memory -system.physmem.bytes_read::total 143790976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70431872 # Number of bytes written to this memory -system.physmem.bytes_written::total 70431872 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246734 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100498 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100498 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 269284566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 269373889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 131945048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 131945048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 131945048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 269284566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401318937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246734 # Number of read requests accepted -system.physmem.writeReqs 1100498 # Number of write requests accepted -system.physmem.readBursts 2246734 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100498 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143754112 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36864 # Total number of bytes read from write queue -system.physmem.bytesWritten 70430784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143790976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70431872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143740736 # Number of bytes read from this memory +system.physmem.bytes_read::total 143788352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70437056 # Number of bytes written to this memory +system.physmem.bytes_written::total 70437056 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245949 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246693 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100579 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100579 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 269297472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 269386680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 131963434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 131963434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 131963434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 269297472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401350114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246694 # Number of read requests accepted +system.physmem.writeReqs 1100579 # Number of write requests accepted +system.physmem.readBursts 2246694 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100579 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143750848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37568 # Total number of bytes read from write queue +system.physmem.bytesWritten 70435904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143788416 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70437056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 587 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139750 # Per bank write bursts -system.physmem.perBankRdBursts::1 136273 # Per bank write bursts -system.physmem.perBankRdBursts::2 133708 # Per bank write bursts -system.physmem.perBankRdBursts::3 136246 # Per bank write bursts -system.physmem.perBankRdBursts::4 134906 # Per bank write bursts -system.physmem.perBankRdBursts::5 135253 # Per bank write bursts -system.physmem.perBankRdBursts::6 136175 # Per bank write bursts -system.physmem.perBankRdBursts::7 136295 # Per bank write bursts -system.physmem.perBankRdBursts::8 143732 # Per bank write bursts -system.physmem.perBankRdBursts::9 146555 # Per bank write bursts -system.physmem.perBankRdBursts::10 144302 # Per bank write bursts -system.physmem.perBankRdBursts::11 146237 # Per bank write bursts -system.physmem.perBankRdBursts::12 145788 # Per bank write bursts -system.physmem.perBankRdBursts::13 146277 # Per bank write bursts -system.physmem.perBankRdBursts::14 142119 # Per bank write bursts -system.physmem.perBankRdBursts::15 142542 # Per bank write bursts -system.physmem.perBankWrBursts::0 69128 # Per bank write bursts -system.physmem.perBankWrBursts::1 67452 # Per bank write bursts -system.physmem.perBankWrBursts::2 65650 # Per bank write bursts -system.physmem.perBankWrBursts::3 66298 # Per bank write bursts -system.physmem.perBankWrBursts::4 66182 # Per bank write bursts -system.physmem.perBankWrBursts::5 66379 # Per bank write bursts -system.physmem.perBankWrBursts::6 67939 # Per bank write bursts -system.physmem.perBankWrBursts::7 68869 # Per bank write bursts -system.physmem.perBankWrBursts::8 70353 # Per bank write bursts -system.physmem.perBankWrBursts::9 70986 # Per bank write bursts -system.physmem.perBankWrBursts::10 70505 # Per bank write bursts -system.physmem.perBankWrBursts::11 70955 # Per bank write bursts -system.physmem.perBankWrBursts::12 70250 # Per bank write bursts -system.physmem.perBankWrBursts::13 70819 # Per bank write bursts -system.physmem.perBankWrBursts::14 69624 # Per bank write bursts -system.physmem.perBankWrBursts::15 69092 # Per bank write bursts +system.physmem.perBankRdBursts::0 139629 # Per bank write bursts +system.physmem.perBankRdBursts::1 136292 # Per bank write bursts +system.physmem.perBankRdBursts::2 133828 # Per bank write bursts +system.physmem.perBankRdBursts::3 136435 # Per bank write bursts +system.physmem.perBankRdBursts::4 134766 # Per bank write bursts +system.physmem.perBankRdBursts::5 135151 # Per bank write bursts +system.physmem.perBankRdBursts::6 136244 # Per bank write bursts +system.physmem.perBankRdBursts::7 136309 # Per bank write bursts +system.physmem.perBankRdBursts::8 143829 # Per bank write bursts +system.physmem.perBankRdBursts::9 146501 # Per bank write bursts +system.physmem.perBankRdBursts::10 144298 # Per bank write bursts +system.physmem.perBankRdBursts::11 146295 # Per bank write bursts +system.physmem.perBankRdBursts::12 145712 # Per bank write bursts +system.physmem.perBankRdBursts::13 146106 # Per bank write bursts +system.physmem.perBankRdBursts::14 142241 # Per bank write bursts +system.physmem.perBankRdBursts::15 142471 # Per bank write bursts +system.physmem.perBankWrBursts::0 69077 # Per bank write bursts +system.physmem.perBankWrBursts::1 67426 # Per bank write bursts +system.physmem.perBankWrBursts::2 65726 # Per bank write bursts +system.physmem.perBankWrBursts::3 66343 # Per bank write bursts +system.physmem.perBankWrBursts::4 66130 # Per bank write bursts +system.physmem.perBankWrBursts::5 66357 # Per bank write bursts +system.physmem.perBankWrBursts::6 67984 # Per bank write bursts +system.physmem.perBankWrBursts::7 68878 # Per bank write bursts +system.physmem.perBankWrBursts::8 70373 # Per bank write bursts +system.physmem.perBankWrBursts::9 70997 # Per bank write bursts +system.physmem.perBankWrBursts::10 70493 # Per bank write bursts +system.physmem.perBankWrBursts::11 70981 # Per bank write bursts +system.physmem.perBankWrBursts::12 70269 # Per bank write bursts +system.physmem.perBankWrBursts::13 70812 # Per bank write bursts +system.physmem.perBankWrBursts::14 69646 # Per bank write bursts +system.physmem.perBankWrBursts::15 69069 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 533796944500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 533761847000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2246734 # Read request sizes (log2) +system.physmem.readPktSize::6 2246694 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100498 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1621551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 445207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 135727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100579 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1621644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 445219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 135704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,216 +129,237 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 48879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 49064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 49063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 49078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 49086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 49106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 49070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 49088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 49113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 49112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 49167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 49186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 49268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 49888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 50325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 51988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 52147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2077673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.074669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.977753 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 184.400722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1659880 79.89% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 227444 10.95% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 69322 3.34% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 37684 1.81% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 24960 1.20% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12074 0.58% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8168 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4452 0.21% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3374 0.16% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2842 0.14% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2038 0.10% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1716 0.08% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1451 0.07% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1190 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1071 0.05% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 949 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 909 0.04% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 717 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 682 0.03% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 676 0.03% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3081 0.15% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 420 0.02% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 289 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 203 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 186 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 219 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 499 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 143 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 125 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 127 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 94 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 128 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 92 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 97 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 82 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 82 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 62 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 59 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 52 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 72 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 47 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 62 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 51 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 51 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 39 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 48 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 40 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 42 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 28 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 34 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 44 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 23 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 29 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 27 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 28 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 28 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 9 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 25 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 18 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 19 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 22 0.00% 99.97% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 49060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 49089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 49071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 49076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 49104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 49085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 49081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 49079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 49128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 49123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 49158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 49172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 49261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 49504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 49899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 50373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 52060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 52016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 52139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see 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-system.physmem.bytesPerActivate::5376-5377 185 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 32 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 10 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 15 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 31 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 10 0.00% 99.98% # Bytes accessed per row activation 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0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 12 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 16 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 38 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 8 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 13 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 22 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 20 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 37 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 13 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 4 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 82 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2077673 # Bytes accessed per row activation -system.physmem.totQLat 32821468000 # Total ticks spent queuing -system.physmem.totMemAccLat 104059554250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11230790000 # Total ticks spent in databus transfers -system.physmem.totBankLat 60007296250 # Total ticks spent accessing banks -system.physmem.avgQLat 14612.27 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26715.53 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7872-7873 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 6 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 4 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 88 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2078319 # Bytes accessed per row activation +system.physmem.totQLat 32815970750 # Total ticks spent queuing +system.physmem.totMemAccLat 104054627000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11230535000 # Total ticks spent in databus transfers +system.physmem.totBankLat 60008121250 # Total ticks spent accessing banks +system.physmem.avgQLat 14610.15 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26716.50 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46327.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 131.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 131.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46326.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 269.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 131.96 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 269.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 131.96 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.35 # Average write queue length when enqueuing -system.physmem.readRowHits 932509 # Number of row buffer hits during reads -system.physmem.writeRowHits 336457 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.57 # Row buffer hit rate for writes -system.physmem.avgGap 159474.14 # Average gap between requests -system.physmem.pageHitRate 37.92 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.98 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 401318817 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420235 # Transaction distribution -system.membus.trans_dist::ReadResp 1420234 # Transaction distribution -system.membus.trans_dist::Writeback 1100498 # Transaction distribution -system.membus.trans_dist::ReadExReq 826499 # Transaction distribution -system.membus.trans_dist::ReadExResp 826499 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593965 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593965 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214222784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214222784 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214222784 # Total data (bytes) +system.physmem.avgWrQLen 10.33 # Average write queue length when enqueuing +system.physmem.readRowHits 932061 # Number of row buffer hits during reads +system.physmem.writeRowHits 336288 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.56 # Row buffer hit rate for writes +system.physmem.avgGap 159461.70 # Average gap between requests +system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.96 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 401350114 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420099 # Transaction distribution +system.membus.trans_dist::ReadResp 1420098 # Transaction distribution +system.membus.trans_dist::Writeback 1100579 # Transaction distribution +system.membus.trans_dist::ReadExReq 826595 # Transaction distribution +system.membus.trans_dist::ReadExResp 826595 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593966 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5593966 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214225408 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214225408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214225408 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12926153000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12926034750 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21085487000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 21084340000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 303451211 # Number of BP lookups -system.cpu.branchPred.condPredicted 249690817 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15200865 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 174297258 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161770128 # Number of BTB hits +system.cpu.branchPred.lookups 303426723 # Number of BP lookups +system.cpu.branchPred.condPredicted 249665263 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15197446 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 174885075 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161766496 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.812779 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17550277 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.498743 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17552924 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 181 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -360,6 +381,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -382,132 +424,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1067594019 # number of cpu cycles simulated +system.cpu.numCycles 1067523845 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 299164557 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2189663567 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303451211 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179320405 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435777521 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88106670 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 164181608 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 55 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 289571528 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5986152 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 969098859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.499353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.206220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 299169160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2189552617 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303426723 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179319420 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435766349 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88088140 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 164108706 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 249 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 289578845 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5989031 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 969003000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.499478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.206212 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 533321418 55.03% 55.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25465587 2.63% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39057125 4.03% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48306210 4.98% 66.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43759030 4.52% 71.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46389880 4.79% 75.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38408230 3.96% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18944401 1.95% 81.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175446978 18.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 533236766 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25461427 2.63% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39064672 4.03% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48308848 4.99% 66.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43759414 4.52% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46393042 4.79% 75.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38404129 3.96% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18940871 1.95% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175433831 18.10% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 969098859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.284238 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.051026 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 331405346 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 142029656 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405372937 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20316462 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69974458 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46022119 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2369134638 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2461 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69974458 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354905741 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 70599540 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20110 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400539970 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73059040 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2306329085 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 151792 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5017639 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60125136 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282204226 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10649650977 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9763673843 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 969003000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.284234 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.051057 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 331406137 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 141956827 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405364012 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20318148 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69957876 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46020737 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 686 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2369052643 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2441 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69957876 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354906744 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 70525275 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17150 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400533325 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73062630 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2306235389 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 151230 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5013278 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60135849 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282078057 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10649208068 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9763247621 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 575884296 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 843 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 840 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160951749 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624757210 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220789926 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85935761 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70812981 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2202388527 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 863 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018815703 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4014611 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 474721541 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1127548434 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 693 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 969098859 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.083189 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906427 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 575758127 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 542 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 539 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160926093 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624728249 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220785157 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86065935 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71218939 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2202289570 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 584 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018746767 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4010968 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 474628449 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1127376318 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 414 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 969003000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.083324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906240 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 286260209 29.54% 29.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153575867 15.85% 45.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160890539 16.60% 61.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120276383 12.41% 74.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123547545 12.75% 87.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73803065 7.62% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38319485 3.95% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9898934 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2526832 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 286111139 29.53% 29.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153618591 15.85% 45.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160911412 16.61% 61.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120366979 12.42% 74.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123454210 12.74% 87.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73801369 7.62% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38320646 3.95% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9892378 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2526276 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 969098859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 969003000 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 899836 3.76% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5555 0.02% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18259038 76.22% 80.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4790984 20.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 901909 3.77% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5511 0.02% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18267438 76.34% 80.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4754077 19.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236944304 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 924745 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236913920 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925199 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -529,90 +571,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 39 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 6 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587884247 29.12% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193062337 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587869811 29.12% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193037777 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018815703 # Type of FU issued -system.cpu.iq.rate 1.890996 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23955413 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011866 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5034700006 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2677299944 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957368325 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 522 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042770975 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64606441 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018746767 # Type of FU issued +system.cpu.iq.rate 1.891055 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23928935 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011853 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5034436167 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2677107941 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957305969 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 270 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 526 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042675566 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64599963 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138830441 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 271664 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192064 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45942881 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138801480 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 270727 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192405 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45938112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4771033 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4771665 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69974458 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33522833 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1603829 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2202389482 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7882723 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624757210 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220789926 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 801 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 479284 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 97151 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192064 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8143428 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9602990 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17746418 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988074209 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574028107 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30741494 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69957876 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33460674 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1602950 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2202290297 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7880065 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624728249 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220785157 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 522 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 477902 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97314 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192405 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8143338 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9598007 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17741345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988017569 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574014855 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30729198 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 92 # number of nop insts executed -system.cpu.iew.exec_refs 764206037 # number of memory reference insts executed -system.cpu.iew.exec_branches 238324356 # Number of branches executed -system.cpu.iew.exec_stores 190177930 # Number of stores executed -system.cpu.iew.exec_rate 1.862201 # Inst execution rate -system.cpu.iew.wb_sent 1965784253 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957368435 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295422958 # num instructions producing a value -system.cpu.iew.wb_consumers 2059236430 # num instructions consuming a value +system.cpu.iew.exec_nop 143 # number of nop insts executed +system.cpu.iew.exec_refs 764181270 # number of memory reference insts executed +system.cpu.iew.exec_branches 238318975 # Number of branches executed +system.cpu.iew.exec_stores 190166415 # Number of stores executed +system.cpu.iew.exec_rate 1.862270 # Inst execution rate +system.cpu.iew.wb_sent 1965726867 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957306072 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295394361 # num instructions producing a value +system.cpu.iew.wb_consumers 2059160488 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.833439 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629079 # average fanout of values written-back +system.cpu.iew.wb_rate 1.833501 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629089 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 479415060 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 479315418 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15200205 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 899124401 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.916391 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.718302 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15196786 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 899045124 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.916560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718243 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 410581675 45.66% 45.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193287424 21.50% 67.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72783200 8.09% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35268105 3.92% 79.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18874620 2.10% 81.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30803459 3.43% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19949403 2.22% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11408599 1.27% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106167916 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 410462230 45.66% 45.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193303811 21.50% 67.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72810970 8.10% 75.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35275316 3.92% 79.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18883906 2.10% 81.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30780783 3.42% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19963318 2.22% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11415613 1.27% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106149177 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 899124401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 899045124 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -623,97 +665,98 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106167916 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106149177 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2995444799 # The number of ROB reads -system.cpu.rob.rob_writes 4475102834 # The number of ROB writes -system.cpu.timesIdled 1153332 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98495160 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2995284619 # The number of ROB reads +system.cpu.rob.rob_writes 4474886700 # The number of ROB writes +system.cpu.timesIdled 1153694 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98520845 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.691195 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.691195 # CPI: Total CPI of All Threads -system.cpu.ipc 1.446770 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.446770 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956366000 # number of integer regfile reads -system.cpu.int_regfile_writes 1937254103 # number of integer regfile writes -system.cpu.fp_regfile_reads 112 # number of floating regfile reads -system.cpu.fp_regfile_writes 111 # number of floating regfile writes -system.cpu.misc_regfile_reads 737634139 # number of misc regfile reads +system.cpu.cpi 0.691149 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.691149 # CPI: Total CPI of All Threads +system.cpu.ipc 1.446865 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.446865 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956057659 # number of integer regfile reads +system.cpu.int_regfile_writes 1937206435 # number of integer regfile writes +system.cpu.fp_regfile_reads 98 # number of floating regfile reads +system.cpu.fp_regfile_writes 94 # number of floating regfile writes +system.cpu.misc_regfile_reads 737611057 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1604602532 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7709032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7709031 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3780837 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893445 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22984242 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22985790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856482496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856532032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856532032 # Total data (bytes) +system.cpu.toL2Bus.throughput 1604912326 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709455 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3782070 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893493 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1550 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986415 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22987965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856591488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856641088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856641088 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10472653342 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10474747083 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1293249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14769367993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14769977492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 20 # number of replacements -system.cpu.icache.tags.tagsinuse 628.438821 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289570320 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 374121.860465 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 19 # number of replacements +system.cpu.icache.tags.tagsinuse 628.273269 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289577640 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 373648.567742 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 628.438821 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306855 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306855 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 754 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 628.273269 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306774 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306774 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 756 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 726 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.368164 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579143830 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579143830 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289570320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289570320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289570320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289570320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289570320 # number of overall hits -system.cpu.icache.overall_hits::total 289570320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1208 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1208 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1208 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1208 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1208 # number of overall misses -system.cpu.icache.overall_misses::total 1208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 83080499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 83080499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 83080499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 83080499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 83080499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 83080499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289571528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289571528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289571528 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289571528 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289571528 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289571528 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 727 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.369141 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 579158465 # Number of tag accesses +system.cpu.icache.tags.data_accesses 579158465 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289577640 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289577640 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289577640 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289577640 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289577640 # number of overall hits +system.cpu.icache.overall_hits::total 289577640 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1205 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1205 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1205 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1205 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1205 # number of overall misses +system.cpu.icache.overall_misses::total 1205 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81284498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81284498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81284498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81284498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81284498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81284498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289578845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289578845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289578845 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289578845 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289578845 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289578845 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68775.247517 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68775.247517 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68775.247517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68775.247517 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67456.014938 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67456.014938 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67456.014938 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67456.014938 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -722,129 +765,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 774 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 774 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56793251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 56793251 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56793251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 56793251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56793251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 56793251 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 430 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 430 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 430 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 430 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 430 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 430 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses 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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73376.293282 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73376.293282 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency 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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233916 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233974 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233916 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233974 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62127.852349 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 76031.242207 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76023.949030 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79742.292792 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79742.292792 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 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+system.cpu.l2cache.overall_mshr_miss_latency::total 173868116500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184124 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184202 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436545 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436545 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233900 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233959 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for overall accesses 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-system.cpu.dcache.tags.age_task_id_blocks_1024::1 2397 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1056 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 635 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2403 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1057 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1355914350 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1355914350 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 489062653 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489062653 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166956698 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166956698 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1355899932 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1355899932 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 489056209 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489056209 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166956265 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166956265 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656019351 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656019351 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656019351 # number of overall hits -system.cpu.dcache.overall_hits::total 656019351 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11507496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11507496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5629349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5629349 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656012474 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656012474 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656012474 # number of overall hits +system.cpu.dcache.overall_hits::total 656012474 # number of overall hits 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cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307744962906 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307744962906 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 671447805394 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 671447805394 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 671447805394 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 671447805394 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500570149 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500570149 # number of ReadReq accesses(hits+misses) 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(read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 670926085256 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 670926085256 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 670926085256 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500562707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500562707 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673156196 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673156196 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673156196 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673156196 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032618 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032618 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 673148754 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673148754 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673148754 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673148754 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022987 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022987 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032620 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31605.732688 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31605.732688 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54667.948799 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54667.948799 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39181.529937 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39181.529937 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24597243 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3988018 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1212289 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.289917 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.230720 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31574.145430 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31574.145430 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54641.235490 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54641.235490 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39152.376435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39152.376435 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24574937 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3988182 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1212192 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65130 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.273139 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.234178 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3780837 # number of writebacks -system.cpu.dcache.writebacks::total 3780837 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3799238 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3799238 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3735904 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3735904 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3782070 # number of writebacks +system.cpu.dcache.writebacks::total 3782070 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3797817 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3797817 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3736290 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7535142 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7535142 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7535142 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7535142 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708258 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708258 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893445 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893445 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601703 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601703 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601703 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601703 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198213123757 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 198213123757 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89346986214 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 89346986214 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287560109971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 287560109971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287560109971 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 287560109971 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7534107 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7534107 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7534107 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7534107 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708681 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708681 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893492 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893492 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602173 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602173 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602173 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198180916008 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 198180916008 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89373429339 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 89373429339 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287554345347 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 287554345347 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287554345347 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 287554345347 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015400 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015400 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014264 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014264 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25714.386280 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25714.386280 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47187.526553 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47187.526553 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25708.797135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25708.797135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47200.320540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47200.320540 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 1a911e7c2..ad0230a84 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 922328096..e972d8df4 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:35:09 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:13:20 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x571a380 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index de1eec5b4..a0198a23d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu sim_ticks 861538200000 # Number of ticks simulated final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2414882 # Simulator instruction rate (inst/s) -host_op_rate 2693979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1346991470 # Simulator tick rate (ticks/s) -host_mem_usage 238968 # Number of bytes of host memory used -host_seconds 639.60 # Real time elapsed on the host +host_inst_rate 2200753 # Simulator instruction rate (inst/s) +host_op_rate 2455102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1227552560 # Simulator tick rate (ticks/s) +host_mem_usage 258852 # Number of bytes of host memory used +host_seconds 701.83 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1723073853 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9731209155 # Th system.membus.data_through_bus 8383808419 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 27330256 # nu system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 7861284498 # number of times the integer registers were read +system.cpu.num_int_register_reads 7861285293 # number of times the integer registers were read system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 05924440e..a5a5a4799 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 684ae1ce5..4d71ca666 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:38:44 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:15:41 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5333d00 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 3ce47f2c9..b8a9db006 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu sim_ticks 2391205115000 # Number of ticks simulated final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1202285 # Simulator instruction rate (inst/s) -host_op_rate 1341761 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1868329144 # Simulator tick rate (ticks/s) -host_mem_usage 247832 # Number of bytes of host memory used -host_seconds 1279.86 # Real time elapsed on the host +host_inst_rate 1176543 # Simulator instruction rate (inst/s) +host_op_rate 1313033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1828326739 # Simulator tick rate (ticks/s) +host_mem_usage 268744 # Number of bytes of host memory used +host_seconds 1307.87 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.5 # La system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -107,7 +149,7 @@ system.cpu.num_func_calls 27330256 # nu system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read +system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written |